UNIT 11 LATCHES AND FLIP-FLOPS

Transcription

1 UNIT 11 LATCHE AN FLIP-FLOP pring 2011

2 Latches and Flip-Flops 2 Contents et-eset latch Gated latch Edge-triggered flip-flop - flip-flop J-K flip-flop T flip-flop Flip-flops with additional inputs eading Unit 11

3 ecap: Two Types of witching Circuits 3 Combinational circuits (memoryless) Outputs depend only on present inputs X 1 X 2 X n... Combinational circuit F Z = F(X 1, X 2,, X n ) equential circuits (with memory) Outputs depend on both present & past inputs In general, sequential ckts = combinational ckts + memory X 1 X 2 X n... Combinational circuit F Z = F(X 1, X 2,, X n, (n-1)) (n-1) (n) Memory element

4 How to emember the Past? 4 Feedback: the output of one of the gates is connected back into the input of another gate in the ckt so as to form a closed loop e.g., inverter with feedback : How fast does the circuit oscillate? A: etermined by the propagation delay of the inverter Feedback X Oscillation at inverter output X e.g., a feedback loop with two inverters Two stable states Latch: basic memory unit (store 1 bit) Now, the values can be kept t

5 5 et-eset Latch - latch

6 et-eset (-) Latch (1/2) 6 0 P P stable =0 set : 0 1; : P P stable =1 reset : 0 1; : 1 0 P = '

7 - Latch (2/2) 7 Cross-coupled form ' ' L : eset : et = = 1 Unstable! Not allowed!! 1 0 P P '

8 Next-tate Equation 8 Timing diagram P (t) (t) (t) Operation (t +є) et to 1 Unchanged eset to 0 K-map Inputs not allowed (t)(t) (t) є є t 1 t 2 t 3 t 4 t t 1 +є t 3 +є є: 2 gate delay X X (t+є)=(t)+'(t)(t) Next-state equation: (Characteristic equation) + = +' under =0 (=1, =1 not allowed)

9 Application: witch ebouncing 9 +V 1 When a mechanical switch is opened or closed, switch contacts tend to vibrate before settling down ebounce with - latch e.g, when the switch is flipped from a to b Work only with a double throw switch ouble throw: switch between two contacts b a Pull down resistors ingle throw: switch between one contact and open witch at a Bounce at a witch between a and b ==0 unchanged witch Bounce at b at b

10 Alternative Form with NAN-Gates 10 - latch: active-low inputs for & Unchanged eset to 0 L et to 1 Inputs not allowed

11 11 Gated Latch G L

12 Gated Latch 12 G G L G L G Unchanged + = G Update + = + =G +G

13 13 Edge-Triggered Flip-Flop

14 Edge-Triggered Flip-Flops 14 Output changes are aligned with clock edges Positive (rising-edge) trigger Negative (falling-edge) trigger ymbol Truth table + FF FF ising-edge trigger Falling-edge trigger Timing diagram for falling-edge triggered FF =

15 FF ising Edge Trigger 15 Construct from 2 gated latches 1 L 1 1 P 2 2 CLK G 1 L 2 G 2 Timing diagram (setup/hold time) CLK=G 2 G 1 P L 2 hold L 1 hold L 2 hold : What s the difference between a latch and a FF? The value of a flip-flop output won t change during a clock cycle.

16 Timing of a FF (etup Time/Hold Time) 16 Because a flip-flop changes state only on the active edge of the clock, the propagation delay (t p ) of a flip-flop is the time between the active edge of the clock and the resulting change in the output. To function properly, the input to an edge-triggered flip-flop must be held at a constant value for a period of time before and after the active edge of the clock. The amount of time that must be stable before the active edge is called the setup time (t su ), and the amount of time that must hold the same value after the active edge is the hold time (t h ).

17 Minimum Clock Period 17 etermine the Minimum Clock Period Minimum clock period =(total delay of gates) + (delay of flip-flop + setup time) Example: uppose that Propagation delay of the inverter = 2ns, Propagation delay of the flip-flop = 5ns, etup time of the Flip-flop = 3ns. etermine the minimum clock period of the circuit.

18 Edge-Triggered Flip-Flop 18 Example ( cont.):

19 19 - Flip-Flop

20 - Flip Flop 20 CLK Output changes at clock edges Construct from 2 latches P Master P lave CLK Operation CLK operation 0 0 No state change 0 1 eset to 0 (after active edge) 1 0 et to 1 (after active edge) 1 1 Not allowed P t 1 t 2 t 3 t 4 t 5 Not an edge-triggered FF o not allow change while CLK is low

21 21 J-K Flip-Flop J K

22 22 J-K Flip-Flop Extension of - FF J: jump to 1 K FF J K: clear to 0 J P CLK Master lave K P J K + + = J + K J = K = 1, Toggle Unchanged Clear to 0 CLK J Jump to 1 K Latches 1 1 & 0FFs Toggle t p t p t p t 1 t 2 t 3

23 23 T Flip-Flop T

24 24 T Flip-Flop FF T T: Toggle T + =T +T =T Unchanged T Toggle t p t 4 t p Implementation t 1 t 2 t 3 K J J-K FF based: J = K = 0 Unchanged J = K = 1 Toggle + = J + K = T + T FF based: input: T + = T = T + T T Clock Clock T

25 25 FFs with Additional Inputs

26 FF with Clear and Preset 26 Use additional inputs to set FF to an initial state independent of the clock e.g., asynchronous Clear and Preset ClrN PreN CLK PreN ClrN + x x (not allowed) x x x x ,1, x 1 1 (no change) ClrN PreN t 1 t 2 t 3 t 4 Normal FF Keep whole cycle

27 FF with Clock Enable 27 We want some Flip-flops to hold existing data even though the data input may be changing Gated clock: gate the clock by clock enable (CE) CE in CLK En CLK in 0 1 CE + = = CE + CE in

28 28 ummary

29 Characteristic Equations for 29 Type + - latch or FF + = + ' ( = 0) Gated latch + = G + G FF + = -CE FF + = CE + CE' J-K FF + = J + K T FF + = T