United States Patent (19) Gardner

Transcription

1 Unied Saes Paen (19) Gardner 4) MICRPRGRAM CNTRL UNITS (7) Invenor: Peer Lyce Gardner, Tolebank, England (73) Assignee: Inernaional Business Machines Corporaion, Armonk, N.Y. 22 Filed: Nov. 13, 197 (21) Appl. No.: 631,47 30 Foreign Applicaion Prioriy Daa Nov. 27, 1974 Unied Kingdom /74 (2) U.S. Cl.... 3/172. () In. Cl.... G06F 9/16 8) Field of Search... 3, 72.; 4/1 (6) References Cied UNITED STATES PATENTS 3,4,378 10, 1968 Threadgold e al.... 3/172. 3,792,441 2/1974 Wymore e al.... 3,172. 3,913,074 10/197 Homberg e al l l ) May 3, ,930,236 12/197 Ferguson e al.... 3,172. 3,93,833 4, 1976 Shapiro... 3,172. Primary Examiner-Harvey E. Springborn Aorney, Agen, or Firm-Bernard M. Goldman 7 ABSTRACT pg, 1 A microprogram conrol uni comprises a micro program sore and an ineracive processor processing he micro insrucions issued by he microprogram sore o produce expanded sysem conrol signals, a leas some of he processing clemens of he ineracive processor being each responsible for producing a unique subse of conrol signals, no oher processing elemen being direcly involved in producing conrol signals in ha subse. The processing elemens may be self-sequencing sores, he micro insrucion supplying he iniial enry poin for each sore may be provided wih is own auomaic looping faciliy. Claims, 3 Drawing Figures ADDRESS CAL CULATR MECHANISM LCAL STRE MAN STRE MASKING UNIT MECHANISM RESULT REGISTER

2 U.S. Paen May 3, 1977 Shee 1 of 3 ADDRESS CAL CULATR MECHANISM MASKING UNIT o i. RESULT REGISTER FIG.

3 U.S. Paen (!)

4 U.S. Paen May 3, 1977 Shee 3 of 3 FWM RW M 100 TM MVM M7A rh GD. TA FW Eze, FWA BWR Hill; C. F. G. 3

5 1 MICRPRGRAM CNTRL UNITS INTRDUCTIN The presen invenion relaes o microprogram con rol unis conrolling he sequence of elemenary oper aions wihin informaion handling sysems. A subsanial percenage of all compuers buil in recen years have uilized microprogrammed conrol unis o conrol he operaions performed by a cenral processing uni (CPU) during he execuion of an in srucion. Under conrol of he microprogrammed con rol uni, he insrucion is execued by he perform ance of a sequence of elemenary operaions in a se quence of CPU cycles, each elemenary operaion being compleed wihin a single CPU cycle. During each of hese cycles, elemenary operaions are per formed under he conrol of a microinsrucion which has been accessed from he conrol uni. Generally, wihin a single CPU cycle, more han one elemenary operaion is performed (in parallel and/or in sequence wihin he cycle). Each elemenary operaion is per formed under conrol of a "micro-order'. A microin srucion hus conains a pluraliy of micro-orders, each of which is performed during one CPU cycle. A se quence of microinsrucions which execue a given funcion (for example, a sofware insrucion) make up a microprogram or micro-rouine. In mos microprogrammed sysems, microinsrucion sequencing is achieved by allocaing a porion of each microinsrucion for indicaing he address of he nex microinsrucion o be performed. The nex address porion is fed, along wih branching conrols, o he address regiser of he conrol sorage in order o selec he nex microinsrucion o be performed. In such a sysem, if a given microninsrucion is used in several differen micro-rouines, he insrucion may be sored a several differen places wihin a microprogram con rol sorage. This replicaion is one facor which ends o increase he size of he conrol uni. Anoher facor which affecs he size of he conrol uni is micro-order densiy. Wihin each microinsruc ion, various fields are allocaed o specific ypes or classes of micro-orders. If, wihin a given microinsruc ion, hen he field or fields allocaed hereo will con ain no informaion ha is of subsanial use o he sysem. The presence in he microprogram sorage of fields which, in effec, conain no informaion of value o he sysem also ends o increase he size of he conrol uni. A paricular insance of decreased efficiency in a conrol sore subsysem in connecion wih he above cied aspecs concerning addressing and branching is realized when a new sequence of microinsrucions mus be iniiaed in response o a new sysem insruc ion. During he execuion of a paricular sysem in srucion, a number of condiions may have o be full filled before execuion of he nex sysem insrucion can be iniiaed. A he conclusion of a microprogram, a paricular microinsrucion mus be decoded o indi cae ha he execuion of he presen sysem insruc ion is compleed before he operaion code of he nex insrucion can be examined and used o conrol he sar of he nex microinsrucion sequence. This re quires one complee sysem cycle o make his deermi naion and he paricular microinsrucion indicaing he end of he operaion (EP) does very lile addi ional effecive work In addiion o effecively losing a machine cycle for he purpose of deermining wheher or no an opera ion has been compleed on a paricular sysem insruc ion, addiional inefficiency is realized a he ime he operaion code of he nex insrucion o be execued is analyzed. In prior sysems, a leas a porion of he operaion code (P CDE) is uilized o form he address of he firs microinsrucion of he sequence required o perform he sysem insrucion. When ui lizing his echnique, a number of binary bi posiions mus be se aside in each microinsrucion o be effec ive only for analyzing he P CDE o provide he abiliy o perform a 64-way branch. These binary bi posiions in all oher microinsrucions are, in effec, wased. A general discussion relaing o he mehod of imple mening a microprogram conrol sorage can be found in an aricle eniled "Microprogram Conrol For Sys em/360' by S. G. Tucker, found in he IBM Sysems Journal, Vol. 6, No. 4, 1967, pages (IBM is a Regisered Trade Mark). This aricle is herewih incor poraed by his reference for is showing of he mehods of conrol sore addressing, division of microinsruc ions ino various fields, and mehods of decoding and branch decision making. In order o reduce he microinsrucion word lengh, decoding circuiry is used which, in effec, recognizes a paricular signal paern (par of a microinsrucion) and auomaically generaes a larger signal paern (he expanded or full se of conrol signals required by he processing elemens of he processor). Such decoding circuiry would have o be alered or replaced each ime any insrucion is alered in such a way ha a new conrol signal paern is required. This means ha, once defined, here is a high cos overhead involved in updaing he microinsrucion se. SUMMARY F THE INVENTIN Wih hese drawbacks in mind, he presen invenion provides a microprogram conrol uni comprising a microprogram sore and an ineracive processor pro cessing he microinsrucions issued by he micropro gram sore o generae expanded sysem conrol signals direcly, a leas some of he processing elemens of he ineracive processor producing conrol signals relaed o only a paricular processing subfuncion. The processing elemens of he ineracive mulipro cessor may comprise sores, he addressing mechanism of which are responsive o he oupu of he micropro gram sore and self-generaed conrol signals, ne advanage of such an arrangemen will become clear when one realizes ha, a any one poin in a mi croinsrucion cycle, many, if no mos, of he process ing elemens are idle. In convenional arrangemens, a processing elemen only requires a conrol signal when ha processing elemen is required o be acive, his applying equally o he processing elemens of he pro cessor as o he processing elemens of he ineracive processor. I follows ha appropriae associaion of processing elemens of he ineracive processor wih processing elemens of he processor can eliminae mos of he blank spaces required in he microprogram sores of he prior ar. The need for decoding circuiry for expanding all conrol signals produced by he con rol uni is also eliminaed. Furher, relaive o he decoding circuiry of he prior ar, he presenly proposed sysem can be alered,

6 3 wihin cerain limis, by wriing fresh daa ino he ineracive processor. DESCRIPTIN F THE DRAWINGS The presen invenion will be described furher by way of example wih reference o an embodimen hereof as illusraed in he accompanying drawings in which: FIG. 1 is a diagram of a simple convenional daa processor; FIG. 2 is a diagram of a uni used five imes in he ircuiry of FIG. 3; and FIG. 3 is a diagram of one kind of microprogram conrol uni according o he presen invenion. EMBDIMENT INTRDUCTIN For hose no so skilled in he ar o gain an apprecia ion of he invenion, here will now be given a very brief explanaion of a daa processor and how i works. Those skilled in he ar will realize ha i is well wihin heir skill o apply he invenion o heir own daa pro cessors as soon as he conrol microcode is defined for hose processors. A daa processor in is simples form comprises a local sore and a main sore ino each of which daa can be wrien and from which daa can be read, ogeher wih an arihmeic and logic uni (ALU) which can funcion o combine and aler daa in a seleced one of a limied number of ways. The basic cycle of operaion sars in one or boh of he sores wih he reading of one or more iems of daa called operands which is or are supplied o and modified by he ALU, he resulan iem of daa being reurned o and wrien ino one or oher of he sores. In order o speed processing, i is usual o incorporae a separae mechanism capable of calculaing he address of he locaions in he sores o be accessed wihou requiring he services of he ALU, ogeher wih a masking uni wih mechanism for selecing par only of an iem of daa, a holding mecha nism for reaining one operand unil a second operand wih which i is o be combined is available and a resul regiser for holding he oupu of he ALU unil he sore ino which i is o be wrien (or someimes he addressing mechanism) is available o receive i. All hese iems are linked ogeher by daa pahs which are conrolled by gaes providing a general configuraion of he kind shown in FIG. 1 and which forms no par of he presen invenion. The operaions o be performed are defined by in srucions wrien ino one or oher daa sore and he whole processor is conrolled by a microprogram con rol uni which examines an insrucion and generaes sequences of ses of signals which ravel along a disri buion nework of conducive pahs o he various ele mens of he processor, an elemen only operaing when i receives an appropriae conrol signal. Al hough he microprogram conrol uni only causes pro cessing operaions in response o insrucions, one of is asks is o cause hose insrucions o be read from he sorage locaions where hey are sored. From he above i will be apparen ha he various elemens of a processor do no have he same work rae. For example, if he gaes are regarded collecively as an elemen, hey have a high work rae since any flow of daa beween wo elemens requires he open ing of a leas one gae. n he oher hand, he holding mechanism has a low work rae since i only has o hold an operand while a second operand is produced and when only one operand is required, he holding mecha nism is no used a all. A furher poin ha mus be appreciaed is ha some elemens require no one bu a sequence of conrol signals in order o perform properly, his being paricu larly rue of he daa sores. Suppose herefore, ha he microprogram conrol uni were o generae a any insan a se of signals, some being significan (=l) and some being non-sig nifican (=0), sufficien o define he enire operaing sae of he elemens of he processor, hen he majoriy of such signals will be 0. When any change, however small, in he specrum of operaing saes is required, a whole new se of signals will have o be generaed and sill he majoriy of such signals will be 0. Wha hap pened convenionally was ha all possible ses of con rol signals ha could be required were wrien as words ino a sore (microprogram sore) and were read ou, one a a ime, in an appropriae order, a a rae equal o he rae of change of he operaing saes of he elemens of he processor. This resuled in a larger sore having o be provided o sore signals which were predominanly non-significan even hough non-opera ion of an elemen could be achieved jus as well by no sending i any signal a all. The presen invenion is based on he realizaion ha he elemens of a processor are operaive in groups and aims for he condiion in which no conrol signals a all are generaed for any group ha is for he ime being quiescen. I does his by providing a microprogram conrol uni which conains a number of processor funcion unis, ideally one processor funcional uni for each operaing group of elemens of he daa processor o be conrolled, arranged o generae conrol signals for ha group only. This means ha when he group is quiescen, so is he associaed processor funcional uni of he microprogram conrol uni bu his also means ha he microprogram funcional unis mus be iner acive a leas in so far as hose unis which are acive mus be responsible for rendering acive anoher quies cen processor funcional unis a he appropriae ime. Furher, since for any operaing group of elemens of he daa processor, he necessary subses of conrol signals end o be organized ino shor sequences some of which are repeaed, i is convenien o use for a leas some of he microprogram processor funcional unis sores which can be eiher self-addressing or which can be caused o respond o exernal addresses since hen a repeaed sequence need only be sored once. THE DETALED EMBDIMENT The microrogram conrol uni now o be described in some deail uses five such sores and so one of hose sores will be described jus in isolaion wih reference o FIG. 2 bef re he iner-relaionship of he five sores and he oher elemens of he microprogram conrol uni is described wih reference o FIG. 3. Thus, in connecion wih he sore of FIG. 2, hree conrol sig nals (X,Y,Z) for he sore iself will be referred o and he origin of hese conrol signals will no become ap paren wihou reference o FIG. 3. The uni of FIG. 2 comprises a convenional wriable, non-desrucive readou daa sore having a sorage marix 10, an inpu regiser 11, an oupu regiser 12, an address regiser 13 and an address decoder 14. The sore responds o conrol and iming signals (no shown) eiher o wrie daa from inpu regiser 11 ino, or o read daa ino oupu regiser 12 from, a word

7 S locaion in marix 10 idenified by an address in address regiser 13 when gaed ino address decoder 14. In addiion o he purely convenional aspecs of he sore, here is provided pre-addressing circuiry and pos-ou pu circuiry. The pos-oupu circuiry comprises AND gaes 1 enabled by conrol signals (X) gaing one bi posiion of he oupu regiser 12 ono line 17 and he remaining bi posiions of he oupu regiser 12 ono a muliple line daa pah 16 (shown as a single line in FIG. 2). The oupu regiser 12 is reseable by conrol signals (Y). Line 17 carries a signal (P) and branches, one branch incorporaing an inver circui 18 and an AND gae 19 enabled by (X) delayed by delay circui, hese combining o produce a single pulse each ime (X) is presen and he bi posiion of oupu regis er 12 gaed ono line 17 conains a "o". The (P) and (P) signals are fed back o he pre-addressing circuiry. The pre-addressing circuiry comprises an address inpu pah conneced o a pre-address regiser 21 reseable by conrol signal (Y). The oupu of regiser 21 is gaed by gae 22 boh o address regiser 13 and back o iself via pah 23. Gae 22 is enabled by conrol signals (Z + Pl) i.e. eiher Z = 1 or P = 1. Address regiser 13 is reseable by conrol signals (Z,+P.+P) and also connecs via pah 24 o an incremening regis er 2 in urn conneced back o address regiser 13 via gae 26 enabled by conrol signal (P). Ignoring he enry of daa ino marix 10, which is convenional, he reading operaions of his uni pro ceed as follows: a. an address on pah, and (Y), resul in he ad dress being enered ino pre-address regiser 21. b. (Z+P) enables gae 22 o ener his address ino address regiser 13 (i being also reurned o regis er 21) and a read cycle is iniiaed causing he read word o be enered ino and reained in oupu regiser 12. Also he address from regiser 13 is enered ino incremening regiser 2 and incre mened herein by a fixed amoun. c. (X) will cause he word in oupu regiser 12 o appear par on line 17 and par on pah 16. If line 17 receives "o", (P) will be generaed causing he conens of incremening regiser 2 o be gaed by gae 26 ino address regiser 13 and a read cycle o be iniiaed. If line 17 received 1, P, will be generaed and he conens of pre-addressing regiser 21 will be gaed by gae 22 ino address regiser 13 causing a read cycle o be iniiaed, he sore bi causing line 17 o be raised being someimes referred o as a "P bi" when (P) is generaed, I follows ha for a given address (W) enered on pah and a sequence (no necessarily a regular ime inervals) of conrol signals (X), he words from loca ions W, W+a, W+2a, W+3a... will be gaed ono pah 16 unil a word is gaed ou which produces a 1 on line 17, whereupon he nex word gaed ou will be ha from locaion W and he sequence will repea. When a new saring address is o be used, (Y) also reses ou pu regiser 12 so ha all of he previous read sequenc ing is removed from he uni. Thus assuming address consecuive locaions in marix 10 conain words hav ing one bis gaable ono line 17 from words (W+3a), (W-4a), (W+7a), successive (X) signals can never cause he word a locaion (W -- 4a) o be accessed since he presence of he 1 bi he in word a (W-- 3a) will cause, oher hings being equal, he nex (X) o ener he word a (W) ino regiser 12. To access he word a (W + 4a) a new address (W) on pah will be required. In fac, alhough he firs four words shown can be accessed in repeiive sequence from saring address (W) only he fifh word can be ac cessed by address (W) and address (W3) is required o access words in he sixh, sevenh and eighh locaions. I follows ha where wo such unis are conneced ogeher in such a way ha one uni generaes he (X) signals for he oher uni, he operaion of he second uni is deermined in par by he las address i received on pah, in par by is own conens, and in par by he conens of he firs uni, Pu picorially, his means ha wihou ineracive unis he mapping of wo iner relaed repeiive sequences of conrol signal fields F, and f would be ypically as follows: The firs eigh pairs of elemens is he basic combined repeiion and he map will conain as many muliples of his submap as are required. Using wo ineracive unis, one for F and he oher for f; wih he F uni generaing (X, ) signals for he f, uni, each uni having is own P hi, we now have wo maps: The foregoing char also illusraes anoher require men, namely some means for sopping or breaking ou of cycling sequences of conrol signals he arrangemen described so far will no do so of iself. Wha is required is a esing mechanism. I may be ha i is known be forehand how many cycles ae required, as in mulipli caion when he number of cycles is a funcion of he number of bis in an operand, in which case a cycle coun can be compiled and esed for equaliy o he known number, equaliy causing breakou. I may be ha breakou is required when cerain saes occur in he processor o be conrolled as for example in divi sion when he resulan from he ALU is negaive. The provision of a suiable esing mechanism can also han dle wha can be ermed "exraordinary evens' such as a deeced error, an exernally generaed inerrup as well as rouine processing ess such as "is he seleced bi 0 or l'. The preferred esing mechanism used in he microprogram conrol uni illusraed in FIG. 3 comprises a uni of he kind shown in FIG. 2, which idenifies he es, coupled o an associaive sore which performs he es receiving informaion signals from appropriae areas of he processor. Associaive sores are well known in many forms, Briefly herefore he microprogram conrol uni of FIG. 3 comprises five of he unis illusraed in FIG. 2, r

8 7 and referenced A, B, C, D and E. Uni A acs as conrol signal generaor for he gaes of a processor. Uni B acs as conrol signal generaor for he sores of he processor. Uni C acs as conrol signal informaion generaor for he masking mechanism of he processor. Uni D acs as conrol signal generaor for he ALU of he processor. Uni E in associaion wih associaive sore F comprises he esing mechanism. The saring addresses applied o he preaddressing circuiry of unis A o E are derived eiher from a micro-program sore or from he associaive sore F. The (X), (Y) and (Z) conrol signals for he unis A o E are generaed wihin he microprogram conrol uni iself. The convenion is used in FIG. 3 ha, for uni A o E, he addresses for address inpu pah are shown sup plied o he lef-hand side of he uni, he conrol sig nals (X), (Y), and (Z) are shown supplied o he op of he uni and he oupu fields are shown leaving he righ-hand side of he uni. Turning now o he microprogram conrol uni illus raed diagrammaically in FIG. 3 i will be seen ha i comprises a convenional microprogram sore M, a clock T, five unis of he kind illusraed in FIG. 2, and referenced A, B, C, D and E, an associaive sore F and a noional inerface J, he processor R o be conrolled being undersood as lying o he righ-hand side of he inerface J in FIG. 3. To simplify he descripion and undersanding of he microprogram conrol uni, sig nals will be referred o according o he following riple cypher, he line or pah for flow of such signal also being referenced by he same cypher: SURCE TYPE DESTINATIN Where he source is eiher R (he processor), M, A, B, C, D, E, F, or T; he ype is eiher Q (iming), W (address), W (conrol), X, Y or Z; he desinaion is eiher R, M, A, B, C, D, E or F. Thus FWM is an ad dress supplied by associaive sore F o microprogram sore M. Search fields for he associaive sore F are regarded as addresses W. Where a pah is common o a number of signals, i will no be referenced. Each uni produces P and P signals which are regarded as being inernal o he respecive unis and are no especially shown in FIG. 3. The microprogram uni produces an oupu word (MWA, MWB, MWC, MWD, MWE) and has is own iming mechanism abou which more will be said laer, Uni A produces an oupu word (AVA, AVM, AVR, AXB, AYB, AXC, AYC, AXD, AYD, AXE, AYE). Uni B produces an oupu word (BVR), as do uni C (CVR), uni D (DVR) and uni E (EWF). Associaive sore F produces an oupu word (FVR, FWM, FWA, FYA, FYB, FYC, FYD, FYE, FVA). Signals RWM and RWF are derived from he inerface J and Signals AVR, BVR, CVR, DVR and FVR are passed o he inerface. The clock T produces oupus (TM, TA, TF). The iming mechanism of microprogram sore M is free running for one complee cycle once iniiaed by conrol logic 100 which passes TQM from AVM = 1 unil a signal MVM = 1, MVM being derived from he iming mechanism a he end of each read cycle of he microprogram sore. Suppose TQM presens iself a imes oais and so on regularly from AVM = 1 unil MVM = 1 and sup pose i akes wo ime inervals o sele a new address in he address mechansim of he sore M, four ime inervals o decode such address, six ime inervals for 8 he sore o pass he conens of he locaion idenified S by he decoded address o he oupu of sore M, wo ime inervals for such oupu o reach unis A o E and one ime inerval for he appropriae regisers 21 of he unis (see FIG. 2) o reac. The iming cycle of he iming mechanism of he sore M will be as follows AVM = 1 o define ime o: TME FUNCTIN SIGNAL o ener new address inernal conrol signal inernal conrol signal s decode address access address inernal conrol signal. gae oupu inernal conrol signal MYA a MWA MZA, MZB, MZC, MZD, MZE 1s MVM The iming mechanism of he sore M esablishes a single funcion cycle and when compleed swiches iself off ( = MVM), afer i has sared up unis. A hrough E (T = MVA, = MVA, T = MZA, MZB, MZC, MZD, MZE). Logic 101 gaes TA o uni A as TXA in he presence of MVA or if eiher he las AVA = or if FWA =. To undersand he operaion of he microprogram conrol uni, consider a saring condiions in which elemens A, B, C, D, E, F and M are loaded, RWM exiss a he inerface, J, regisers 21 and 12 of unis B, C, D, E are empy and regiser 12 of uni A conains AVM = 1 and zeros oherwise. The nex occurring TXA (TQA gaed by logic 101) causes logic 100 o pass TM o sore M iniiaing a read cycle of sore M o access he word W(RWM) a he locaion corre sponding o RWM and, since AVA = 0, logic 101 inhib is TXA (TQA degaed) causing uni A o become quiescen. When he word a RWM is available a he oupu of sore M, he iming mechanism of sore M generaes MYA clearing regiser 21 of uni A. W(RWM) = (MWA, MWB, MWC, MWD, MWE) is gaed by he iming mechanism ino respecive regisers 21 of unis A, B, C, D and E and MVA, MZA, MZB, MZC, MZD and MZE are generaed by he iming mechanism iniiaing read cycles of unis A, B, C, D and E o place words W(MZA), W(MZB), W(MZC), W(MZD) and W(MZE) in regiser 12 of unis A, B, C, D and E, Uni A cycles because MVA gaes TQA o uni A. When W(MZA) is in regiser 12 of uni. A he nex TXA (TQA gaed by logic 101) will gae W(MZA) = (AVA, AVM, AVR, AXB, AYB, AXC, AYC, AXD, AYD, AXE, AYE) and will generally be of he form (1,0, nnnnn.nnnn,0,n,0, n,0,n,0) where n is eiher 1 or 0. AVR is saed o be an eigh bi field (nnnnn.nnn) bu his field will be of a lengh appropri ae o is funcion o be described laer. The operaions following depend on he valves of he n erms. Where n = 1 here will be acion where n = 0 here will be no acion. For example if AXB = 1 and AXC = 0, W(MZB) will be gaed and uni B will cycle once in a manner depending on he value of he P bi in W(MZB) while uni C will remain exacly as i was. Uni A will cycle since AVA is 1 and in due ime gae ou W(MZA o ar

9 9 + a) causing furher operaions o be performed. Afer normally many cycles of uni A, a word will be gaed ou of regiser 12 of uni A of he form (1,0, nnnnnnnn,0,1,0,1,0,1,0,1) reseing he conrol uni o he saring sae safe for uni A which cycles Ce noe o ener he word (0,1,nnnnnnnn,0,0,0,0,0,0,0,0) ino regiser 12 of uni A. The above operaions can be inerruped by prede ermined ses of signals (RWF, EWF) which find a mach in associaive sore F producing an oupu (FVR, FWM, FWA), FYA, FYB, FYC, FYD, FYE, FVA) of he form (nnnn.nnnn, nnnnnnnn, nnnnnnnn, 1,1,1,1,1,1) where he pah for FVA incor poraes a delay long enough for FYA o clear regiser 12 of uni A. Here again he field sizes of FVR and FWM are shown as eigh bis bu are in ac as long as hey need o be and W(FWA) (0,1, ,0,0,0,0,0,0,0,0). There may be enries in associaive sore F which will mach wih (RWF.EWF) when EWF = 0. When conneced o a convenional processor, RWM is generaed by he PCDE decoder of he processor from ha posiion of he insrucion o be execued which defines he operaion o be performed while RWF is generaed by he various overflow, underflow and error laches disribued hroughou he processor as well as by he processor regiser holding wha can be referred o as "Sysem saus' or a saemen of he curren operaing possibiliies such as which inerrups may inerrup he curren program being execued as well as o seleced poins in he daa flow. AVR is con neced o he gaes hroughou he processor. BVR is conneced o he sorage of he processor. CVR is con neced o he masking (or par daa flow selecion) mechanism of he processor, DVR is conneced o he arihmeic and logic circuiry (ALU) of he processor. I follows ha he lengh of he AVR field is deermined by he number of separaely operable gaes in he pro cessor, one bi per gae. If wo or more gaes are always opened or closed ogeher, hey only need one conrol ling bi. Thus AVR conrols he daa flow hroughou he processor bu has nohing o do wih he daa which flows, how much of he flowing daa is significan nor how such daa is o be manipulaed. Similar crieria obviously apply o BVR, CRV and DVR. FVR is used for esing purposes and he lengh of he FVR field is relaed o he number of ess o be performed. The daa loaded ino sores M and F and unis A o E depends on he insucion se of he processor. Since incremening regiser 2 is normally se o generae he "nex" address, sequenially needed words are enered ino sequenially adjacen locaions. Unis A, B, C, D and E are capable of looping, as has aleady been de scribed, so ha any of hese unis ha is needed a num ber of imes consecuively in any one operaion need only be loaded once. Since each uni conrols only one kind of funcion, is enries can be limied o he per muaions and combinaions involved in ha funcion alone. Since MWA, MWB, MWC, MWD and MWE can all be differen, funcionally aligned sequences in unis A o E need no be aligned by address. Since unis B o E only provide an oupu when gaed by AXB, AXC, AXD or AXE here is no need o fill hem wih he blank enries o preserve synchronism. Since here is no hardware decoder o expand he signal array beween he conrol uni and he processor, he insrucion se can be changed a will be enering fresh daa in sores M and F and unis A o E provided always ha he sorage accommodaion of each is large enough. To illusrae some of hese poins consider he Sys em 360 Sandard Insrucion Se now well known for many years and se ou, for example, in documen IBM X (IBM being a Regisered Trade Mark). There is provision made for 26 insrucions hough no all of he heoreically possible insrucions are used. Suppose he average number of sequenial opera ions for execuion of each insrucion was and sup pose only conrol lines (equivalen o AVR = BVR = CVR= DVR = FVR = 8) are required. To provide a microprogram sore of no sophisicaion whasoever o handle his insrucion se would require 26XX bi sorage posiions arranged as 1 words of bis per word. Consider now he firs insrucion given namely (1A) ADD. The insrucion provides hree iems, an PCDE= (1A), a firs regiser idenifier R and a second regiser idenifier R. The manner of execuing his insrucion is generally as follows: a. decode (1A) and ener he microprogram sore a he corresponding posiion. Then under conrol of he microprogram sore passing from enry o se quenial enry, proceed as follows: b. obain (R) from he insrucion regiser c. ener ha par of sorage conaining he regisers and read he word in he regiser idenified by (R) d. cause word (R) o flow o hold regiser e. obain (R) from he insrucion regiser f. ener ha par of sorage conaining he regisers and read he word in he regiser idenified by (R) g, cause word (R) o flow o he ALU and release word (R) from he hold regiser and caue i o flow o he ALU h. acuae he ALU o ADD i. obain (R) from he insrucion regiser j. ener ha par of he sorage conaining he regisers and access he regiser idenified by (R) and release he oupu of he ALU and cause i o flow o and be wrien ino regiser (R) k. access he locaion holding he locaion in sorage of he insrucion jus execued l. cause his locion idenifier o pass he ALU m. acuae he ALU o incremen his locaion ideni fier by a fixed amoun n. cause he oupu of he ALU o flow back o he locaion accessed in sep (K) o, obain he locaion idenifier from he locaion of sep (n) and access he idenifier locaion in sorage p. cause he oupu of he sorage o flow o he insruc ion regiser q. cause he PCDE par of he insrucion regiser o be gaed o he PCDE decoder. Assume he 17 saed seps (a) and (q) each repre sen one enry in he microprogram sore, his repre sening 17 x bi posiions. f hese, he field corre sponding o DVR is empy save for seps (h) and (m) providing 1 x 8 enforced empy bi posiions. The field corresponding o BVR is empy save for seps (c), (f), (j) and (o) if he curren insrucion idenifier loca ion is no in sorage or seps (c), (f), (j), (k), (n), (o) and (p) if i is, hese represening 13 x 8 or 10 x 8 enforced idle bi posiions respecively. Furher seps (k) o (q) and (a) have really nohing o do wih in srucions (1A) bu occur a he end of he execuion of each insrucion since hey represen he obaining of he nex insrucion. From jus his crude analysis of

10 11 ha is nearly he simples insrucion possible, i will e apparen ha he proposal of he presen invenion resens a considerable saving. To sar wih here will e jus one se of enries for seps (k) o (q) and no 6 repeiions of he se, he sars of he enries in ach uni being deermined by jus one word in micro rogram sore M. This sequence will be enered ino via es deermined by MWE and consequenially by WF. Uni D conains jus one enry DVR relaing o he acual execuion of his insrucion and MWD oins o his enry. CVR is no required and his con ains no enry. BVR is required for seps (c), (f), (j) nd will conain hree enries, he enry for sep (c) eing poined o by MWB. Uni A will conain Considering he ieraive secion of (1C) alone, i sars a a siuaion a which boh operands have been obained and are locaed in regisers of he processor and uses four regisers R., R., R., and R. The seps involved are, in broad erms: a. gae he muliplier (R) b. selec is highes bi c. es is highes bi d. gae R and gae R (conaining muliplicand) if es = 1 e. shif and ADD f. ener resul ino R. g: gae muliplier from R. h. shif muliplier spilling highes bi nries (Seps (b) o (j) and a linking sep); MWA 1 i. reurn shifed muliplier o Rs oining o he enry corresponding o sep (b). j. gae coun from R. WA AVM AVR AXB AYB AXC AYC AXD AYD AXE AYE STEP n 0 b nnnn C runnan inn 0. d e r 0. f T ooooooo 0 0 h 0 i nnnnnn nrn l ) j k 30 k. ADD 1 o coun Assume MWA EMWBMWC MWD MWE i, reurn coun o R, AVR = BVR = CVR = DVR =EWF = RWF = RWM = m. gae coun FWM = FVR = 8 - n. es coun, if coun= 32 (for a 32 bi muliplier) sop follows ha he oal bi posiions requires o conrol ieraion. he execuion of seps (b) o (k) ((k) being he link) is 3 in he conrol uni of FIG. 3 his ieraion requires one word in he microprogram sore, 14 words in Uni A, no words in Uni B if R, R, R and Rica be gaed x 8 - direcly as will be he case for mos processors, one SEM is 180 word in he Uni C (sep b), wo words in Uni D (seps Uni B 3 x 8 E. 24 (e) and (d)) wo words in Uni E (seps (c) and (h)) R; C and wo words in associaive sore F. ni E Sore F m x 32 = 32 m The sore F words are accessed or mached in seps m (c) and (n) respecively and he resuling oupus are used in seps (d) and (n + 1) respecively, gaing R, in sep (d) and reaccessing sore M in seps (n + 1) when I is really no fair o include ie conribuion from sore F because hese 32 m bi posiions are common o all insrucions. Thus a ruer heoreical figure is he resuls of he respecive ess so indicae. A basic microprogram sore would require 32 = 4 words in sead of he specified 22 words. A beer comparison would be wih he kind of microprogram sore which i- m = A- generaes is own nex address from is own conens 26 8 i.e., one which has a branch on condiion faciliy. Such a sore migh only need 14 enries bu now each enry where n is he number of differen values of RWF ha mus be considered. If he associaive sore F were of would comprise ( = L) bis, where L bis are re quired for inernal addressing. In his case he compari he kind which could provide seleced universal son is bewee- 14 X ( + L) bis and ( + 14X18+ mach" elemens he value of m could be grealy re- ox8 + 1x8 + 2x8 + 2x32) = 14x or a saving of luced. The wors value of m for RWF = (nnnnn.nnn) is (12 + L) x 14-4 bis. * = 26, given a wors heoreical value for "oal" In all, for such an insrucion, hree words will be 282 as opposed o 9 x =360 for he basic conven- required in sore M, one conrolling he operaion up o ional form of he microprogram sore. However, bear 60 he sar of he ieraion, one conrolling he ieraion in mind ha insrucion (1A) is one of he simples and one conrolling he operaion afer he ieraion up insrucions o execue. Consider muliply (insrucion o he ime when he linking operaion which is used C) or move (insrucion D2) boh of which incorpo- beween each insrucion execuion in invoked. ae ieraive looping, he number of ieraions in he The ypical move insrucion provides a coun and :ase of (1C) being equal o he possible number of bis wo sorage addresses and causes words from succes in he muliplier operand and, in he case of D2, equal sive sorage locaions saring a one given address o o he acual number of words o be moved and here be moved o successive sorage locaions saring a he ore, wihin reason, unlimied. oher given address, he number of words being moved

11 13 being equal o he coun, one word a a ime being moved. l will be apparen ha such an operaion is convenienly handled by a conrol uni of he kind shown in FIG. 3. Such a conrol uni can be given greaer power a lile exra cos by adding furher unis and furher spliing funcions. Take Uni B for example, which conrols he accessing of sorage. This operaion in volves wo separae maers, conrolling he funcions of he sorage as a piece of hardware and poining o he acual locaion in sorage ha is o be accessed. Conrolling sorage for a sandard processor having wo sores involves four rouines, READ and WRITE for each sore. In some cases he address poining a he locaion o be accessed comes direcly from he conrol uni and in oher cases comes from a locaion idenified by he conrol uni. Thus, providing wo unis B1 and B2, one conrolling READ and WRITE for each sore, and he oher providing he corresponding addresses eiher direcly or indirecly, will eiher decrease he number of enries needed for a sandard insrucion se, or enable a more complex insrucion se o be handled for he same number of enries. I is hough ha only unis B, C, and D can be advanageously subdivided. Hence, he microprogram conrol uni of his inven ion may be looked upon as having a ree organizaion, in which uni M is he apex of he ree and unis A, B, C, D and E are verices which are son nodes of he paren apex M. Uni F is a son verex of node E. Fur her, subdivisions of any uni will provide son nodes of ha uni. Anoher faciliy ha can be incorporaed is o enable such a conrol uni o handle wo insrucion ses by melding signals idenifying he program from which he curren insrucion comes and hence he insrucion se being handled wih MWA, MWB, MWC, MWD and MWE. For example, if he melding resuls in he high order bis of he acual address used being derived from he program idenifying signals, hen he conrol signal fields for one insrucion se will be sored in he low order half of each uni and he conrol signal fields for he oher insrucion se will be sored in he high order half of each uni. To summarize, he presen invenion provides a mi croprogram conrol uni which is effecively an inerac ive processor in ha i incorporaes unis which are in par self-conrolling and in par conrolled by oher similar unis a leas in so far as he generaion of a sequence of oupus herefrom is emporarily suspend able in response o he naure of he oupu from an oher uni. A microprogram sore is provided bu i does no produce conrol signals for he processor o be conrolled hereby. I merely esablishes enry poins ino he operaion of he several unis of he processor or, in oher words, acs as he microprogram sore of he processor. Each uni of he processor has conrol of a paricular funcion and generaes he conrol signals for ha funcion direcly, no hardward decoder being inerposed beween he uni and he processor ele mens conrolled hereby. The crieria of a funcion suiable for isolaion and for handling by is own uni 2. i. Does he funcion have a cycle of operaion which repeas during he execuion of a given insrucion, or ii. Does he funcion have cycles of operaion which are common o he execuion of a number of insruc ions, or iii. Is he funcion one which is required only from ime o ime, bu when i is required, calls for an apprecia ble number of conrol signals o be generaed? While he invenion has been paricularly shown and described wih reference o a preferred embodimen hereof, i will be undersood by hose skilled in he ar ha he foregoing and oher changes in form and deail may be made herein wihou deparing from he spiri and scope of he invenion. Wha is claimed is: 1. A microprogram conrol uni for conrolling a sysem conaining a processor, comprising microprogram sore, a pluraliy of microprogram auxiliary unis, auxiliary selecing means connecing he auxiliary unis o he microprogram sore for selecing an auxiliary uni under conrol of he microprogram sore o issue and process microinsrucion signals con ained in he auxiliary uni o hereby generae sysem conrol signals for a microprogram conrol inerface o he sysem, groups of processing elemens organized by funcion in he sysem, each auxiliary uni producing signals relaed o a paricular group of processing elemens and for iniiaing one or more oher connecing auxiliary unis o iniiae he cycling of he conneced auxil iary uni, and means connecing he auxiliary unis ogeher in he microprogram conrol uni and o an associaed one of he groups of processing elemens for in eracively iniiaing oher auxiliary unis for con rolling he groups of processing elemens. 2. A microprogram conrol uni as claimed in claim 8, in which means for coupling wo of he auxiliary unis ogeher for accessing of an associaed auxiliary uni o rese he wo auxiliary unis. 3. A microprogram conrol uni as claimed in claim 1, furher comprising, means for melding microinsrucions from an asso ciaed microprogram auxiliary uni wih processor insrucion se idenifying signals derived from he processor acuaion of he microprogram conrol uni. 4. A microprogram conrol uni as claimed in claim 1, furher including an associaive sore adaped o receive search fields from boh he processor conrolled by he micro program conrol uni and from a leas one of he auxiliary unis for generaing conrol signals effec ive o access he microprogram sore o conrol an iniiaion of anoher of he auxiliary unis o pro duce sysem conrol signals.. A microprogram conrol uni as claimed in claim 1, in which he auxiliary unis furher comprise self-addressing non-desrucive read ou daa sores, means for accessing he daa sores in response o a microinsrucion currenly being execue in he microprogram sore o produce an oupu when an exernal conrol signal is applied o he micropro gram sore, and means for deriving such exernal conrol signal from a leas one group of he processing elemens under acuaion of signals from one of he auxiliary unis. ck k xk k sk