IDT70V05S/L 8K x 8 DUAL-PORT STATIC RAM

Transcription

1 HIGH-PEED 3.3V IDT7V/ 8K x 8 DUA-PORT TATIC RAM EAD FINIH (npb) ARE IN EO PROCE - AT TIME BUY EXPIRE JUNE 1, 218 Feaures True Dual-Pored memory cells which allow simulaneous reads of he same memory locaion High-speed access Commercial: 1/2/2/3/ (max.) Indusrial: 2 (max.) ow-power operaion IDT7V Acive: 4mW (yp.) andby: 3.3mW (yp.) IDT7V Acive: 38mW (yp.) andby: 66µW (yp.) IDT7V easily expands daa bus widh o 16 bis or more using he Maser/lave selec when cascading more han Funcional Block Diagram one device M/ = VIH for BUY oupu flag on Maser M/ = VI for BUY inpu on lave Inerrup Flag On-chip por arbiraion logic Full on-chip hardware suppor of semaphore signaling beween pors Fully asynchronous operaion from eiher por TT-compaible, single 3.3V (±.3V) power supply Available in 68-pin PGA and PCC, and a 64-pin TQFP Indusrial emperaure range (-4 C o +8 C) is available for seleced speeds Green pars available, see ordering informaion OE OER CE R/W CER R/WR I/O- I/O7 I/O Conrol I/O Conrol I/OR-I/O7R, BUY ( ( BUYR A12 A Address Decoder MEMORY ARRAY Address Decoder A12R AR CE OE R/W ARBITRATION INTERRUPT EMAPHORE OGIC CER OER R/WR EM INT NOTE: 1. (MATER): BUY is oupu; (AVE): BUY is inpu. 2. BUY oupus and INT oupus are non-ri-saed push-pull. M/ EMR INTR 2942 drw Inegraed Device Technology, Inc. 1 MARCH 218 DC 2941/11

2 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Descripion The IDT7V is a high-speed 8K x 8 Dual-Por aic RAM. The IDT7V is designed o be used as a sand-alone 64K-bi Dual-Por RAM or as a combinaion MATER/AVE Dual-Por RAM for 16-bior-more word sysems. Using he IDT MATER/AVE Dual-Por RAM approach in 16-bi or wider memory sysem applicaio resuls in fullspeed, error-free operaion wihou he need for addiional discree logic. This device provides wo independen pors wih separae conrol, address, and I/O pi ha permi independen, asynchronous access for reads or wries o any locaion in memory. An auomaic power down feaure conrolled by CE permis he on-chip circuiry of each por o ener a very low sandby power mode. Fabricaed using IDT s CMO high-performance echnology, hese devices ypically operae on only 4mW of power. The IDT7V is packaged in a ceramic 68-pin PGA and PCC and a 64-pin hin quad flapack (TQFP). Pin Configuraio (1,2, 12/3/1 INDEX I/O1 I/O OE R/W EM CE VDD A12 A11 A1 A9 A8 A7 A6 I/O2 I/O3 I/O4 I/O V I/O6 I/O7 VDD V I/OR I/O1R I/O2R VDD I/O3R I/O4R I/OR I/O6R IDT7VJ J68-1 (4) Pin PCC 18 Top View () A A4 A3 A2 A1 A INT BUY V M/ BUYR INTR AR A1R A2R A3R A4R, I/O7R OER R/WR EMR CER V A12R A11R A1R A9R A8R A7R A6R AR 2941 drw 2 12/3/1 I/O1 I/O OE R/W EM CE VDD A12 A11 A1 A9 A8 A7 A6 A INDEX NOTE: 1. All VCC pi mus be conneced o power supply. 2. All GND pi mus be conneced o ground supply. 3. J68-1 package body is approximaely.9 in x.9 in x.17 in. PN64 package body is approximaely 14mm x 14mm x 1.4mm. 4. This package code is used o reference he package diagram.. This ex does no indicae orienion of he acual par-marking I/O2 I/O3 I/O4 I/O V I/O6 I/O7 VDD V I/OR I/O1R I/O2R VDD I/O3R I/O4R I/OR I/O6R I/O7R OER R/WR EMR CER 7VPF PN-64(4) 64-Pin TQFP Top View() GND A12R A11R A1R A9R A8R A7R A6R 32 AR A4 A3 A2 A1 A INT BUY V M/ BUYR INTR AR A1R A2R A3R A4R 2941 drw 3,

3 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Pin Configuraio (1,2, (con'.) 12/3/ A A4 A2 A BUY M/ INTR A1R A3R A7 A6 A3 A1 INT V BUYR AR A2R A4R AR 9 A9 4 A8 32 A7R 33 A6R 8 7 A11 6 A1 3 A9R 31 A8R VDD EM 8 A CE IDT7VG G68-1(4) 68-Pin PGA Top View() 28 A11R 26 V A1R 27 A12R OE 64 R/W 22 EMR 23 CER 3 67 I/O 66 2 OER 21 R/WR I/O1 I/O2 I/O4 V I/O7 V I/O1R VDD I/O4R I/O7R I/O3 I/O I/O6 VDD I/OR I/O2R I/O3R I/OR I/O6R A B C D E F G H J K INDEX NOTE: 1. All VCC pi mus be conneced o power supply. 2. All GND pi mus be conneced o ground supply. 3. Package body is approximaely 1.18 in x 1.18 in x.16 in. 4. This package code is used o reference he package diagram.. This ex does no indicae orienion of he acual par-marking drw 4 Pin Names CE ef Por CER R/ W R/ WR Righ Por Chip Enable Names Read/Wrie Enable OE A - A 2 OER Oupu Enable 1 AR - A12R Address I/O - I/ O7 I/ OR - I/ O7R Daa Inpu/Oupu EM EMR emaphore Enable INT INTR Inerrup Flag BUY BUYR Busy Flag M/ Maser or lave elec VDD Power (3.3v) V Ground (v) 2941 bl

4 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Truh Table I: Non-Conenion Read/Wrie Conrol 1) I npus ( Oupus C E R/ W OE EM I/ O-7 H X X H High-Z X H DATAI H H DATA X X H X High-Z O N UT Deseleced: Power-Down Wrie o Memory Read Memory Oupus Disabled Mode NOTE: 1. A A12 AR A12R 2941 bl 2 Truh Table II: emaphore Read/Wrie Conrol (1) 1) I npus ( Oupus C E R/ W OE EM I/ O-7 H H DATA H X DATAI X X O UT N Read Daa in emaphore Flag Wrie I/ O ino emaphore Flag No Allowed Mode NOTE: 1. There are eigh semaphore flags wrien o via I/O and read from I/O -I/O7. These eigh semaphores are addressed by A-A bl

5 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Absolue Maximum Raings (1) V T ymbol TERM BIA TTG I OUT Raing Terminal Volage wih Respec o GND Temperaur e Under Bias orage Temperaure DC Oupu Curren Commercial & Indusrial Uni -. o +4.6 V - o +12 o C -6 o +1 o C 2941 bl 4 NOTE: 1. resses greaer han hose lised under ABOUTE MAXIMUM RATING may cause permanen damage o he device. This is a sress raing only and funcional operaion of he device a hese or any oher condiio above hose indicaed in he operaional secio of his specificaion is no implied. Exposure o absolue maximum raing condiio for exended periods may affec reliabiliy. 2. VTERM mus no exceed VDD +.3V. Maximum Operaing Temperaure and upply Volage (1) Grade Ambien Temperaure GND NOTE: 1. This is he parameer TA. This is he "ian on" case emperaure. Recommended DC Operaing Condiio VDD Commercial O C o +7 O C V 3.3V +.3V O Indusrial -4 C o +8 O C V 3.3V +.3V ymbol VDD V P arameer T yp. Max bl Uni upply Volag e V Ground V VIH Inpu High Volag e. ( 2) 2 VDD+. 3 V Capaciance (TA = +2 C, f = 1.MHz) ymbol CIN 1) P arameer Inpu Capacianc e ( ondiio C Max. VN I Uni = 3dV 9 pf VI Inpu ow Volag e. NOTE: 1. VI> -1.V for pulse widh less han VTERM mus no exceed VDD +.3V. ( 1) -. 8 V 2941 bl 6 C OUT Oupu Capacianc e VOUT = 3dV 1 pf 2941 bl 7 NOTE: 1. This parameer is deermined by device characerizaion bu is no producion esed. 2. 3dV references he inerpolaed capaciznce when he inpu and oupu signals swich from V o 3V or from 3V o V. DC Elecrical Characerisics Over he Operaing Temperaure and upply Volage Range (VDD = 3.3V ±.3V) 7V 7V ymbol Parameer Tes Condiio M ax. Max. Uni ( 1) I VDD = 3.6V, VIN = V o VDD II npu eakage Curren 1 _ µ A I O Oupu eakage Curren VOUT = V o VDD 1 _ µ A VO Oupu ow Volag e IO = +4 _ V VOH Oupu High Volag e IOH = V NOTE: 1. A VDD < 2.V inpu leakages are undefined bl

6 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM DC Elecrical Characerisics Over he Operaing Temperaure and upply Volage Range (1) (VDD = 3.3V ±.3V) ymbol IDD IB1 IB2 IB3 IB4 Parameer Dynamic Operaing Curren (Boh Pors Acive) andby Curren (Boh Pors - TT evel Inpus) andby Curren (One Por - TT evel Inpus) Full andby Curren (Boh Pors - CMO evel Inpus) Full andby Curren (One Por - CMO evel Inpus) Tes Condiion CE = VI, Oupus Disabled EM = VIH f = fmax CER = CE = VIH EMR = EM = VIH f = fmax CE or CER = VIH Acive Por Oupus Disabled, f=fmax Boh Pors CE and CER > VDD -.2V, VI N > VDD -.2V or (4) VI N <.2V, f = EMR = EM > VDD -.2V One Por CE or CER > VDD -.2V EMR = EM > VDD -.2V VI N > VDD -.2V or VI N <.2V Acive Por Oupus Disabled, f = fmax COM' IND COM' IND COM' IND COM' IND COM' IND V ersion yp. 7VX1 ( 2) T ax M yp VX2 Com'l & Ind ( 2) T ax M yp VX2 2) T ( Max Uni 2941 bl 9a 7VX3 7VX ymbol Parameer Tes Condiion V ersion yp. ( 2) T ax. M yp. 2) T ( Max. Uni IDD Dynamic Operaing Curren (Boh Pors Acive) CE = VI, Oupus Disabled EM = VIH f = fmax COM' IND IB1 andby Curren (Boh Pors - TT evel Inpus) CER = CE = VIH EMR = EM = VIH f = fmax COM' IND IB2 andby Curren (One Por - TT evel Inpus) CE or CER = VIH Acive Por Oupus Disabled, f=fmax COM' IND IB3 Full andby Curren (Boh Pors - CMO evel Inpus) Boh Pors CE and CER > VDD -.2V, VI N > VDD -.2V or (4) VI N <.2V, f = EMR = EM > VDD -.2V COM' IND IB4 Full andby Curren (One Por - CMO evel Inpus) One Por CE or CER > VDD -.2V EMR = EM > VDD -.2V VI N > VDD -.2V or VI N <.2V Acive Por Oupus Disabled, f = fmax COM' IND bl 9b NOTE: 1. X in par number indicaes power raing ( or ) 2. VDD = 3.3V, TA = +2 C, and are no producion esed. IDD DC = 11 (Typ.) 3. A f = fmax, address and conrol lines (excep Oupu Enable) are cycling a he maximum frequency read cycle of 1/RC, and using AC Tes Condiio of inpu levels of GND o 3V. 4. f = mea no address or conrol lines change

7 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM AC Tes Condiio 3.3V 3.3V Inpu Pulse Inpu Rise/Fall Inpu Timing evels Oupu Reference Times Reference evels evels GND o 3.V 3 Max. 1.V 1.V DATAOUT BUY INT 43Ω 9Ω 3pF DATAOUT 43Ω 9Ω pf* Oupu oad Figures 1 and bl drw Figure 1. AC Oupu Tes oad Figure 2. Oupu Tes oad *Including scope and jig. (For Z, HZ, WZ, OW) Timing of Power-Up Power-Down CE ICC IB PU PD % % 2941 drw

8 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM AC Elecrical Characerisics Over he Operaing Temperaure and upply Volage Range (4) 7VX1 7VX2 Com'l & Ind 7VX2 ymbol READ CYCE RC P arameer M ax. M ax. Max. Read Cycle Time Uni AA A ddress Access Time ACE AOE C hip Enable Access Time O upu Enable Access Time ( 1 2 ( OH Z Oupu Hold from Address Change 3 O upu ow-z Time _ 3 3 ( HZ O upu High-Z Time ( PU C hip Enable o Power Up Time ( PD C hip Disable o Power Down Time ( OP emaphore Flag Updae Pulse ( OE or EM) AA emaphore Address Access ( bl 11a 7VX3 7VX ymbol READ CYCE RC P arameer M ax. Max. Read Cycle Time 3 Uni AA A ddress Access Time 3 ACE AOE C hip Enable Access Time O upu Enable Access Time ( 3 ( 2 3 OH Z Oupu Hold from Address Change 3 O upu ow-z Time _ 3 ( 3 3 HZ O upu High-Z Time ( 1 2 PU C hip Enable o Power Up Time ( PD C hip Disable o Power Down Time ( 3 OP emaphore Flag Updae Pulse ( OE or EM) 1 1 AA emaphore Address Access ( 3 NOTE: 1. Traiion is measured mv from ow or High-impedance volage wih Oupu Tes oad (Figure 2). 2. This parameer is deermined by device characerizaion bu is no producion esed. 3. To access RAM, CE = VI, EM = VIH. 4. 'X' in par number indicaes power raing ( or ) bl 11b

9 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Waveform of Read Cycles () RC ADDR CE OE (4) AA ACE (4) AOE (4) R/W DATAOUT (1) Z VAID DATA (4) OH HZ BUYOUT (3,4) BDD 2941 drw 7 NOTE: 1. Timing depends on which signal is assered las, OE or CE. 2. Timing depends on which signal is de-assered firs CE or OE. 3. BDD delay is required only in cases where he opposie por is compleing a wrie operaion o he same address locaion. For simulaneous read operaio BUY has no relaion o valid oupu daa. 4. ar of valid daa depends on which iming becomes effecive las AOE, ACE, AA or BDD.. EM = VIH

10 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM AC Elecrical Characerisics Over he Operaing Temperaure and upply Volage () 7VX1 7VX2 Com'l & Ind 7VX2 ymbol Parameer M ax. M ax. Max. Uni WRITE CYCE WC EW AW A WP WR DW Wrie Cycle Time C hip Enable o End-of-Wri e ( Address Valid o End-of-Wri e 2 A ddress e-up Time ( Wrie Pulse Widh 2 Wrie Recovery Time Daa Valid o End-of-Wri e _ HZ O upu High-Z Time ( DH 4) D aa Hold Time ( WZ ( OW WRD P 1,2,4) O upu Acive from End-of-Wri e EM EM ( Flag Wrie o Read Time Flag Conenion Window 2941 bl 12a 7VX3 7VX ymbol Parameer M ax. Max. Uni WRITE CYCE WC EW AW A WP WR DW Wrie Cycle Time C hip Enable o End-of-Wri e 3 ( 3 4 Address Valid o End-of-Wri e A ddress e-up Time 3 4 ( Wrie Pulse Widh Wrie Recovery Time Daa Valid o End-of-Wri e 2 4 _ 1 3 HZ O upu High-Z Time ( 1 2 DH 4) D aa Hold Time ( WZ W rie Enable o Oupu in High-Z W rie Enable o Oupu in High-Z ( 1 2 OW WRD P 1,2,4) O upu Acive from End-of-Wri e EM EM ( Flag Wrie o Read Time Flag Conenion Window NOTE: 2941 bl 12b 1. Traiion is measured mv from ow or High-impedance volage wih Oupu Tes oad (Figure 2). 2. This parameer is deermined by device characerizaion bu is no producion esed. 3. To access RAM, CE = VI, EM = VIH. To access semaphore, CE = VIH and EM = VI. Eiher condiion mus be valid for he enire EW ime. 4. The specificaion for DH mus be me by he device supplying wrie daa o he RAM under all operaing condiio. Alhough DH and OW values will vary over volage and emperaure, he acual DH will always be smaller han he acual OW.. X in par number indicaes power raing ( or )

11 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Timing Waveform of Wrie Cycle No. 1, R/W Conrolled Timing (1,3,,8) ADDRE OE WC (7) HZ CE or EM (9) AW (6) A WP WR R/W (7) WZ OW DATAOUT (4) (4) DW DH DATAIN 2941 drw 8 Timing Waveform of Wrie Cycle No. 2, CE Conrolled Timing (1,3,,8) WC ADDRE AW CE or EM R/W (9) (6) A EW WR DW DH DATAIN 2941 drw 9 NOTE: 1. R/W or CE mus be HIGH during all address raiio. 2. A wrie occurs during he overlap (EW or WP) of a OW CE and a OW R/W for memory array wriing cycle. 3. WR is measured from he earlier of CE or R/W (or EM or R/W) going HIGH o he end of wrie cycle. 4. During his period, he I/O pi are in he oupu sae and inpu signals mus no be applied.. If he CE or EM OW raiion occurs simulaneously wih or afer he R/W OW raiion, he oupus remain in he High-impedance sae. 6. Timing depends on which enable signal is assered las, CE, or R/W. 7. Timing depends on which enable signal is de-assered firs, CE, or R/W. 8. If OE is OW during R/W conrolled wrie cycle, he wrie pulse widh mus be he larger of WP or (WZ + DW) o allow he I/O drivers o urn off and daa o be placed on he bus for he required DW. If OE is HIGH during an R/W conrolled wrie cycle, his requiremen does no apply and he wrie pulse can be as shor as he specified WP. 9. To access RAM, CE = VI and EM = VIH. To access emaphore, CE = VIH and EM = VI. EW mus be me for eiher condiion

12 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Timing Waveform of emaphore Read afer Wrie Timing, Eiher ide (1) AA OH A-A2 VAID ADDRE VAID ADDRE AW WR ACE EM EW DW OP DATA DATAIN VAID DATA OUT VAID R/W A WP DH WRD AOE OE Wrie Cycle NOTE: 1. CE = VIH for he duraion of he above iming (boh wrie and read cycle). 2. DATAOUT VAID represens all I/O's (I/O-I/O7) equal o he semaphore value. OP Read Cycle 2941 drw 1 Timing Waveform of emaphore Wrie Conenion (1,3,4) A"A"-A2"A" MATCH IDE "A" R/W"A" EM"A" P A"B"-A2"B" MATCH IDE "B" R/W"B" EM"B" 2941 drw 11 NOTE: 1. DOR = DO = VI, CER = CE = VIH, emaphore Flag is released from boh sides (reads as ones from boh sides) a cycle sar. 2. A may be eiher lef or righ por. B is he opposie por from A. 3. This parameer is measured from R/W A or EM A going HIGH o R/W B or EM B going HIGH. 4. If P is no saisfied, he semaphore will fall posiively o one side or he oher, bu here is no guaranee which side will obain he flag

13 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM AC Elecrical Characerisics Over he Operaing Temperaure and upply Volage Range (6) ymbol B UY TIMING (M/ = VI H) BAA BDA BAC BDC AP BDD WH BUY BUY BUY BUY A D A D ccess Time from Address Mach isable Time from Address No Mached ccess Time from Chip Enable OW isable Time from Chip Enable HIGH 2) A rbiraion Prioriy e-up Time BUY D isable o Valid Daa Wrie Hold Afer B UY TIMING (M/ = VI ) WB WH BUY ) B UY 4) I npu o Wrie Wrie Hold Afer PORT-TO-PORT DEAY TIMING 7VX1 Com'l Ony 7VX2 Com'l & Ind 7VX2 P arameer M ax. M ax. Max ( ( 18 3 ( ( ) B UY ( Uni WDD DDD 1) W rie Pulse o Daa Delay 1) W rie Daa Valid o Read Daa Delay ( 3 4 ( bl 13a 7VX3 7VX ymbol B UY TIMING (M/ V = I H) P arameer M ax. Max. Uni BAA BDA BAC BUY BUY BUY A D A ccess Time from Address Mach isable Time from Address No Mached ccess Time from Chip Enable OW BDC AP BUY D isable Time from Chip Enable HIGH 2) A rbiraion Prioriy e-up Time 2 ( 3 BDD WH BUY D isable o Valid Daa Wrie Hold Afe r B UY TIMING (M/ V = I ) ) B UY ( 3 ( WB WH BUY 4) I npu o Wrie Wrie Hold Afe r ( ) B UY ( 2 2 PORT-TO-PORT DEAY TIMING WDD DDD 1) W rie Pulse o Daa Delay 1) W rie Daa Valid o Read Daa Delay ( 6 ( NOTE: 2941 bl 13b 1. Por-o-por delay hrough RAM cells from wriing por o reading por, refer o Timing Waveform of Read Wih BUY (M/ = VIH) or Timing Waveform of Wrie Wih Por- To-Por Delay (M/ = VI). 2. To eure ha he earlier of he wo pors wi. 3. BDD is a calculaed parameer and is he greaer of, WDD WP (acual) or DDD DW (acual). 4. To eure ha he wrie cycle is inhibied during conenion.. To eure ha a wrie cycle is compleed afer conenion. 6. 'X' is par number indicaes power raing ( or )

14 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Timing Waveform of Wrie wih Por-o-Por Read wih BUY (2,4,) (M/=VIH) WC ADDR"A" MATCH WP R/W"A" DW DH DATAIN "A" VAID (1) AP ADDR"B" MATCH BAA BDA BDD BUY"B" WDD DATAOUT "B" VAID DDD NOTE: 1. To eure ha he earlier of he wo pors wi. AP is ignored for M/ = VI (AVE). 2. CE = CER = VI. 3. OE = VI for he reading por. 4. If M/ = VI (AVE) hen BUY is inpu. For his example, BUY A = VIH and BUY B inpu is shown above.. All iming is he same for lef and righ pors. Por A may be eiher lef or righ por. Por B is he por opposie from Por A drw

15 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Timing Waveform of Wrie wih BUY WP R/W"A" WB BUY"B" WH (1) R/W"B" 2941 drw 13 NOTE: 1. WH mus be me for boh BUY inpu (slave) and oupu (maser). 2. BUY is assered on por B Blocking R/W B, unil BUY B goes HIGH. 3. WB is only for he slave version. Waveform of BUY Arbiraion Conrolled by CE Timing (1) (M/ = VIH) ADDR"A" and "B" ADDREE MATCH CE"A" AP CE"B" BAC BDC BUY"B" 2941 drw 14 Waveform of BUY Arbiraion Cycle Conrolled by Address Mach Timing (1) (M/ = VIH) ADDR"A" ADDRE "N" AP ADDR"B" MATCHING ADDRE "N" BAA BDA BUY"B" NOTE: 1. All iming is he same for lef and righ pors. Por A may be eiher he lef or righ por. Por B is he por opposie from A. 2. If AP is no saisfied, he BUY signal will be assered on one side or anoher bu here is no guaranee on which side BUY will be assered drw

16 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM AC Elecrical Characerisics Over he Operaing Temperaure and upply Volage Range (1) 7VX1 7VX2 Com'l & Ind 7VX2 ymbol INTERRUPT TIMING P arameer M ax. M ax. Max. Uni A WR Address e-up Time Wrie Recovery Time IN INR I nerrup e Time I nerrup Rese Time bl 14a 7VX3 7VX ymbol INTERRUPT TIMING P arameer M ax. Max. Uni A WR Address e-up Time Wrie Recovery Time IN INR I nerrup e Time I nerrup Rese Time bl 14b NOTE: 1. 'X' in par number indicaes power raing ( or )

17 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Waveform of Inerrup Timing (1) WC ADDR"A" INTERRUPT ET ADDRE (4) A WR CE"A" R/W"A" IN INT"B" 2941 drw 16 RC ADDR"B" INTERRUPT CEAR ADDRE A CE"B" OE"B" INR INT"B" 2941 drw 17 NOTE: 1. All iming is he same for lef and righ pors. Por A may be eiher he lef or righ por. Por B is he por opposie from A. 2. ee Inerrup Truh Table III. 3. Timing depends on which enable signal (CE or R/W) is assered las. 4. Timing depends on which enable signal (CE or R/W) is de-assered firs

18 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Truh Table III Inerrup Flag (1) ef Por Righ Por R/W CE OE A12-A NT I / R WR CER OER A12R-A R INTR X 1FFF X X X X X 2) X X X X X X 1FFF H ( e Righ ( Rese Righ Funcion INTR Flag X X X X ( X 1FFE X e ef INT Flag INTR Flag X 1FFE H ( 2) X X X X X Rese ef INT Flag NOTE: 1. Assumes BUY = BUYR = VIH. 2. If BUY = VI, hen no change. 3. If BUYR = VI, hen no change. 2941bl 1 Truh Table IV Address BUY Arbiraion CE CER Inpus Oupus A12-A A12R-A R BUY BUYR Funcion X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal W M ATCH ( 2) ( 2) rie Inhibi 2941 bl 16 NOTE: 1. Pi BUY and BUYR are boh oupus when he par is configured as a maser. Boh are inpus when configured as a slave. BUYX oupus on he IDT7V are push pull, no open drain oupus. On slaves he BUYX inpu inernally inhibis wries. 2. VI if he inpus o he opposie por were sable prior o he address and enable inpus of his por. VIH if he inpus o he opposie por became sable afer he address and enable inpus of his por. If AP is no me, eiher BUY or BUYR = OW will resul. BUY and BUYR oupus canno be low simulaneously. 3. Wries o he lef por are inernally ignored when BUY oupus are driving low regardless of acual logic level on he pin. Wries o he righ por are inernally ignored when BUYR oupus are driving low regardless of acual logic level on he pin. Truh Table V Example of emaphore Procuremen equence (1,2, Funcio D - D7 ef D - D7 Righ No Acion 1 1 emaphore free ef Por Wries "" o emaphore 1 ef por has semaphore oken Righ Por Wries "" o emaphore 1 No change. Righ side has no wrie access o semaphore ef Por Wries "1" o emaphore 1 Righ por obai semaphore oken ef Por Wries "" o emaphore 1 No change. ef por has no wrie access o semaphore Righ Por Wries "1" o emaphore 1 ef por obai semaphore oken ef Por Wries "1" o emaphore 1 1 emaphore free Righ Por Wries "" o emaphore 1 Righ por has semaphore oken Righ Por Wries "1" o emaphore 1 1 emaphore free ef Por Wries "" o emaphore 1 ef por has semaphore oken ef Por Wries "1" o emaphore 1 1 emaphore free aus NOTE: 1. This able denoes a sequence of evens for only one of he eigh semaphores on he IDT7V. 2. There are eigh semaphore flags wrien o via I/O and read from all I/O's (I/O-I/O7). These eigh semaphores are addressed by A-A2. 3. CE = VIH, EM = VI o access he semaphores. Refer o he emaphore Read/Wrie Conrol Truh Table bl

19 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM MATER CE Dual Por RAM BUY () BUY (R) AVE CE Dual Por RAM BUY () BUY (R) DECODER BUY () MATER CE Dual Por RAM BUY () BUY (R) AVE CE Dual Por RAM BUY () BUY (R) BUY (R) 2941 drw 18 Figure 3. Busy and chip enable rouing for boh widh and deph expaion wih IDT7V RAMs. Funcional Descripion The IDT7V provides wo pors wih separae conrol, address and I/O pi ha permi independen access for reads or wries o any locaion in memory. The IDT7V has an auomaic power down feaure conrolled by CE. The CE conrols on-chip power down circuiry ha permis he respecive por o go ino a sandby mode when no seleced (CE HIGH). When a por is enabled, access o he enire memory array is permied. Inerrups If he user chooses he inerrup funcion, a memory locaion (mail box or message cener) is assigned o each por. The lef por inerrup flag (INT) is se when he righ por wries o memory locaion 1FFE (HEX). The lef por clears he inerrup by reading address locaion 1FFE. ikewise, he righ por inerrup flag (INTR) is se when he lef por wries o memory locaion 1FFF (HEX) and o clear he inerrup flag (INTR), he righ por mus read he memory locaion 1FFF. The message (8 bis) a 1FFE or 1FFF is user-defined. If he inerrup funcion is no used, address locaio 1FFE and 1FFF are no used as mail boxes, bu as par of he random access memory. Refer o Truh Table III for he inerrup operaion. Busy ogic Busy ogic provides a hardware indicaion ha boh pors of he RAM have accessed he same locaion a he same ime. I also allows one of he wo accesses o proceed and signals he oher side ha he RAM is busy. The BUY pin can hen be used o sall he access unil he operaion on he oher side is compleed. If a wrie operaion has been aemped from he side ha receives a BUY indicaion, he wrie signal is gaed inernally o preven he wrie from proceeding. The use of BUY logic is no required or desirable for all applicaio. In some cases i may be useful o logically OR he BUY oupus ogeher and use any BUY indicaion as an inerrup source o flag he even of an illegal or illogical operaion. If he wrie inhibi funcion of BUY logic is no desirable, he BUY logic can be disabled by placing he par in slave mode wih he M/ pin. Once in slave mode he BUY pin operaes solely as a wrie inhibi inpu pin. Normal operaion can be programmed by ying he BUY pi HIGH. If desired, uninended wrie operaio can be prevened o a por by ying he BUY pin for ha por OW The BUY oupus on he IDT 7V RAM in maser mode, are push-pull ype oupus and do no require pull up resisors o operae. If hese RAMs are being expanded in deph, hen he BUY indicaion for he resuling array requires he use of an exernal AND gae. Widh Expaion wih Busy ogic Maser/lave Arrays When expanding an IDT7V RAM array in widh while using BUY logic, one maser par is used o decide which side of he RAM array will receive a BUY indicaion, and o oupu ha indicaion. Any number of slaves o be addressed in he same address range as he maser, use he BUY signal as a wrie inhibi signal. Thus on he IDT7V RAM he BUY pin is an oupu if he par is used as a maser (M/ pin = VIH), and he BUY pin is an inpu if he par used as a slave (M/ pin = VI) as shown in Figure 3. If wo or more maser pars were used when expanding in widh, a spli decision could resul wih one maser indicaing BUY on one side of he array and anoher maser indicaing BUY on one oher side of he array. This would inhibi he wrie operaio from one por for par of a word and inhibi he wrie operaio from he oher por for he oher par of he word. The BUY arbiraion, on a maser, is based on he chip enable and address signals only. I ignores wheher an access is a read or wrie. In a maser/slave array, boh address and chip enable mus be valid long enough for a BUY flag o be oupu from he maser before he acual wrie pulse can be iniiaed wih he R/W signal. Failure o observe his iming can resul in a gliched inernal wrie inhibi signal and corruped daa in he slave. emaphores The IDT7V is a fas Dual-Por 8K x 8 CMO aic RAM wih an addiional 8 address locaio dedicaed o binary semaphore flags. These flags allow eiher processor on he lef or righ side of he Dual- Por RAM o claim a privilege over he oher processor for funcio defined by he sysem designer s sofware. As an example, he semaphore can be used by one processor o inhibi he oher from accessing a porion of he Dual-Por RAM or any oher shared resource. The Dual-Por RAM feaures a fas access ime, and boh pors are

20 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM compleely independen of each oher. This mea ha he aciviy on he lef por in no way slows he access ime of he righ por. Boh pors are idenical in funcion o sandard CMO aic RAM and can be read from, or accessed, a he same ime wih he only possible conflic arising from he simulaneous wriing of, or a simulaneous READ/WRITE of, a noemaphore locaion. emaphores are proeced agai such ambiguous siuaio and may be used by he sysem program o avoid any conflics in he non-semaphore porion of he Dual-Por RAM. These devices have an auomaic power-down feaure conrolled by CE, he Dual-Por RAM enable, and EM, he semaphore enable. The CE and EM pi conrol on-chip power down circuiry ha permis he respecive por o go ino sandby mode when no seleced. This is he condiion which is shown in Truh Table II where CE and EM are boh HIGH. ysems which can bes use he IDT7V conain muliple processors or conrollers and are ypically very high-speed sysems which are sofware conrolled or sofware ineive. These sysems can benefi from a performance increase offered by he IDT7V's hardware semaphores, which provide a lockou mechanism wihou requiring complex programming. ofware handshaking beween processors offers he maximum in sysem flexibiliy by permiing shared resources o be allocaed in varying configuraio. The IDT7V does no use is semaphore flags o conrol any resources hrough hardware, hus allowing he sysem designer oal flexibiliy in sysem archiecure. An advanage of using semaphores raher han he more common mehods of hardware arbiraion is ha wai saes are never incurred in eiher processor. This can prove o be a major advanage in very high-speed sysems. How he emaphore Flags Work The semaphore logic is a se of eigh laches which are independen of he Dual-Por RAM. These laches can be used o pass a flag, or oken, from one por o he oher o indicae ha a shared resource is in use. The semaphores provide a hardware assis for a use assignmen mehod called Token Passing Allocaion. In his mehod, he sae of a semaphore lach is used as a oken indicaing ha shared resource is in use. If he lef processor wans o use his resource, i requess he oken by seing he lach. This processor hen verifies is success in seing he lach by reading i. If i was successful, i proceeds o assume conrol over he shared resource. If i was no successful in seing he lach, i deermines ha he righ side processor has se he lach firs, has he oken and is using he shared resource. The lef processor can hen eiher repeaedly reques ha semaphore s saus or remove is reques for ha semaphore o perform anoher ask and occasionally aemp again o gain conrol of he oken via he se and es sequence. Once he righ side has relinquished he oken, he lef side should succeed in gaining conrol. The semaphore flags are acive low. A oken is requesed by wriing a zero ino a semaphore lach and is released when he same side wries a one o ha lach. The eigh semaphore flags reside wihin he IDT7V in a separae memory space from he Dual-Por RAM. This address space is accessed by placing a OW inpu on he EM pin (which acs as a chip selec for he semaphore flags) and using he oher conrol pi (Address, OE, and R/W) as hey would be used in accessing a sandard aic RAM. Each of he flags has a unique address which can be accessed by eiher side hrough address pi A A2. When accessing he semaphores, none of he oher address pi has any effec. When wriing o a semaphore, only daa pin D is used. If a OW level is wrien ino an unused semaphore locaion, ha flag will be se o a zero on ha side and a one on he oher side (see Truh Table V). Tha semaphore can now only be modified by he side showing he zero. When a one is wrien ino he same locaion from he same side, he flag will be se o a one for boh sides (unless a semaphore reques from he oher side is pending) and hen can be wrien o by boh sides. The fac ha he side which is able o wrie a zero ino a semaphore subsequenly locks ou wries from he oher side is wha makes semaphore flags useful in inerprocessor communicaio. (A horough discussion on he use of his feaure follows shorly.) A zero wrien ino he same locaion from he oher side will be sored in he semaphore reques lach for ha side unil he semaphore is freed by he firs side. When a semaphore flag is read, is value is spread ino all daa bis so ha a flag ha is a one reads as a one in all daa bis and a flag conaining a zero reads as all zeros. The read value is lached ino one side s oupu regiser when ha side's semaphore selec (EM) and oupu enable (OE) signals go acive. This serves o disallow he semaphore from changing sae in he middle of a read cycle due o a wrie cycle from he oher side. Because of his lach, a repeaed read of a semaphore in a es loop mus cause eiher signal (EM or OE) o go inacive or he oupu will never change. A sequence WRITE/READ mus be used by he semaphore in order o guaranee ha no sysem level conenion will occur. A processor requess access o shared resources by aemping o wrie a zero ino a semaphore locaion. If he semaphore is already in use, he semaphore reques lach will conain a zero, ye he semaphore flag will appear as one, a fac which he processor will verify by he subsequen read (see Truh Table V). As an example, assume a processor wries a zero o he lef por a a free semaphore locaion. On a subsequen read, he processor will verify ha i has wrien successfully o ha locaion and will assume conrol over he resource in quesion. Meanwhile, if a processor on he righ side aemps o wrie a zero o he same semaphore flag i will fail, as will be verified by he fac ha a one will be read from ha semaphore on he righ side during subsequen read. Had a sequence of READ/WRITE been used iead, sysem conenion problems could have occurred during he gap beween he read and wrie cycles. I is imporan o noe ha a failed semaphore reques mus be followed by eiher repeaed reads or by wriing a one ino he same locaion. The reason for his is easily undersood by looking a he simple logic diagram of he semaphore flag in Figure 4. Two semaphore reques laches feed ino a semaphore flag. Whichever lach is firs o presen a zero o he semaphore flag will force is side of he semaphore flag OW and he oher side HIGH. This condiion will coninue unil a one is wrien o he same semaphore reques lach. hould he oher side s semaphore reques lach have been wrien o a zero in he meanime, he semaphore flag will flip over o he oher side as soon as a one is wrien ino he firs side s reques lach. The second side s flag will now say OW unil is semaphore reques lach is wrien o a one. From his i is easy o undersand ha, if a semaphore is requesed and he processor which requesed i no longer needs he resource, he enire sysem can hang up unil a one is wrien ino ha semaphore reques lach.

21 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM The criical case of semaphore iming is when boh sides reques a single oken by aemping o wrie a zero ino i a he same ime. The semaphore logic is specially designed o resolve his problem. If simulaneous requess are made, he logic guaranees ha only one side receives he oken. If one side is earlier han he oher in making he reques, he firs side o make he reques will receive he oken. If boh requess arrive a he same ime, he assignmen will be arbirarily made o one por or he oher. One cauion ha should be noed when using semaphores is ha semaphores alone do no guaranee ha access o a resource is secure. As wih any powerful programming echnique, if semaphores are misused or misinerpreed, a sofware error can easily happen. Iniializaion of he semaphores is no auomaic and mus be handled via he iniializaion program a power-up. ince any semaphore reques flag which conai a zero mus be rese o a one, all semaphores on boh sides should have a one wrien ino hem a iniializaion from boh sides o assure ha hey will be free when needed. Using emaphores ome Examples Perhaps he simples applicaion of semaphores is heir applicaion as resource markers for he IDT7V s Dual-Por RAM. ay he 8K x 8 RAM was o be divided ino wo 4K x 8 blocks which were o be dedicaed a any one ime o servicing eiher he lef or righ por. emaphore could be used o indicae he side which would conrol he lower secion of memory, and emaphore 1 could be defined as he indicaor for he upper secion of memory. To ake a resource, in his example he lower 4K of Dual-Por RAM, he processor on he lef por could wrie and hen read a zero in o emaphore. If his ask were successfully compleed (a zero was read back raher han a one), he lef processor would assume conrol of he lower 4K. Meanwhile he righ processor was aemping o gain conrol of he resource afer he lef processor, i would read back a one in respoe o he zero i had aemped o wrie ino emaphore. A his poin, he sofware could choose o ry and gain conrol of he second 4K secion by wriing, hen reading a zero ino emaphore 1. If i succeeded in gaining conrol, i would lock ou he lef side. Once he lef side was finished wih is ask, i would wrie a one o emaphore and may hen ry o gain access o emaphore 1. If emaphore 1 was sill occupied by he righ side, he lef side could undo is semaphore reques and perform oher asks unil i was able o wrie, hen read a zero ino emaphore 1. If he righ processor performs a similar ask wih emaphore, his proocol would allow he wo processors o swap 4K blocks of Dual-Por RAM wih each oher. The blocks do no have o be any paricular size and can even be variable, depending upon he complexiy of he sofware using he semaphore flags. All eigh semaphores could be used o divide he Dual-Por RAM or oher shared resources ino eigh pars. emaphores can even be assigned differen meanings on differen sides raher han being given a common meaning as was shown in he example above. emaphores are a useful form of arbiraion in sysems like disk inerfaces where he CPU mus be locked ou of a secion of memory during a rafer and he I/O device canno olerae any wai saes. Wih he use of semaphores, once he wo devices has deermined which memory area was off-limis o he CPU, boh he CPU and he I/O devices could access heir assigned porio of memory coninuously wihou any wai saes. emaphores are also useful in applicaio where no memory WAIT sae is available on one or boh sides. Once a semaphore handshake has been performed, boh processors can access heir assigned RAM segmens a full speed. Anoher applicaion is in he area of complex daa srucures. In his case, block arbiraion is very imporan. For his applicaion one processor may be respoible for building and updaing a daa srucure. The oher processor hen reads and inerpres ha daa srucure. If he inerpreing processor reads an incomplee daa srucure, a major error condiion may exis. Therefore, some sor of arbiraion mus be used beween he wo differen processors. The building processor arbiraes for he block, locks i and hen is able o go in and updae he daa srucure. When he updae is compleed, he daa srucure block is released. This allows he inerpreing processor o come back and read he complee daa srucure, hereby guaraneeing a coisen daa srucure. PORT EMAPHORE REQUET FIP FOP R PORT EMAPHORE REQUET FIP FOP D WRITE D Q Q D D WRITE EMAPHORE READ EMAPHORE READ 2941 drw 19 Figure 4. IDT7V emaphore ogic

22 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Ordering Informaion XXXXX Device Type A Power 999 peed A Package A A Process/ Temperaure Range A Blank 8 Tube or Tray Tape and Reel Blank I (1) Commercial ( C o +7 C) Indusrial (-4 C o +8 C) G Green PF G J 64-pin TQFP (PN64 or PNG64) 68-pin PGA (GU68) 68-pin PCC (P68 or PG68) Commercial Only Commercial & Indusrial Commercial Only Commercial Only Commercial Only andard Power ow Power peed in nanoseconds NOTE: 1. Conac your local sales office for Indusrial emp range in oher speeds, packages and powers. 2. Green pars available. For specific speeds, packages and powers conac your local sales office. EAD FINIH (npb) pars are in EO process. Produc Disconinuaion Noice - PDN# P V 64K (8K x 8) 3.3V Dual-Por RAM 2941 drw 2 Daashee Documen Hisory 3/11/99: Iniiaed daashee documen hisory Convered o new forma Cosmeic and ypographical correcio Page 2 and 3 Added addiional noes o pin configuraio 6/9/99: Changed drawing forma 11/1/99: Replaced IDT logo 3/1/: Added 1 & 2 speed grades Upgraded DC parameers Added Indusrial Temperaure informaion Changed ±2mV o mv in noes /26/: Page Increased sorage emperaure parameer Clarified TA parameer Page 6 DC Elecrical parameers2 changed wording from open o disabled 12/4/1: Page 2 & 3 Added dae revision o pin configuraio Page 2, 3, & 6 Changed naming convenio from VCC o VDD and from GND o V Page 6, 8, 1, 13 & 16 Removed indusrial emp for 2, 3 and from DC & AC Elecrical Characerisics Page 22 Removed indusrial emp from 2, 3 and from ordering informaion Page 1 & 22 Replaced TM logo wih logo 7/27/6: Page 1 Added green availabiliy o feaures Page 22 Added green indicaor o ordering informaion 1/23/8: Page 22 Removed "IDT" from orderable par number 6/14/12: Page 11 Correced foonoe 9 from VIN o VIH, o read "To access RAM, CE = VI and EM = VIH". Page 22 Added T& R indicaor o ordering informaion

23 IDT7V/ High-peed 3.3V 8K x 8 Dual-Por aic RAM Daashee Documen Hisory (con') 3/16/18: Produc Disconinuaion Noice - PDN# P-17-2 as ime buy expires June 1, 218 CORPORATE HEADQUARTER for AE: for Tech uppor: 624 ilver Creek Valley Road or an Jose, CA 9138 fax: DualPorHelp@id.com The IDT logo is a regisered rademark of Inegraed Device Technology, Inc