Techniques to Improve Memory Interface Test Quality for Complex SoCs

Transcription

1 Techniques o Improve Inerface Tes Quali for omplex Sos V.R. evanahan, Srinivas Vooka Texas Insrumens (Inia) Pv. L., angalore , Inia {vr, vsrinivas}@i.com Absrac Aggressive spee an volage binning schemes are wiel use in he inusr o improve he iel of Sos. or accurae bin classificaion, i is essenial ha he ess use for binning arge he wors criical/spee-limiing pahs in he esign. We have observe in man Sos ha memor inerface pahs are amongs he op criical pahs. In his paper, we propose new T schemes o improve he quali of memor inerface logic es. We also iscuss pracical challenges an propose soluions for successfull implemening ATPG on memor-inerface pahs of large Sos. Experimenal resuls on 40nm inusrial esigns show an average increase of 36% memor inerface faul coverage. max resul from proucion So silicon esablishes he effeciveness of he propose scheme for spee binning. I. INTROUTION Process variaion an esign marginaliies in eep submicron echnologies have resule in manufacure ies o exhibi a power-performance sprea boh wihin an across wafers. onsequenl, microprocessor an So manufacurers grae/bin he ies accoring o heir performance/spee, hereb improving he iel [1]. Aapive volage scaling or similar volage binning schemes have also been propose o improve he iel b conrolling he volage o shrink he power-performance sprea ue o process variaion [2]. or such binning schemes o be effecive, he choice of ess emploe o ienif he bin is criical. Opimisic binning scheme of assigning slower evices o faser bins ma resul in cusomer reurns causing increase shippe efecive Pars Per Million (PPM), while pessimisic binning scheme of assigning faser evices o slower bins ma impac iel/revenue. Traiionall, funcional ess have been effecivel use for binning [3]. Unforunael, generaing robus funcional paerns wih goo coverage is prohibiivel effor-inensive, poeniall aking man person-ears for a large So. Moreover, highl inrusive moniors are require o be embee wihin he esign o enable quick ebug an iagnosis of funcional es failures an/or o enhance he esign for improve performance [4]. or microprocessors, a goo iniial se of funcional paerns ma be reuse across muliple evices/generaions. On he oher han, such large-scale reuse is no possible for Sos. To overcome hese limiaions an o ensure fas ime-o-marke, srucural scan-base ATPG ess (ransiion faul, pah-ela faul, ec.) pose a viable an aracive alernaive for boh paern generaion an ebug. A big challenge in using scan-base ATPG ess for effecive spee binning is o es he inerface pahs of logic an IPs, specificall embee memories, wih he wors funcional iming. I has been wiel observe on man Sos ha memor inerface pahs conribue o he op spee limiing pahs [5] [7]. This is evien from he fac ha oa s Sos have large embee memor conen. or example, i was noe in [8] ha i is increasingl common o fin large ASIs wih more han 40M bis of embee SRAMs, which consiue more han 75% of oal silicon area. Embee memories are picall wrappe wih a es collar ha suppors memor IST an scan es. eicae pors are available for funcional an memor IST operaional moes. These are muliplexe (muxe) base on a es moe signal (calle IST MOE). To enable full conrollabili an observabili of inerface logic aroun memories wih ATPG, he memor inpus have eicae scan collar flip-flops o observe he inpus, an he memor oupu is conrolle b a scan flip-flop. A eicae por (calle ATPG MOE) ma be use o conrol he oupu of he memor uring ATPG, funcional an IST moes. ig. 1 shows a such collare embee memor wih various pahs exercise uring funcional an es moes. Tes pors are prefixe wih T. uncional moe inpu (oupu) pah is from (o) he funcional flip-flops, marke, hrough he funcional inerface por o (from) he memor arra. This is illusrae wih an arrow marke as uncpah. Similarl, he memor IST inpu (oupu) pah is from (o) memor IST conroller flip-flops, marke, hrough he es inerface por o (from) he memor arra. This is inicae wih an arrow marke as ISTPah in ig. 1. On he oher han, he ATPG inpu pah sars from eiher funcional or IST conroller flip-flop an erminaes a memor scan collar flip-flop. Similarl, he ATPG oupu pah sars from he memor scan collar flip-flop an erminaes a eiher funcional or IST conroller flip-flop. ATPG pah is inicae wih a ashe arrow in ig. 1. I ma be seen from he ig. 1 ha neiher he pah exercise uring memor IST nor ATPG maches wih he funcional pah. As memor IST is primaril argee o ienif efecs wihin he memor, ATPG paerns mus aiionall be use o arge he memor inerface logic. u, bpassing he memor arra an using onl he collar flops uring ATPG resuls in relaxe iming compare o rue funcional pah. I was observe in [7] ha max from ATPG pah ma be as much as 60% higher han he rue funcional pah hrough he memor arra. ATPG shoul hence, exercise he funcional pah hrough he memor arra or an ienicall ime pah. ew challenges face b moern So esigns for high quali memor inerface es are given below. (a) Tunfrienl esign pracices use o inegrae memories wihin esigns, resul in poor coverage; (b) Securi implicaions of inusrial Sos ma preven accessing he memor conen uring ATPG; (c) Similar o pah-ela ATPG, esing he criical memor inerface pah shoul also inclue esing Paper 14.3 INTERNATIONAL TEST ONERENE /11/$26.00 c 2011 IEEE

2 ig. 1. /^K W'K (a) uncional an memor IST moes /^K W'K (b) ATPG moe LEGEN uncpah - Pah uring funcional moe ISTPah - Pah uring memor IST ATPGPah - Pah uring ATPG uncional logic IST logic IST/Scan collar Pahs exercise uring memor use/es moes along he criical logic pah while simulaneousl exercising he wors memor-inernal pah. The wors-case memorinernal pah is highl ie o he memor archiecure, memor size/configuraion, process an emperaure corner. In his paper, we focus on various T schemes o improve he quali of scan-base ransiion faul ess for memorinerface pahs, aressing challenges (a) an (b). We furher resric our focus o ransiion ela fauls a he inerfaces of snchronous memories, where boh wrie an rea operaions are clocke. Aressing he challenge (c) (i.e. pah-irece memor inerface es) is ousie he scope of his paper an is a par of fuure work. The res of he paper is organize as follows. Secion II iscusses he prior work. Secion III proposes various T schemes o improve he memor-inerface es quali. Secion IV iscusses pracical challenges wih scan-base memor inerface faul es. Effeciveness of propose echniques is shown in Secion V wih experimenal resuls on inusrial Sos. Secion VI conclues he paper. II. PRIOR WORK Tesing he funcional inerface of memories b ATPG (also known as RAM-sequenial ATPG) is a well known problem. Issues in esing memor inerfaces an is effeciveness were iscusse in [5], [9]. eaile max aa correlaion beween funcional, srucural (flip-flop-o-flop ransiion faul paerns, ransiion faul paerns hrough memories, pah-ela) an memor IST paerns were analze for spee binning a processor in [5]. I was conclue ha ransiion faul paerns hrough he memor arra ha goo correlaion wih funcional paerns. In [9], clocking an oher conrollabili issues for esing logic wihin memories using scan paerns were iscusse. Rules were propose for memor esign an scan es o ease faul eecion. I was observe ha even wih numerous such rules, generaing scan paerns hrough memor remaine a challenging ask. ommercial ools, such as asscan [10] an TeraMax [11], suppor RAM-sequenial ATPG wih faul propagaion hrough memories o eec memor-inerface fauls. RAM-sequenial paern works as follows. uring scan shif, funcional scan flops ha conrol he memor are iniialize for subsequen memor operaions. u, he memor iself is no wrien o uring scan shif. uring scan capure of a RAM-sequenial paern, wrie an rea operaions are performe a-spee. All fauls are eece onl b observing he resul of he final rea operaion b capuring a he funcional scan flop. ATPG ools recommen esign guielines for conrollabili of memor clocks, enables an oher conrol signals for paern generaion, similar o [9]. These conrollabili/observabili guielines ma no be honore for complex Sos wih esigns from muliple venors ue o area an iming impac, resuling in poor coverage of memor inerface fauls. Le us consier an example of a single-por memor o beer illusrae he funcioning of RAM-sequenial ATPG. To generae a-spee ransiion a he memor oupu (sa 1 2), i is necessar o iniialize wo isinc wors of memor wih values 1 an 2 using wrie operaions an hen subsequenl rea hem a-spee. So, 5 capure ccles are require uring ATPG (i.e. < Wrie 1 A1,Wrie2 A2,Rea A1,Rea A2,apure >). We use o enoe a wrie operaion a aress A1 wih aa 1. Similarl, o eec fauls a inpus of he memor, 4 capure ccles are require (i.e. < Wrie 1 A1,Wrie2 A2,Rea A2,apure >) as i is sufficien he noaion Wrie 1 A1 o propagae onl he faul effec of he final wrie a aress A2 o a scan flop. Scan shif is expece o iniialize he carebis require uring hese (4 or 5) capure ccles. To simplif his problem for paern generaion, ATPG ools also suppor muliple loa RAM-sequenial paerns, where capure ccles of a paern are spli across muliple scan loas (or scan shifs). In oher wors, insea of one scan loa iniializing all he care-bis followe b 5 a-spee capures, muliple scan loas ma be use b he ool o generae inermeiae care-bis. A muli-loa paern wih 4 loas/shifs o eec he oupu faul ma look like: [Shif 1 ] :< Wrie 1 A1 >, [Shif 2 ] :< Wrie 2 A2 >, [Shif 3 ] :< Rea A1 >, [Shif 4 ] :< Rea A2,apure >, where each scan shif operaion is enoe b [Shif i ]. Noe ha las wo ccles nee o be a-spee for eecing 1 2 ransiion faul a he memor oupu. Two major problems wih such mulipleloa scan paerns are: (a) es ime es volume, an (b) PLL clock programming. irsl, scan shif ominaes he es ime an volume for an scan-base es. As muliple complee shif operaions now happen per paern, es ime an paern volume muliplies linearl wih he number of scan loas. Seconl, i is common for high performance esigns Paper 14.3 INTERNATIONAL TEST ONERENE 2

3 TALE I RAM-QUENTIAL ATPG ON INUSTRIAL ESIGNS esign Gae lip-flop Number of Single-loa RAM-sequenial ATPG Muli-loa RAM-sequenial ATPG coun coun memories overage Paern oun Run-ime overage Toal #Shifs Run-ime A 2.5 M 100 K % s K 20 K 20 0% 0 5hrs 39.2% hrs 2.2 M 173 K % hrs 86 % hrs 2.1 M 165 K % hrs 86.3% hrs E 1.8 M 164 K % hrs 95.5% hrs o use on-chip PLLs for ransiion faul es ha suppors programmable clock leaker circuis (such as [12]). To leak a fixe number of pulses, he clock-leaker circui ma eiher be saicall programme for a es session using JTAG (or an similar inerface) or ma be namicall be programme using scan shif, aiionall consuming scan es banwih for each paern. Wih muli-loa paerns, each shif wihin a paern ma use ifferen number of capure ccles, hereb requiring an aiional overhea of programming he clock leaker muliple imes wihin a paern. or example, he above example has firs hree shifs using 1 capure pulse, while he fourh shif uses 2 capure pulses. or he above wo reasons, muli-loa paerns are usuall avoie. In [7], we propose schemes o improve coverage an paern-coun of RAM-sequenial ATPG for snchronous memories wih scan compression. These schemes aim o eliminae he unknowns (Xs) from memor uring RAM-sequenial ATPG hereb enabling ATPG o achieve high coverage wih compression similar o ha wihou compression. As a resul, hese schemes are no effecive when he RAM-sequenial ATPG coverage is poor even wihou compression. Table I illusraes he case for his paper on 5 inusrial 40nm esigns using a commercial ATPG ool wihou scan compression wih single-loa an muli-loa paerns. The coverage repore are for ransiion faul ATPG a he funcional memor inerface using he schemes propose in [7]. rom earlier iscussion, o ge rue funcional inerface coverage, scan collar flops wihin he memor are no use for faul eecion. Insea, pahs hrough he memor are exercise. esign A has ver goo (i.e. >95%) coverage even wih single loa paern, so muli-loa ATPG was no run on esign A. esign A was also use as he escase in [7], where he problem was geing ver goo coverage wih scan compression. esigns,, an E, on he oher han, have poor coverage wih single-loa paerns. While he use of muliloa paerns achieve ver goo coverage for esign E, oher esigns sill have a coverage gap o be aresse. ollowing are he broa reasons for poor coverage on hese esigns: (a) Large (40+) levels of combinaional logic o conrol an/or observe he memories; (b) Presence of combinaional pahs beween memories (i.e. oupu of one memor riving he inpu of anoher) also referre o as memor-o-memor pahs; (c) Presence of self-feeback o he memor (i.e. oupu of a memor riving he aa an/or aress an/or conrol signals of iself); () Muli-banke memor archiecure forme b grouping muliple insances o form a large logical block wih cusom clocking. esign suffers from reasons (a) o (). Reasons (a) an (b) are applicable for esigns an, while reasons (a) o (c) are applicable for esign E. ue o he above complexiies of RAM-sequenial ATPG, a ifferen approach has also been use in lieraure o effecivel es he funcional memor inerface b eliminaing he nee for a separae RAM-sequenial ATPG. our such schemes are iscusse below. irs scheme is o re-use funcional inerface pahs for memor IST b re-using funcional PUs as a IST conroller o run IST algorihms along he funcional pah [13]. This scheme is no applicable for applicaion specific esigns ha o no have a programmable processor. Secon scheme is o share he firs sage of inpu an oupu funcional pipelines closes o he memor for IST. Here, he IST collar rives he funcional pipeline an no he memor arra [14]. or his scheme, memor IST es riviall covers he funcional inerface logic as he funcional an IST logic conrolling/observing he memor is ienical. u his scheme is highl inrusive o he esign as i requires funcional pipelines o be irecl riving he memor wihou an combinaional logic an IST muxes shoul be place before he share funcional pipeline. Thir scheme requires he memor hemselves o have mache imings beween funcional an ATPG moes, such ha capure ono (launch from) he inpu (oupu) collar flops uring ATPG has similar seup/hol (clock-o-oupu) iming requiremen as he inpu (oupu) pors for funcional access. Maching oupu imings for self-ime memories can be achieve b enabling scan wrapper flops an memor oupu using he same selfime signal (such as replica bilines [15]) as funcional operaion. Maching iming is more complex for inpus (such as aresses) ha pre-ecoe he signals when he clock is off o improve he ccle-ime [16]. Main rawback of his scheme is he complexi of maching he por imings beween funcional an ATPG moes, accurael an robusl across process variaion, aress ranges an rea/wrie margin moes. Lasl, novel T schemes were propose for asnchronous memories in [7] o eliminae RAM-sequenial ATPG b performing scan shif an capure hrough he memor wor iself, hereb maching funcional iming uring ATPG. All hese four schemes are eiher highl inrusive o he esign or require complex enhancemens o he memor esign o mach iming. In his paper, we focus on improving conrollabili an observabili of inerface logic o snchronous memories using commercial ATPG ools wih minimal So esign impac an no memor esign impac. III. IMPROVING MEMOR INTERAE TEST: U O IST PATH OR UNTIONAL INTERAE TEST In his secion, we spli he problem of esing he memor inerface ino esing memor inpu inerface an esing memor oupu inerface pahs. While he funcional pahs o he memor ma be arbiraril complex, IST pahs o he memor are usuall simple wih irec (or negligible combinaional) conrol from IST aapah or IST conroller Paper 14.3 INTERNATIONAL TEST ONERENE 3

4 Scan chain 1 LK > Scan chain 2 Launch apure Scan chain 3 LK Scan chain 1 Scan chain 2 > Launch apure Scan chain 3 /^Kl W'K apure maske/ clock-gae ig. 3. Launch-off-IST scheme ig. 2. schemes (a) Launch-on-apure, an (b) Launch-off-Shif ransiion faul scan flip-flops. We use his observaion an propose schemes ha maximall use he simpler IST pah for faul jusificaion an/or propagaion, while sill ensuring ha fauls are eece along he funcional inerface. Various echniques an heir benefis are propose below o improve he memor oupu an inpu inerface es coverage. Laer, limiaions of he propose schemes are also presene. A. Launch-off-IST: Tesing memor oupu inerface We raw an analog from LO (Launch-on-apure) an LOS (Launch-off-Shif) ransiion faul schemes [17] o escribe he propose scheme. ig. 2 (a) illusraes LO scheme where ransiion is launche uring he ccle name Launch a flop along he funcional pah (from flop A), an ig. 2 (b) illusraes LOS scheme where ransiion is launche uring he ccle name Launch a flop along he shif pah (from flop ). oh schemes help eec ransiion fauls in he fanou of b capuring a flop, bu launching ransiions along ifferen pahs. LOS has been foun o be easier for he ATPG ool ue o improve conrollabili wih shif pah. Similarl, we observe ha, o launch a ransiion a a memor oupu, he manner in which memor is iniialize or conrolle is immaerial. uncpah escribe in ig. 1 (a) illusraes he pah exercise b convenional RAM-sequenial ATPG, which is he same as he funcional use moe. We propose a scheme wherein, ransiion a he memor oupu is launche using IST pah. ig. 3 illusraes such a pah. I ma be noe ha while wries an oher conrols o he memor are generae using he IST pah (wih IST MOE se o 1), he oupu is capure onl along he funcional pah. Masking (or ignoring compares a) he IST oupu aa pah is a naive wa o ensure funcional pah faul eecion. u, masking impacs effeciveness wih scan compression. A more elegan meho of clock-gaing he IST oupu pah ma be use. We enoe such a scheme of generaing RAM-sequenial paerns for memor oupus as Launch-off-IST (LO).. apure-on-ist: Tesing memor inpu inerface Along he same lines as LO, we propose a scheme o es memor inpus b conrolling he memor using funcional pah an observing / capuring he response using he simpler IST pah. ig. 4 illusraes pah use b ATPG wih such a scheme (having IST MOE se o 0). I ma be noe ha /^Kl ig. 4. W'K apure-on-ist scheme clocks o he IST logic ha conrol he memor (an no hose ha observe he memor) ma be gae-off. However, unlike LO, his is no necessar, bu raher onl an opimizaion o reuce es power.. Inepenen IST moe conrol for memories onvenionall, esigns have one saic IST moe signal ha rives IST MOE pins of all memories. In such cases, all memories in he esign woul eiher have funcional inerface acive (IST MOE=0) or es inerface acive (IST MOE=1). We propose a scheme wherein, each memor has inepenen saic IST moe conrol. Inepenen IST moe conrols ma be generae using a eicae pipeline flop ha rives he IST MOE pin of each memor. IST moe conrol signal is mae saic b ensuring ha he pipeline flop reains/hols he las shife in value uring capure. This scheme enables some memories o be in LO moe wih simpler conrol pah, while ensuring ha he remaining memories are O moe wih simpler observe logic. Laer, we woul noe in Secion IV-A ha such a scheme is useful o improve coverage for cases wih memor-o-memor pahs. igures 5 (a) an 5 (b) illusrae he memor inerface signals for O an LO, respecivel. This iagram is applicable when a single signal rives IST MOE of all memories an also when inepenen saic IST moe conrols are presen for each memor. Propagaion of inpus from es/ist inerface is seen for LO as IST MOE is se o 1. The memor inerface signals for O is same as funcional moe (wih IST MOE = 0) wih he onl change a he locaion of capure flip-flop/observe from memor oupu. So Paper 14.3 INTERNATIONAL TEST ONERENE 4

5 /^K (a) O ig. 5. ig. 6. S S Q Q /^K (b) LO signals wih saic IST moe conrol unc / IST conrol 0 SI /^K signals for namic IST moe conrol 1 unc / IST conrol 0 SI ig A IST_MOE IST_MOE RAM_Q_MOE (a) Saic onrol unc / IST conrol 0 SI 1 b1 SI 1 b1 S S Q Q 1 unc / IST conrol 0 1 A IST_MOE IST_MOE RAM_Q_MOE (b) namic onrol Inepenen IST moe conrol generaion he problem of poor conrollabili wih a memor woul sill resul in poor faul coverage of inpu fauls wih O. We improve inpu faul conrollabili wih he following observaion. or esing he funcional inerface, onl he ransiion ha exercises he faul shoul be from he funcional pah. Oher iniializaion an propagaion can use he IST inerface. or example, in he O scheme, he funcional pah is manaor onl for he secon capure ccle (i.e Wrie A2 2) ha launches a ransiion a he memor inpu. Neiher he firs capure ccle (ha iniializes he memor inpu), nor he hir capure ccle (ha observes he ransiion), nor he las capure ccle mus be along he funcional pah. Such a scheme is illusrae in ig. 6, where funcional an IST moes namicall change uring capure ccles. A simple scheme o implemen inepenen saic an namic IST moe conrol is o use a eicae flip-flop o conrol he IST MOE signal of each memor uring RAM-sequenial ATPG, as illusrae in ig. 7. Wih saic IST moe conrol (ig. 7 (a)), he flip-flop hols he las shife value uring capure. Wih namic IST moe conrol (ig. 7 (b)), he flip-flop conrolling IST MOE is alwas in shif-onl moe. Area overhea wih inepenen IST moe conrol is one flip-flop an a mux per memor. namic IST moe conrol has an aiional phsical esign overhea, wherein he IST MOE signal shoul be iming-close for a-spee ransiion uring ATPG. I ma be noe ha IST MOE is a saic signal in funcional moe. LO an O schemes also use i as a saic conrol. The aiional aspee iming requiremen (from he conrolling scan flip-flop o he memor IST MOE signal) is purel for improve es coverage wih inepenen namic IST moe conrol scheme. Wih each memor having a eicae scan flip-flop o conrol IST MOE, he overhea ma be simplifie b placing hese flip-flops close o he respecive memor.. ine-graine IST moe conrol Inepenen IST moe conrol enables selecive use of IST pah on a per-memor basis. We furher enhance he conrollabili b enabling selecive use of IST pah a an inerface level (i.e. aa / aress / enables) wihin each memor. This is effecive for esigns wih correlae memor inpus. or example, le us consier a case where funcional aa inpu (i.e. pin) an rea-wrie enable conrols (i.e. ME / WE pins) are correlae. Inepenen IST moe conrol of Secion III- woul resul in use of IST pah for boh aa an enables or use of funcional pah for boh aa an enables. When memor inpu fauls are argee using funcional inerface, correlaion among he inpus resrics he conrollabili. Having a separae IST moe conrol for aa an enables help arge funcional inerface fauls in aa, while using he enables from IST moe an vice-versa. This can eiher be achieve b having a eicae IST moe por wihin he memor, or using exernal collar for each inerface similar o he IST muxes of ig. 1. E. resricions on he propose schemes 1) Applicabili of LO an O: Techniques propose in his secion spli he memor accesses ino wries an reas an furher, exercise non-funcional/ist pah o conrol an/or observe he memor. or hese echniques o be effecive in esing he rue funcional iming, i is necessar o honor he following assumpions. 1) Generaing conrols (such as aress an enables) for rea operaing using IST inerface oes no impac he oupu (clock-o-oupu) iming. 2) Wries performe using he funcional inerface eecs ela fauls in he inpu inerface, even if subsequen reas are one from he IST inerface. or snchronous memories, rea an wrie conrols are lache inernal o he memor. The wor corresponing o he lache aress is rea an he oupu is lache base on he clock. or self-ime memories [18], all inernal operaions are conrolle b inernall/self generae/ime clocks. Once he inpus are lache correcl wih he clock, he oupu iming oes no epen upon pah use for conrolling inpu. As a resul, assumpion #1 covers oupu inerface logic wih LO while assumpion #2 covers inpu inerface logic wih Paper 14.3 INTERNATIONAL TEST ONERENE 5

6 apure ccle: 1, 2 apure ccle: 2, 4 apure ccle: 5 apure ccle: 1, 2 apure ccle: 2, 4 apure ccle: 3 /^Kl M1: W'Kl (a) M2: /^Kl Wrie 1 A1 Wrie2 A2 Rea A1 Rea A2 Rea A1 Rea A2 Wrie A Wrie Rea A Rea W'Kl apure apure ccle: 1, 2 ig. 9. /^Kl W'Kl (a) (b) apure ccle: 2, 4 /^Kl W'Kl M1: IST.Wrie 1 A1 IST.Rea A apure M2: IST.Wrie unc.wrie A IST.Rea eecing memor-o-memor fauls wih namic IST moe ig. 8. (b) eecing ela faul a oupu of M2 M1 M2 M3 O. Hence, LO ogeher wih O compleel covers oupu an inpu funcional memor-inerface logic, wihou compromising on es quali for snchronous memories. Asnchronous-rea memories, on he oher han, have a irec fee-hrough pah from rea aress o he oupu an an ela in he rea aress woul manifes as ela a he oupu. To eec ela fauls in he oupu pah, i is necessar ha inpu / rea aress also exercises he funcional pah. Hence, asnchronous memories o no honor he above assumpions. IV. PRATIAL HALLENGES AN SOLUTIONS ommon esign scenarios ha pose challenges o memor inerface es were menione owars he en of Secion II. This secion provies more eails on hese challenges an soluions o aress hem. A. Improving esabili of memor-o-memor pahs The firs challenge aresse is he presence of pure combinaional pahs beween memories an combinaional selffeeback o he memories. An example for a memor-omemor pah is illusrae in ig. 8 (a). or his case, le us consier he problem of eecing ela fauls a he oupu of memor M2. This woul require wo reas (for a ransiion a oupu of M2) followe b a capure ono funcional flop. The funcional conrols for rea a memor M2 is generae from M1. This causes reas a M2 o require corresponing wries an reas from M1. Hence, a capure eph of 8 is require for esing ela efecs a oupu of M2, using funcional inerface as escribe in ig. 8 (b). Similarl, wih combinaional feeback from he memor oupu back o iself, Xs (unknowns) from he memor oupu prevens iniializaion of memor inpu. To break such X feeback, an aiional consrain ha shoul be me is o iniialize he memor oupu from he las scan shif operaion. One such mechanism o iniialize he oupu was propose in [7] b laching he memor oupu inernal o he memor. LEGEN /^ W>KlK /^ ig. 10. eecing memor-o-memor fauls wih namic IST moe for 3 back-o-back memories 1) Use of LO an O: I is worh noing ha LO ma be use o eec fauls a he oupu of M2 b using he IST inerface wih jus 5 capure ccles, hereb avoiing he complex memor-o-memor pah. Similarl, o eec fauls a oupu of M1 an inpu of M2, a capure eph of 7 is require. In his case, LO a M1 an O a M2 are simulaneousl applie (refer ig. 9 (a)). This ma be enable b inepenen IST moe for each memor (refer Secion III-) an saic conrol is sufficien for his case. u, his woul sill require capure eph of 7. using he inepenen namic IST moe conrol (also in Secion III-), we no onl opimize conrollabili an observabili furher, bu also reuce he capure eph o 5 (refer ig. 9 (b)). An imporan observaion o be mae is ha he propose scheme is scalable. When wo memories are back-o-back, we saw earlier in his secion ha 8 capure ccles are require o es he oupu of he las memor. Exening his furher, for a case wih 3 back-o-back memories (refer ig. 10), capure ephs of 10 an 11 are require o eec fauls a he inpu an oupu, respecivel, of he las memor - M3. u, wih he propose scheme, even wih N memories back-o-back (such as ig. 10 wih N=3), eecing memor fauls alwas reuces o he wors case of jus wo back-o-back memories, wih he maximum capure eph of onl 5. 2) Selecive use of memor bpass pah: I was seen in Secion II ha maching funcional an ATPG moe iming eliminaes he nee for RAM-sequenial ATPG. Maching he iming for memor oupus is relaivel simpler han ha of he inpus. Le us consier a case wih oupus of all or selece memories having mache funcional an ATPG moe imings. or such memories, he ATPG MOE signal Paper 14.3 INTERNATIONAL TEST ONERENE 6

7 apure ccle: 1, 3 apure ccle: 2 apure ccle: 1, 3 apure ccle: 4 ank A ank /^Kl W'Kl apure ccle: 2 apure ccle: 1, 3 /^Kl W'Kl LK LK / 2 (a) ig. 11. eecing memor-o-memor fauls wih selecive memor bpass LK ma be assere o selec he scan wrapper flops o rive he oupus wih he same funcional iming, wihou loss in es quali. Wih ATPG MOE of M1 assere, esing memoro-memor pahs now reuces o a problem of esing jus one memor (M2) an he propose O scheme wih capure eph of 4 is sufficien o arge he inpu inerface of M2 (refer ig. 11). Such a scheme requires inepenen conrol of ATPG MOE of each memor. This woul also incur an aiional overhea of one flop an a mux per memor ha conrols ATPG MOE. There is no aiional iming requiremen as ATPG MOE conrol is a saic signal ha oes no swich a-spee uring capure ccles. I ma also be noe ha selecive use of memor bpass pah provies an elegan an effecive wa o resric he Xs generae uring RAM sequenial ATPG from non-argee memories, especiall asnchronous memories.. Enabling RAM-sequenial ATPG for secure evices Securi is an imporan aspec for consumer an mobile evices, where high es quali wih improve conrollabili an observabili poses a significan risk. Tes challenges for secure evices were iscusse in [19]. Embee memories ha sore criical cusomer aa are a primar arge for proecion agains loss of informaion via he es/ist inerface. In his conex, ensuring securi wih RAM-sequenial ATPG poses an imporan challenge. Le us consier such a secure evice wih a se of embee memories being marke as secure memories ha conain criical aa ha canno be compromise. Such a evice shoul picall have a mechanism o clear he memor conen before enering he ram sequenial es moe so ha a poenial hacker oes no use RAM-sequenial ATPG as a mechanism o access he secure aa. Special care-abous exis for evices ha require ssem/fiel es when compare o evices ha require onl manufacuring es. or evices ha require onl manufacuring es, in absence of reliable clearing mechanism, an memor IST es ma be run o re-iniialize all he memories an hereb erasing he memor conen. Running memor IST es o clear memor conen ma no be feasible uring ssem/fiel es. In such cases, RAM-sequenial ATPG nee o be isable on hose memories. Selecive memorbpass mechanism iscusse in previous secion ma be use o isable RAM-sequenial ATPG for secure memories, b bpassing he memor arra an using onl he scan collar. To scheule es for Sos wih boh secure an non secure esigns, inepenen ATPG MOE conrol for each esign ma be use o enable memor inernal access for selec / nonsecure esigns, while bpassing all memories wihin oher / LK / 2 ig. 12. Scan capure / RAM access (b) A sample muli-banke configuraion secure esigns. This can furher be exene wihin a esign, if boh secure an non-secure memories are presen.. Hanling muli-bank slow-spee memories A large amoun of on-chip level-wo cache is common on microprocessors an large Sos [20]. These use large (or muli-banke) embee memories an operae a slow-spee clock compare o he esign ssem clock. locks o hese memories ma be hanle as muli-ccle pahs wih respec o he fas esign ssem clock. On man Sos, inerface o hese memories en up being iming criical. Tesing muli-ccle pahs is no irecl suppore b he commercial ATPG ools. u, his ma be aresse inirecl using he flexibili available wih an programmable on-chip clock leaker circuir (such as [12]) o leak/release cusom clocking sequences ha mimic rue funcional operaion. ig. 12 (a) escribes one such scenario of ual-banke memor operaing a half he esign frequenc. The clocking waveform use for esing is inicae in ig. 12 (b). I ma be noe ha he ssem clock of he esign (LK) is pulse ever alernae ccles o have he same frequenc uring capure as he slower clock (LK/2). I ma be noe here ha shif for boh memor an funcional flip-flops happen a he same spee shif clock. Pah from each funcional flop o he memor is a wo-ccle pah. he isribuing he operaions across each of hese banks an pipelining he access, he hroughpu a he esign ssem clock frequenc ma sill be achieve. Generaing clocking sequence for he ssem clock wih pulsing onl alernae ccles nee o be suppore b he esign, possibl using echniques such as programmable clock leakers [12]. V. EXPERIMENTAL RESULTS To illusrae he benefi of propose schemes, we implemene hese echniques on few inusrial 40nm esigns (escribe in Table I) an a large 40nm TI So an generae es paerns using commercial ATPG ools. I is worh noing ha he propose T schemes are generic an are full suppore b commercial ATPG ools. As esign A ha ver goo RAM-sequenial coverage even wihou he propose scheme, propose schemes were implemene an evaluae onl on esigns o E. We use convenional RAM-sequenial Paper 14.3 INTERNATIONAL TEST ONERENE 7

8 TALE II IMPAT O LAUNH-O-IST esign onv. oupu Single-loa LO RAM-sequenial ATPG Ram-seq. overage overage Paern oun Run-ime 0% 0% 0 2hrs 69.5% 90.9% hrs 87.2% 94.1% hrs E 4.9% 73.4% hrs TALE III IMPAT O APTURE-ON-IST esign onv. inpu Single-loa O RAM-sequenial ATPG Ram-seq. overage overage Paern oun Run-ime 0% 1.4% 4 1hrs 92.5% 92.8% hrs 89.6% 91.3% hrs E 36.6% 36.7% hrs E e / /^ / /^ ATPG o enoe he RAM-sequenial scheme of [7]. overage repore here are for he fauls onl in he memor-inerface logic using ransiion faul moel. We firs begin wih simple LO an O resuls an hen presen furher enhancemens. ig are-bis require o reach convenional RAM-sequenial coverage A. Impac of LO an O Table II compares memor oupu inerface faul coverage on esigns o E wih respec o he convenional RAMsequenial ATPG from commercial ATPG ool ha uses funcional pah for boh inpu an oupu inerface as in ig. 1. I ma be noe from he Table ha excep esign, all oher esigns have significan improvemen in coverage. Table III compares he memor inpu inerface faul coverage for esigns o E wih respec o he convenional RAMsequenial ATPG from commercial ATPG ool, similar o ha of Table II. While coverage improves for esigns an, here is no improvemen in coverage for esigns an E. The oupu an inpu coverages wih convenional scheme were exrace from he single-loa ATPG run of Table I. Runimes wih LO an O are comparable wih convenional runs, while paern couns are much lesser.. Impac of inepenen IST moe conrol Table IV shows he impac of inepenen IST moe conrol. I ma be noe ha comparison of inepenen IST moe conrol scheme is one wih respec o propose LO an O schemes an no wih convenional RAM-sequenial ATPG. aa for saic IST moe conrol is shown wihin parenhesis below he corresponing aa for namic conrol. I ma also be noe ha while saic conrol improves he coverage over LO an O, namic conrol significanl improves he coverage furher. Run-imes reuce significanl wih inepenen namic conrol scheme while paern coun remains similar o simple LO/O scheme. overage for esign an E is poor even wih inepenen namic IST conrol. Wha separaes esigns an E from ohers is he presence of highl correlae self-feeback, which is argee b fine-graine IST moe conrol. To furher illusrae he benefi of inepenen namic IST moe conrol, we compare he oal number of carebis require b inepenen namic an saic IST moe conrol schemes o reach he convenional RAM-sequenial coverage for esigns, an E. This provies an iea of how efficienl various schemes achieve a paricular coverage overage (%) ig. 14. E esigns Overall coverage resuls wih propose schemes onvenional LO+O Inep. n. IST moe conrol ine-graine IST moe conrol arge. esign was no chosen as he convenional RAMsequenial coverage was 0%. ig. 13 shows 2X o 6X reucion in care-bi coun, wih an average reucion of 3X using he inepenen namic IST moe conrol scheme compare o he convenional RAM-sequenial ATPG. Inepenen saic IST moe conrol provies comparaivel lesser benefi (i.e. 10% o 5X) care bi reucion over he convenional scheme.. Impac of fine-graine IST moe conrol or esigns an E having poor coverage wih inepenen namic IST moe conrol, fine-graine IST moe conrol was implemene wih each se of inerface pors (such as aa, aress an enables) having a separae IST moe mux conrol. Table V shows he resuls wih such an implemenaion, where esigns an E have significan coverage improvemen. As in he earlier able, he reference for comparison here is no wih he convenional RAM-sequenial coverage, insea i is wih respec o he above inepenen namic IST moe conrol. I ma be noe from he able ha wih fine-graine conrol scheme, boh esign E an esign sees more han 20% improvemen in overall coverage.. Overall impac While he ables provie coverages, paern couns an runimes for inpu an oupu inerfaces separael, we consoliae Paper 14.3 INTERNATIONAL TEST ONERENE 8

9 TALE IV IMPAT O INEPENENT IST MOE ONTROL Inpu memor inerface - single loa ATPG Oupu memor inerface - single loa ATPG esign O Inepenen namic (saic) IST moe conrol LO Inepenen namic (saic) IST moe conrol overage overage Paern oun Run-ime overage overage Paern oun Run-ime 1.4% 37% hrs 0% 27.4% 4 1hrs (1.5%) (6) (1 hrs) (0%) (0) (1 hrs) 92.8% 95.7% hrs 90.9% 99.9% hrs (93.73) (826) (23.5 hrs) (99.8%) (161) (1 hrs) 91.3% 92.3% hrs 94.1% 99.8% hrs (89 %) (908) (24 hrs) (99.7%) (165) (1.1 hrs) E 36.7% 58.6% hrs 73.4% 95.4% hrs (28.5%) (171) (43 hrs) (94.8%) (120) (6.1 hrs) TALE V IMPAT O INE-GRAINE IST MOE ONTROL Inpu memor inerface - single loa ATPG Oupu memor inerface - single loa ATPG esign O Single-loa per-inerface IST moe conrol LO Single-loa per-inerface IST moe conrol overage overage Paern oun Run-ime overage overage Paern oun Run-ime 37% 52.4% hrs 27.4% 70.4% hrs E 58.6% 92.9% hrs 95.4% 99.6% hrs TALE VI IMPAT O USING MULTI-LOA ATPG esign Muli-loa RAM-sequenial ATPG wih inepenen namic IST moe conrol overage Toal #Shifs Run-ime Increase ecrease ecrease esign 52.4% hrs esign E 1.8% 820 1hr he coverage impac of each of he propose schemes o illusrae he overall coverage in his paragraph. ig. 14 shows he overall memor-inerface faul coverage improvemen for all esigns wih onl single loa ATPG enable. ine-graine IST moe conrol was no implemene on esigns an. So, he coverage numbers from inepenen namic conrol is reaine for he fine-graine scheme in he figure. Across hese 4 esigns, fine-graine IST moe conrol scheme achieves an average of 36% increase in memor inerface faul coverage when compare o he convenional scheme. urher, i ma also be noe ha for all esigns, excep E, he coverage using single-loa ATPG wih he propose schemes also excee ha of convenional muli-loa RAM-sequenial ATPG coverages (in Table I). Even for esign E, he ifference beween singleloa ATPG wih propose scheme an muli-loa ATPG wih convenional scheme is marginal ( 2%). As esign E ha less coverage han ha of convenional RAM-sequenial ATPG wih muliple loas an esign ha poor coverage wih single-loa, muli-loa ATPG was use in conjuncion wih he namic IST moe schemes for esigns an E o su he benefi. Table VI escribes he increase in coverage wih using inepenen namic IST moe conrol an muli-loa ATPG compare o convenional muli-loa ATPG (escribe in las 3 columns of Table I). We recall ha es ime an volume are eermine b he oal number of shifs for muli-loa paerns. overage of esign improve from 39.2% wih convenional scheme o 91.6% (i.e. 52.4% increase), while ha of esign E improve b 1.8% o reach 97.3%. Reasons for huge coverage increase in esign are wo-fol: (a) simpler clocking wih muli-loa ATPG for muli-banke memories, an (b) improve conrollabili of memor inpus wih he propose scheme. As explaine in Secion IV-, careful clocking sequence is crucial for esing TALE VII OVERHEA O THE PROPO SHEME Scheme Area impac Timing impac ATPG overhea LO / O NIL NIL Two ATPG runs One flip-flop Inepenen an a mux A-spee Two ATPG runs IST moe per memor/por IST MOE One flip-flop ine-graine an a mux A-spee Two ATPG runs IST moe per inerface of IST MOE each memor muli-banke memories. Use of muli-loa ATPG enables each scan loa o be resrice o a maximum of jus 2 capure ccles hereb simplifing he clocking sequence wih an increase in es ime. or he propose schemes, Table VII qualiaivel summarizes aiional overhea for hese schemes compare o convenional RAM-sequenial ATPG of [7]. Area impac summarizes he number of aiional flip-flops require. Timing impac escribes he aiional iming consrains ue o he propose scheme. A common ATPG overhea for all hese schemes is ha paern generaion is one separael for inpus an oupus, in a wo-pass manner. This is ue o he fac ha oupu IST wrapper flip-flops shoul be maske for LO, while O uses hem. A-spee IST MOE conrol is o enable namic conrol. ine-graine conrol also requires cusom IST mux conrol in he memor collar, bu his oes no a o he area. To pu hings in perspecive, he number of aiional flip-flops (overhea) neee for he wors-case finegraine conrol for esign ha has ver few (20) memories is 80 flip-flops. ine-graine conrol on esign wih man (149) memories require 1008 aiional flops, ue o presence of muli-por memories. The aiional flip-flop overhea for all he esigns were beween 0.4% o 0.6% of he oal number of flip-flops. onsiering he enire esign, he area overhea for all hese esigns were beween 0.08% o 0.2%. To summarize, following are he ke ake-awas from he experimens. 1) -inerface es coverage is ighl couple o esign sle. Even small esigns (wih memor-o-memor pahs an self-feeback) ma have poor coverage. 2) Even convenional muli-loa RAM-sequenial ATPG Paper 14.3 INTERNATIONAL TEST ONERENE 9

10 Normalize max LEGEN ig. 15. evices across spli lo wafers Transiion aul Paerns Ram-sequenial paerns wih inepenen namic IST moe conrol Silicon resuls on a proucion TI So wih commercial ATPG ools oes no enable ver high ( 95%) coverage. 3) Propose schemes are ver effecive in improving coverage, wih an average coverage increase of 36% wih using single-loa ATPG. Muli-loa ATPG wih he propose scheme furher improves he coverage. 4) are-bi coun reuces b an average of 3X o reach he convenional coverage, ue o improve conrollabili. 5) Minimal area overhea (<0.2% of oal area). E. Silicon resuls on a proucion TI So The propose inepenen namic IST moe conrol an selecive memor bpass schemes were implemene in a 40nm 600 Million ransisor proucion TI So wih 96 clock omains. ig. 15 shows normalize max scaer plo for ransiion ela faul ATPG es paerns an propose RAM-sequenial paerns, on a sample se of evices across spli lo wafers. I is also worh noing ha, on an average, RAM-sequenial paerns ha reuce he max b 6% compare o ransiion faul paerns. These ransiion ela faul paerns, argeing he logic ha a consoliae coverage of abou 88.2%, while he propose RAM-sequenial paerns argeing onl he memor inerface fauls ha a coverage of 79.8%. A ke poin o noe is ha wihou he propose inepenen namic IST moe conrol scheme, achievable memor inerface faul coverage was onl 47.5%. As observe in earlier esigns, primar reason for poor coverage wih he original scheme for his So was poor conrollabili of he memor inpu inerface ue o he large presence of memor-o-memor pahs. To summarize, he propose scheme improve he memor inerface faul coverage (b 32%) an also reuce he ssem max (b 6%). As a resul, es paerns using he propose scheme was ae o he proucion spee-binning es suie of his So o improve he binning quali. VI. ONLUSION AN UTURE WORK In his paper, we focuse on he problem of improving he memor-inerface faul coverage for snchronous memories using off-he-shelf commercial ATPG ools. We propose novel echniques o improve he conrollabili an observabili of memor-inerface b maximal usage of IST inerface wihou impacing he es quali. Each of hese schemes have increasing coverage improvemen wih corresponing area overhea. These schemes were also evaluae on four 40nm inusrial esigns. An average of 36% increase in coverage was achieve wih a small (<0.2%) aiional area overhea. are-bi coun also reuce an average of 3X ue o improve conrollabili wih he propose scheme. Propose schemes were implemene on a large 40nm TI So an were foun ver effecive in erms of boh coverage improvemen (>32%) an max reucion (6%). While he propose scheme uses ransiion faul moel o arge memor inerface fauls, fuure work lies in argeing long/criical pahs along he memor inerface eiher using small ela efec ATPG [21] or pah-ela ATPG. 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