Sub-micron high aspect ratio silicon beam etch

Transcription

1 Sub-micron high aspect ratio silicon beam etch Gary J. O Brien a,b, David J. Monk b, and Khalil Najafi a a Center for Wireless Integrated Microsystems, Dept. of Electrical Engineering and Computer Science The University of Michigan, Ann Arbor, MI 19 b Motorola Inc. Sensor Products Division, Technology and Product Development Group, Tempe, AZ ABSTRACT High aspect ratio beam/trench arrays are etched into single crystal silicon substrates (1 orientation) using a Surface Technology Systems (STS) deep reactive ion etch (RIE) tool. Process input parameters are varied using high/low values for etch cycle time, passivation cycle time, RF coil power, and SF flow rate. The silicon etch process is characterized using photo-resist masked trench arrays varied from 1.µm through µm in both width and spacing. A design of experiments (DOE) approach is used to model the following measured outputs: 1) trench depth (R 2 =.9), 2) lateral trench etch (R 2 =.2), 3) trench sidewall angle (R 2 =.1), and ) aspect ratio dependent etch (R 2 =.92), where R 2 represents the correlation between actual and model predicted values. The presented characterization models are employed to form beams as small as 3nm wide etched to a depth >1µm with near vertical sidewalls using standard photolithography equipment. In addition, the provided models are exploited to produce a dual re-entrant/tapered beam etch release process. Released silicon beams are demonstrated over 12µm long and 3µm thick with a base width of 3nm. 1. INTRODUCTION High aspect ratio silicon structures are desired in MEMS devices such as accelerometers [1] and gyroscopes [2,3]. Fluorine based chemistry is the common choice for deep silicon etching because of its high etch rate and selectivity. Fluorine etch anisotropy can be improved by using a time multiplexed plasma etch and passivation process previously developed by Bosch []. Etching of silicon microstructures with feature sizes typically ranging from two to hundreds of microns have been thoroughly studied with etch parameters extensively characterized [-]. Fluorine based chemistries have been previously shown to significantly increase both selectivity and etch rate in excess 1:1 and 1µm/minute [] respectively. Deep reactive ion etching of silicon trenches based on Cl 2 chemistry [] exhibits slow silicon etch rates and lower selectivity toward the desired SiO 2 masking film [9], typically 2-3:1. Photo-resist etch selectivity in Cl 2 chemistry is on the order of 1:1 when compared to silicon, practically excluding its use as an etch mask in deep trench etching. In contrast to chlorine, fluorine radicals etch silicon without the need for ion impact assistance resulting in an isotropic etch. Anisotropy has previously been improved for SF based chemistries by ion impact assistance coupled with sidewall passivation using polymer deposition [] and/or O 2 plasma oxidation and redeposition at the silicon sidewall surface [1,11]. The introduction of O 2 during the etch cycle has also been previously suggested to improve anisotropy by acting as a getting agent for carbon [12]. In any case, the trench width is generally increased as compared to the original mask opening due to the presence of mixed silicon etching of the sidewall typically on the order of hundreds of nanometers. The passivation cycle, ranging from to seconds, deposits a fluorocarbon polymer on the wafer surface using C F as a plasma source gas. The fluorocarbon polymer is comprised of a chain of CF 2 molecules similar in composition to Teflon TM with a film thickness of approximately 1-nm. The following etch cycle, ranging from to 12 seconds, uses SF as a plasma source gas to etch silicon. The ion assisted SF etch removes the polymer passivation on exposed

2 horizontal surfaces prior to etching the underlying silicon. Scalloping occurs when chemically reactive fluorine is adsorbed at a non-passivated silicon trench sidewall surface resulting in a localized isotropic silicon etch. Trench sidewall scalloping is typically more pronounced at the top, lessening in severity from top to bottom. The first five steps for the STS ICP-RIE sequence are shown in Figure 1. Mask Silicon Substrate Pre-Etch Polymer (CF 2 ) CF 2 Step 3: Passivate + SF n + F Photoresist Scalloping Step1: Passivate + SF n + F Step : Etch CF 2 Silicon Substrate Step 2: Etch Step : Passivate Scalloping Figure 1. The STS Time Multiplexed Passivation/Etch Cycle Process with Trench Etch Example Cross Section Smaller feature size with larger aspect ratio is typically preferred in MEMS accelerometer and gyroscope proof mass suspension tethers. This paper presents a DOE based characterization of silicon deep trench etching using typical input parameters for the STS RIE tool. Characterization results are used to form submicron MEMS suspension tethers as beams released from the substrate using typical photolithography minimum feature sizes of 1µm-µm. 2. MEASUREMENT PROCEDURES 2.1 Micrometer Width Trench Arrays A Surface Technology Systems (STS) deep RIE tool was used with 1.3µm thick positive photo-resist (AZ-113) to pattern trench arrays etched in this experiment. Fixed trench width was maintained on an individual array basis while inter trench spacing (beam width) was varied from 1µm to µm. Three fixed trench width arrays of 2µm, µm, and µm are evaluated in this paper. An array with fixed layout defined trench width of 2µm is shown in Figure 2. Top Width Depth Bottom Width Figure 2. Example of Trench Array Measurements Used to Characterize the STS Deep Silicon RIE Tool A design of experiments (DOE) approach provides a viable method to evaluate the maximum number of simultaneous input variables producing a statistically significant change in a specific output variable over a minimum number of

3 evaluated samples [13]. DOE also provides rank order of statistical significance regarding input variable versus modeled output variable responses. Interactions of 1 st and higher orders can also be evaluated simultaneously among the input variables versus output responses. Proper choice of input variable levels is required to preclude artificial correlation of input variables. Typical STS process parameters (etch cycle time, passivation cycle time, RF coil power, and SF flow rate) were varied in this 2 level (high/low) DOE screening experiment as shown in Table 1. Level Pattern Passivate (sec) Power (Watts) SF Flow (sccm) Table 1. DOE Process Input Variables The sample size used in this experiment consisted of sixteen silicon wafers with nine scanning electron microscope (SEM) based measurement sites per wafer. Layout defined trench width and spacing were also included as model geometric variable inputs over all levels shown in Table 1. The modeled output variables were trench etch depth, lateral trench etch width, trench sidewall angle, and aspect ratio dependent etch (ARDE). The output models were evaluated using JMPä statistical software. Input variables observed to produce weak influence (less than % increase in model R 2 ) on model prediction were excluded. The total etch duration was fixed at minutes for all sample measurements incorporated into the presented models. A constant O 2 flow rate of 12sccm was introduced during the etch cycle to improve anisotropy. 3. ETCH MODELS 3.1 Trench Depth Model Trench etch depth was modeled (R 2 =.9) with the following input variables listed in order of decreasing statistical significance: 1) etch cycle time, 2) passivation cycle time, 3) RF coil power, as shown in Figure 3. Etch rate can be extracted from the contour plot shown in Figure 3 by dividing the etch depth by the minute etch period. An example of calculated etch rate for the following input parameters (etch=1s, passivate=s, RF coil power=w) is modeled as 19µm over the min duration, or 2.µm/min. Power (Watts)= Power (Watts)= Power (Watts)= Etch Depth [µm] µm/min Figure 3. Trench Depth Model as a Function of Passivation and Etch Cycle for an RF coil power of,, and W

4 3.2 Lateral Trench Etch Model The lateral trench etch model was referenced to the trench top width measurement. As a result, the lateral trench etch model defines the lateral mask undercut/erosion at the photo-resist/silicon interface. Lateral trench etch was modeled (R 2 =.2) with the following input variables listed in order of decreasing significance: 1) etch cycle time, 2) passivation cycle time, and 3) RF etch power, as shown in Figure. Power (Watts)=.1.2. Power (Watts)=.2 Power (Watts)= Lateral Etch [µm] Figure. Lateral Etch Model as a Function of Passivation and Etch Cycle for an RF coil power of,, and W The lateral trench etch model was re-evaluated with the following input variables listed in order of decreasing significance: 1) etch cycle time, 2) passivation cycle time, 3) RF etch power, and ) layout defined trench width. The second lateral trench etch model (R 2 =.91) exhibited an increase of only.9% in prediction as compared to the initial model. Although the second model accurately predicts the trend of higher etch rate for larger width trenches, the small increase in prediction as compared to added complexity should be noted. An excerpt from the second model with a fixed RF coil power of Watts for layout defined trench widths of 2µm, µm, and µm wide trenches is shown in Figure. Statistical model dependence on inter-trench spacing (beam width) was not observed. Power (Watts)= =2 Power (Watts)= = Power (Watts)= = Lateral Etch [µm] Figure. Lateral Etch Model as a Function of Passivation and Etch Cycle Time for an RF coil Power of W with Fixed 2µm, µm, and µm Trench Widths 3.3. Sidewall Angle Model Trench sidewall angle [1] was measured as the straight angle between the top and bottom trench width measurements as shown in Figure. Trench sidewall angle was initially modeled with the following input variables listed in order of decreasing statistical significance: 1) etch cycle time, 2) passivation cycle time, and 3) RF coil power as shown in figure.

5 Photoresist θ 1º-θ Trench Silicon Substrate Figure. Re-entrant Trench Etch Sidewall Angle Measurement The trench sidewall angle model (R 2 =.1) is a weak, but statistically significant function of layout defined trench width. Additional modeling included layout defined trench width with an increase in prediction of only 2.% (R 2 =.39). Although the prediction increase is small, the etch trend is captured and results for the layout defined 2µm and µm wide trenches are shown in Figures and respectively. =2 Power (Watts)= =2 Power (Watts)= =2 Power (Watts)= T.. Sidewall Angle [ ] Figure. Sidewall Angle Model as a Function of Passivation and Etch Cycle Time for an with Fixed 2µm Trench Width and RF coil Power of,, and W = Power (Watts)= = Power (Watts)= = Power (Watts)= Sidewall Angle [ ] Figure. Sidewall Angle Model as a Function of Passivation and Etch Cycle Time for an with Fixed µm Trench Width and RF coil Power of,, and W

6 To produce a near vertical sidewall we note that the slope of the 9 sidewall angle model line, shown in both Figures and, is approximately 1. Our model predicts that for etch cycle times greater than seconds, the corresponding passivation cycle time producing a 9º sidewall is four seconds shorter overall. Although the SF flow rate and mask defined trench spacing were both statistically significant they had less than a % affect on model R 2 when factored either together or separately. As a result, both the SF and trench width input parameters were excluded from the model. 3. Aspect Ratio Dependent Etch Aspect ratio dependent etch [] trench depth was modeled with the following input variables listed in order of decreasing statistical significance: 1) etch cycle time, 2) passivation cycle time, 3) mask defined trench width, and ) RF coil power. The ARDE model (R 2 =.92) describes the relationship between layout defined trench width and etch depth; as the trench width is decreased the etch depth also decreases for a fixed etch and passivation cycle time. The ARDE trench depth model is shown in Figure 9 with a constant etch cycle time of 12s. =12 Power (Watts)= =12 Power (Watts)= =12 Power (Watts)= Etch Depth [µm] Figure 9. Trench Depth Model ARDE Effects with a Fixed 12s Etch Cycle for an RF Power of,, and W The ARDE can be minimized by adjusting the ratio of etch to passivation cycle time []. As the ratio of etch to passivation cycle time approaches unity the etch rate distributed across the 2µm through µm layout defined trench widths is relatively uniform for a fixed s etch cycle time as shown in Figure 1. 2 = Power (Watts)= = Power (Watts)= = Power (Watts)= E Etch Depth [µm] Figure 1. Trench Depth Model ARDE Effects with a Fixed s Etch Cycle for an RF Power of,, and W However, a 1:1 etch to passivation cycle significantly reduces the overall etch rate and the resulting sidewall angle is less than vertical. The sidewall profile observed for levels 1 through were tapered (ϑ<9 ) and all trenches formed using these etch input parameters exhibited grass [11] formation as shown in Figure

7 Figure 11. Tapered Etch with Grass Formation in Large Trenches The re-entrant (ϑ>9 ) and vertical (ϑ 9 ) sidewall trenches were not observed to form grass. The re-entrant etch trench sidewall is represented by levels 9 through 12 while the vertical trench etch profiles are represented by levels 13 through 1, as shown in Table 1. Grass was observed when the ratio of etch to passivation cycle time was less than 3:2. Also, the surface density of grass was observed to significantly increase as the ratio of etch to passivation cycle time was decreased below 1:1 respectively.. SUBMICRON BEAM ETCH.1 Submicron Beam Formation Beam arrays with a photo defined 1.µm trench spacing were etched for min using level 1 etch parameters, as shown in Table 1. The lateral trench etch model predicted a post etch.µm beam width. The actual post etch beam width was approximately.3µm, as shown in Figure 12..3µm Figure 12. Vertical Sidewall, 3nm Wide Beam Detail Scalloping of the trench sidewall near the top of the trench was observed as large as 9nm. Sidewall asperities near the trench midsection were limited to <nm. Beam sidewall angle was estimated as nearly vertical..2 Submicron Beam Re-entrant Etch Release A 1 minute re-entrant etch (level 9) immediately followed with a 2 minute tapered etch (level 1) was used to release beams from the substrate. The released silicon beam tip is approximately 12µm long, 3µm thick, with a maximum width of 3nm at the etch mask/si interface as shown in Figure 13.

8 ~3nm wide at mask interface Beam Tip Detail ~3µm 1µm Front View Side View Re-entrant etch released beam tip Figure 13. Midpoint Re-entrant Etch Released Beam This represents an aspect ratio of approximately 1. The rough bottom etch is attributed to abrupt switching between re-entrant and tapered recipes. The abrupt switching rationale is supported by the rough etch band located at the trench midpoint corresponding to the STS etch recipe transition region on large width silicon as shown in Figure 1. Future release etch efforts will include a chamber gas stabilization period between the re-entrant and tapered STS etch recipe transition. Re-entrant Etch Beam STS Etch Recipe Transition Tapered Etch Beam Figure 1. Midpoint Re-entrant Etch Released Beam Base Detail The ratio of etch to passivation cycle time was changed from 3:1 to 1:1, with all other input parameters held constant, resulting in a swing from re-entrant to tapered sidewall etching at the beam midpoint respectively. The silicon wafers (1 orientation) were insitu doped with phosphorous during Czochralski growth [1] to a uniform bulk resistivity of.-12.ω-cm. The absence of a buried dielectric layer coupled with a photo-resist etch mask suggests that the angle of ion assisted incidence is not significantly affected by trapped dielectric charge [1,1] in the presented case. We suggest the etch sidewall angle is most likely a strong function of the etch to passivation ratio as predicted by our presented model. Also, beams have been etch released from the substrate without an intermediate sidewall oxidation step [1]..3. Submicron Beams and Trenches Lateral and vertical trench etching was evaluated at the submicron level using a nano-imprint defined [1] oxide hardmask. Trenches 3nm wide with a nm period were formed using a 12nm thick oxide etch mask. Etch parameters were fixed to s passivation cycle, RF coil power of W, and SF flow rate of 13sccm, for a total duration of 2 minutes. The etch cycle time was varied over three evaluated etch samples. The first sample etch cycle time was set to.s. The.s etch sample exhibited an average trench depth was measured as 1.3µm (σ=.µm) where σ represents the standard deviation. Lateral trench etching was observed on the order of 9nm per side with scalloping sidewall asperities as large as nm were observed using the. second etch cycle time as shown in Figure 1.

9 SiO 2 Mask Mask Interface Silicon Figure 1. Submicron Lateral Trench Etching using.s Etch Cycle A 1:1 etch to passivation cycle time ratio was chosen to minimize lateral trench etching. Lateral trench etching on the order of 3nm per side with scalloping sidewall asperities as large as nm were observed using a. second etch cycle time described by level 2 etch parameters. Surface roughness due to scalloping can be reduced post etch by thermal oxidation of the sidewall followed by removal of the oxide [19]. The average trench depth was measured as 9.µm (σ=.µm) as shown in Figure 1. Figure 1. Minimized Submicron Lateral Trench Etching using.s Etch Cycle Negative lateral trench etching on the order of 9nm per side with scalloping sidewall asperities as large as nm were observed using a 3. second etch cycle time described by level 3 etch parameters. The average trench depth was 3.9µm (σ=.3µm) as shown in Figure 1..3µm.1µm Figure 1. Negative Submicron Lateral Trench Etching using 3.s Etch Cycle

10 The average etched trench depth for the.s and 3.s etch cycle samples were 1.3µm and 3.9µm respectively representing a decrease in etch rate on the order of 2.X. The post etch trench for the 3.s etch cycle was approximately 1nm wide as compared to the SiO 2 masked 3nm wide opening. This negative lateral etch represents an approximate reduction of.2µm in the SiO 2 masked trench width. Silicon etching was not observed for an etch cycle of 3.2s due to excessive CF 2 deposition at the oxide hard mask and exposed silicon surface. A combination of CF 2 pile-up and silicon surface oxidation may be responsible for the smaller than mask defined trenches observed. Oxygen has been previously proposed to passivate the silicon surface [1,11] by forming an oxide film and may also protect the sidewall at the SiO 2 /Si interface resulting in a smaller than mask defined etched trench width. Submicron layout defined beam and trench spacing, with or without an SiO 2 hardmask, requires lateral silicon etching to be minimized by setting the etch to passivation ratio with approximately 1:1 values. As a result, very little sidewall etch angle control is afforded submicron layout defined beam spacing since all etch profiles in this regime are slightly tapered. In addition, trench widths larger than nm were observed to form grass [11] using a near 1:1 etch to passivation cycle ratios. Trench widths in excess of nm require an etch to passivation ratio larger than 3:2 respectively where silicon grass formation is undesired. Scalloping has previously been eliminated using electroplated Ni masks []. A dual trench etch process has also been previously shown to significantly reduce both sidewall scalloping and inter trench depth variation in submicron trench arrays by using HBr/Cl chemistry to etch the initial nm of trench depth followed by a 1µm etch in a SF /C F based time multiplexed process [2] sequence. This diffusion rate limited deep etch process is very sensitive to submicron inter trench sidewall scallop variation across an array as the silicon etch byproduct is transported away from the trench bottom in gas phase causing an increase the etched trench depth variability. This microscopic loading effect manifests itself as an etch rate dependence on feature size and array density [21]. Scalloping asperities were observed to decrease where the etch to passivation ratio was fixed and both etch and passivation cycle times were decreased resulting in a lower overall etch rate and higher sidewall scallop frequency versus normalized depth.. CONCLUSION Submicron high aspect ratio beams etched into silicon wafers have been demonstrated using standard photolithography equipment in conjunction with STS deep RIE equipment. Models were presented for 1) trench depth (R 2 =.9), 2) trench sidewall angle (R 2 =.1), 3) trench lateral etch (R 2 =.2), and ) aspect ratio dependent etch (R 2 =.92). The most significant parameters common throughout all four presented models were etch cycle time, passivation cycle time, and RF coil power. Proper mask bias can be estimated using the models presented in this paper with to form submicron beam/trench designs on silicon wafer substrates with nearly vertical sidewalls. Re-entrant etch released beams with an aspect ratio of approximately 1 are demonstrated. Future work will address fabrication of accelerometer submicron width high aspect ratio tethers using the re-entrant etch release process. Modeled lateral etch trends were observed on submicron width trench arrays with an oxide hard mask using a 1:1 etch to passivation cycle time ratio. Sidewall scalloping was observed to decrease as the etch to passivation ratio is decreased below a 1:1 ratio respectively. REFERENCES [1] M. Offenberg, F. Laermer, B. Elsner, H. Munzel, and W. Riethmuller, Novel Process for a Monolithic Integrated Accelerometer, IEEE Transducers 9, pp. 9-92, 199. [2] M. Putty and K. Najafi, A Micromachined Vibrating Ring Gyroscope, Solid State Sensor and Actuator Workshop, Hilton Head, pp , 199. [3] F. Ayazi and K. Najafi, Design and Fabrication of a High Performance Polysilicon Vibrating Ring Gyroscope, IEEE MEMS9, pp. 21-2, 199.

11 [] F. Laermer and A. Schlip of R. Bosch GmbH, Method of Anisotropically Etching Silicon, U.S. Patent Nos.,,1 and,,2 (1991) and German Patent No. 21C1 (199). [] F. Laermer, A. Schlip, K. Funk, and M. Offenberg, Bosch Deep Silicon Etching: Improving Uniformity and Etch Rate for Advanced MEMS Applications, MEMS 99, pp , [] A.A. Ayon, R. Braff, C.C. Lin, H.H.Sawin, and M.A. Schmidt, Characterization of a Time Multiplexed Inductively Coupled Plasma Etcher, J. Electrochem. Soc., 1(1), pp , [] J.W. Weigold, Dry Etching of High Aspect Ratio Si Microstructures in High Density Plasma for use in MEMS, Ph.D. Thesis, University of Michigan, 2. [] W. C. Tian, J. W. Weigold, S. W. Pang, Comparison of Cl 2 and F-based Dry Etching for High Aspect Ratio Si Microstructures Etched with an Inductively Coupled Plasma, J. Vac. Sci. Technol., B 1, pp , 2. [9] K. T. Sung, and S. W. Pang, Etching of Si with Cl 2 Using an Electron Cyclotron Resonance Source, J. Vac. Sci. Technol., A 11, pp , [1] C. P. D Emic, K. K. Chan, and J. Blum, Deep Trench Plasma Etching of Single Crystal Silicon using SF /O 2 Gas Mixtures, J. Vac. Sci. Technol., B 1, pp , [11] H. Jansen, M. de Boer, and M. Elwenspoek, The Black Silicon Method, J. Micromechanics, vol., no. 2, pp (199). [12] J. Bhardwaj, H. Ashraf, and A. McQuarrie, Dry Silicon Etching for MEMS, Symposium on Microstructures and Microfabricated Systems, Electrochemical Society, 199. [13] D. C. Montgomery, Design and Analysis of Experiments, Wiley, N.Y., N.Y., [1] A. A. Ayon, S. Nagle, L. Frechette, A. Epstein, and M. A. Schmidt, Tailoring Etch Directionality in a Deep Reactive Ion Etching Tool, J. Vac. Sci. Technol., B 1, pp , 2. [1] S. Wolf, and R.N. Tauber, Silicon Processing for the VLSI Era, Lattice Press, Sunset Beach, CA, vol 1, 2. [1] S. A. Campbell, and H. J. Lewerenz, Semiconductor Micromachining, Wiley, N.Y., N.Y., vol. 2, 199 [1] K. A. Shaw, Z. L. Zhang, and N. C. MacDonald, SCREAM: A Single Mask, Single Crystal Silicon Process for MEMS Structures, MicroElectroMechanical Systems Workshop, pp. 1-1, [1] S. Y. Chou, P. R. Krauss, W. Zhang, L.J. Guo, and L. Zhuang, Nanoscale Silicon Field Effect Transistors Fabricated using Imprint Lithography, J. Vac. Sci. Technol. B, 1, pp , 199. [19] W.H. Juan, and S.W. Pang, Batch-Micromachined, High Aspect Ratio Si Mirror Arrays for Optical Switching Applications, International Conference on Solid-State Sensors and Actuators, pp. 93-9, 199. [2] G. O Brien, X. Cheng, and L.J. Guo, Deep Reactive Ion Etched Submicron Beam/Trench Characterization, ASME Microelectromechanical Systems, 21. [21] R.A. Gottscho, C.W. Jurgenson, and D.J. Kitkavage, Microscopic Uniformity in Plasma Etching, J. Vac. Sci. Technol. B 1, pp , 1992.