Imperial College OF SCIENCE, TECHNOLOGY AND MEDICINE University of London. Digital IC Design Course

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Scalable CMOS Layout Design Rules Scalable CMOS Layout Design Rules Imperial College OF SCIENCE, TECHNOLOGY AND MEDICINE University of London Department of Electrical & Electronic Engineering Digital

1 Scalable CMOS Layout Design Rules Scalable CMOS Layout Design Rules Imperial College OF SCIENCE, TECHNOLOGY AND MEDICINE University of London Department of Electrical & Electronic Engineering Digital IC Design Course Scalable CMOS (SCMOS) Design Rules (Based on MOSIS design rule Revision 7.3) 1 Introduction 1.1 SCMOS Design Rules In the SCMOS rules, circuit geometries are specified in the Mead and Conway's lambda based methodology [1]. The unit of measurement, lambda, can easily be scaled to different fabrication processes as semiconductor technology advances. Each design has a technology-code associated with the layout file. Each technology-code may have one or more associated options added for the purpose of specifying either (a) special features for the target process or (b) the presence of novel devices in the design. Standard SCMOS The standard CMOS technology accessed by MOSIS is a single polysilicon, double metal, bulk CMOS process with enhancement-mode n-mosfet and p-mosfet devices [3]..1 Well Type Three technology-codes are used to indicate the well type (substrate) used for fabrication (as shown in Table 1). Technology-Code SCN SCP SCE Description Scalable CMOS N-well Scalable CMOS P-well Scalable CMOS Either-well Table 1: SCMOS well types For our course, we are using Scalable CMOS n-well 0.35 um process similar to that of TSMC 0.35 process.. SCMOS Options SCMOS options are used to designate projects that use additional layers beyond the standard single-poly, double metal CMOS. Each option is called out with a designator that is appended to the basic technology-code. The current list is shown in Table. Designation Long Form Description E 3M _SUBM Electrode Triple Metal Sub Micron Adds a second polysilicon layer (poly or electrode) that can serve either as the upper electrode of a poly capacitor or (1. and.0um only) as a gate for transistors Adds second via (via) and third metal (metal3) layers Uses revised layout rules for better fit to submicron processes (see section.3) Table : SCMOS technology options The process we will be using on our course is based on TSMC 0.35um, 3 metal, poly processes as shown below: Foundry Process Lambda Options TSMC 0.35um 3 Metal Poly (3.3V/5V) 0.um SCN3ME_SUBM Table 3: SCMOS_SUBM-compatible mappings.3 SCMOS_SUBM - Sub Micron Rules The SCMOS layout rules were historically developed for 1.0 to 3.0 micron processes. To take full advantage of advanced submicron processes, the SCMOS rules were revised to create SCMOS_SUBM. By increasing the lambda size for some rules (those that didn't shrink as fast in practice as did the overall scheme of things), the submicron rules allow for use of a smaller value of lambda, and better fit to these small feature size processes. Table 4 lists the differences between SCMOS and SCMOS sub-micron. Rule Description SCMOS SCMOS sub-micron 1.1 Well width Well space (different potential) Well overlap (space) to transistor Poly space 3 5.3, 6.3 Contact space 3 5.5b Contact to Poly space to Poly Metal1 space Via on flat unrestricted 9. Metal space Metal3 width Metal3 space 4 3 Table 4: SCMOS, SCMOS tight metal, SCMOS Sub-micron differences 3 CIF and GDS layer specification A user design using the SCMOS rules can be in either Calma GDSII format [] or Caltech Intermediate Form (CIF version.0) [1]. The two are completely interchangable. Note that all submitted CIF and GDS files have already been scaled before submission, and are always in absolute metric units -- never in lambda units. GDSII is a binary format, while CIF is a plain ASCII text. For detailed syntax and semantic specifications of GDS and CIF, refer to [] and [1] respectively. In GDS format, a design layer is specified as a number between 0 and 55 (formerly 63). SCMOS now reserves layer numbers 1 through 6, inclusive, for drawn layout. Layers 0 through 0 plus layers 63 and above can be used by designers for their own purposes. A partial list of SCMOS layers is shown in Table 5, along with a list by tech-code in Table 6. CIF GDS LAYER NOTES CCC 5 CONTACT (1 of 4) [10/30/000 0:08:50] ( of 4) [10/30/000 0:08:50]

2 Scalable CMOS Layout Design Rules XP 6 XP CWN 4 N_WELL CAA 43 ACTIVE CSP 44 P_PLUS_SELECT CSN 45 N_PLUS_SELECT CPG 46 POLY CCP 47 POLY_CONTACT CCA 48 ACTIVE_CONTACT Non-fab layer used to highlight pads Use for SCN* and SCE* designs This layer should be replaced by CONTACT This layer should be replaced by CONTACT Scalable CMOS Layout Design Rules charge fluence, a figure of exposed conductor area to transistor gate area ratio is determined which guarantees Time Dependent Dielectric Breakdown (TDDB) reliability requirements for the fabricator. Failure to consider antenna rules in a design may lead to either reduced performance in transistors exposed to process induced damage, or may lead to total failure if the antenna rules are seriously violated. See the following for more details. References [1] C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980 [] Cadence Design Systems, Inc./Calma. GDSII Stream Format Manual, Feb. 1987, Release 6.0, Documentation No. B97E060 [3] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, Addison-Wesley, nd edition, 1993 CCE 55 ELECTRODE_CONTACT This layer is for For SC*E designs only. It should be replaced by the CONTACT layer. CEL 56 ELECTRODE CMF 49 METAL1 CVA 50 VIA CMS 51 METAL COG 5 GLASS CVS 61 VIA Use for SC*3M designs CMT 6 METAL3 Use for SC*3M designs CTA 60 THICK_ACTIVE Use for TSMC 0.5, 0.35µ SC* designs only Table 5: SCMOS layer map Tech-code SCN3ME Layers N-well, Active, N-select, P-select, Poly, Contact, Poly, Metal1, Via, Metal, Via, Metal3, Glass Table 6: Tech-code map 4 Minimum Density Rule Many fine-featured processes utilize CMP (Chemical-Mechanical Polishing) to achieve planarity. Most of the 0.35 micron (and smaller) processes are in this category. Effective CMP requires that the variations in feature density on a layer be restricted. See the following for more details. 5 Process-Induced Damage (otherwise known as "Antenna Rules") Rules - General Requirements The "Antenna Rules" deal with process induced gate oxide damage caused when exposed polysilicon and metal structures, connected to a thin oxide transistor, collect charge from the processing environment (e.g., reactive ion etch) and develop potentials sufficiently large to cause Fowler Nordheim current to flow through the thin oxide. Given the known process (3 of 4) [10/30/000 0:08:50] (4 of 4) [10/30/000 0:08:50]

(or logos, or anything else); large openings must be replaced by an array of standard sized openings. SCMOS - Contact 6.3 Minimum contact spacing [SUBM 3] 6.4 Minimum spacing to gate of transistor 5.

3 SCMOS - Contact SCMOS Layout Rules - Simple Contact to Poly On 0.5um process (and all finer feature size processes), it is required that ALL features on the insulator layers (CONTACT, VIA, VIA) MUST BE of the single standard size; there are no exceptions for pads (or logos, or anything else); large openings must be replaced by an array of standard sized openings. SCMOS - Contact 6.3 Minimum contact spacing [SUBM 3] 6.4 Minimum spacing to gate of transistor 5.1 Exact contact size x 5. Minimum poly overlap Minimum contact spacing [SUBM 3] 5.4 Minimum spacing to gate of transistor SCMOS Layout Rules - Alternative Contact to Poly The rules above are preferred. If, however, one cannot handle the 1.5 lambda contact overlap in 5., then that rule, 5., may be replaced by these rules, which reduce the overlap, but increase the spacing to surrounding features. The remaining rules above, 5.1, 5.3, and 5.4, still apply as originally stated. SCMOS Layout Rules - Simple Contact to Active 6.1 Exact contact size x 6. Minimum active overlap b Minimum poly overlap b Minimum spacing to other poly 4 [SUBM 5] 5.6.b Minimum spacing to active (one contact) 5.7.b Minimum spacing to active (many contacts) 3 (1 of 4) [10/30/000 0:09:43] ( of 4) [10/30/000 0:09:43]

SCMOS - Contact SCMOS - Contact SCMOS Layout Rules - Alternative Contact to Active The rules above are preferred. If, however, one cannot handle the 1.5 lambda contact overlap in 6.

4, still apply as originally stated. 6..b Minimum active overlap 1 6.5.b Minimum spacing to diffusion active 5 6.6.b Minimum spacing to field poly (one contact) 6.7.

4 SCMOS - Contact SCMOS - Contact SCMOS Layout Rules - Alternative Contact to Active The rules above are preferred. If, however, one cannot handle the 1.5 lambda contact overlap in 6., then that rule, 6., may be replaced by these rules, which reduce the overlap, but increase the spacing to surrounding features. The remaining rules above, 6.1, 6.3, and 6.4, still apply as originally stated. 6..b Minimum active overlap b Minimum spacing to diffusion active b Minimum spacing to field poly (one contact) 6.7.b Minimum spacing to field poly (many contacts) b Minimum spacing to poly contact 4 (3 of 4) [10/30/000 0:09:43] (4 of 4) [10/30/000 0:09:43]

SCMOS Layout Rules - Well SCMOS - Active SCMOS Layout Rules - Well 1.1 Minimum width 1. Minimum spacing between wells at different potential 10 [SUBM 1] 9 [SUBM 18] 1.

5 SCMOS Layout Rules - Well SCMOS - Active SCMOS Layout Rules - Well 1.1 Minimum width 1. Minimum spacing between wells at different potential 10 [SUBM 1] 9 [SUBM 18] 1.3 Minimum spacing between wells at same potential 0 or Minimum spacing between wells of different type (if both are drawn) 0 SCMOS Layout Rules - Active.1 Minimum width 3. Minimum spacing 3.3 Source/drain active to well edge 5 [SUBM 6].4 Substrate/well contact active to well edge 3.5 Minimum spacing between active of different implant 0 or 4 [10/30/000 0:10:01] [10/30/000 0:10:56]

SCMOS - Poly SCMOS Layout Rules - Poly SCMOS - Metal1 SCMOS Layout Rules - Metal1 3.1 Minimum width 7.1 Minimum width 3 3. 3..a Minimum spacing over field Minimum spacing over active [SUBM 3] [SUBM 3] [DEEP 4] 7.

3 Minimum overlap of any contact 1 3.4 Minimum active extension of poly 3 3.5 Minimum field poly to active 1 http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/design%0rules/scmos-poly.

6 SCMOS - Poly SCMOS Layout Rules - Poly SCMOS - Metal1 SCMOS Layout Rules - Metal1 3.1 Minimum width 7.1 Minimum width a Minimum spacing over field Minimum spacing over active [SUBM 3] [SUBM 3] [DEEP 4] 7..a Minimum spacing 3 7..b Minimum tight metal spacing (only allowed between minimum width wires - otherwise, use regular spacing rule) 3.3 Minimum gate extension of active 7.3 Minimum overlap of any contact Minimum active extension of poly Minimum field poly to active 1 [10/30/000 0:11:04] [10/30/000 0:11:13]

SCMOS - Via, Metal SCMOS Layout Rules - Via1 SCMOS - Via, Metal 8.1 Exact size x 8. Minimum via1 spacing 3 8.3 Minimum overlap by metal1 1 8.

.a Minimum spacing 4 9..b Minimum tight metal or SUBM spacing (only allowed between minimum width wires - otherwise, use regular spacing rule) 3 9.

7 SCMOS - Via, Metal SCMOS Layout Rules - Via1 SCMOS - Via, Metal 8.1 Exact size x 8. Minimum via1 spacing Minimum overlap by metal Minimum spacing to contact 8.5 Minimum spacing to poly or active edge (SCMOS only, not SUBM, DEEP) SCMOS Layout Rules - Metal 9.1 Minimum width 3 9..a Minimum spacing 4 9..b Minimum tight metal or SUBM spacing (only allowed between minimum width wires - otherwise, use regular spacing rule) Minimum overlap of via1 1 (1 of ) [10/30/000 0:11:] ( of ) [10/30/000 0:11:]

SCMOS - Via, Metal3 SCMOS Layout Rules - Via SCMOS - Via, Metal3 SCMOS Layout Rules - Metal3 14.1 Exact size x 14. Minimum spacing 3 14.

Minimum spacing to metal3 6 [SUBM 5] 4 [SUBM 3] 15.3 Minimum overlap of via http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/design%0rules/scmos-metal3.

8 SCMOS - Via, Metal3 SCMOS Layout Rules - Via SCMOS - Via, Metal3 SCMOS Layout Rules - Metal Exact size x 14. Minimum spacing Minimum overlap by metal Minimum spacing to via Via may be placed over contact 15.1 Minimum width 15. Minimum spacing to metal3 6 [SUBM 5] 4 [SUBM 3] 15.3 Minimum overlap of via (1 of ) [10/30/000 0:11:39] ( of ) [10/30/000 0:11:39]

MOSIS Scalable CMOS (SCMOS) Design Rules. (Revision 7.2) The MOSIS Service USC/ISI Admiralty Way. Marina del Rey, CA

MOSIS Scalable CMOS (SCMOS) Design Rules (Revision 7.2) The MOSIS Service USC/ISI 4676 Admiralty Way Marina del Rey, CA 90292-6695 1 Introduction 1.1 SCMOS Design Rules This document defines the official