Achieve Your Best Design

Transcription

1 Achieve Yur Best Design In digital standards, every generatinal change puts new risks in yur path. We see it firsthand when creating ur prducts and wrking with engineers like yu. Agilent s slutin set fr highspeed digital test is a cmbinatin f instrumentatin and brad expertise built n ur nging invlvement with industry experts. By sharing ur latest experiences, we can help anticipate challenges and accelerate yur ability t create prducts yu ll be prud f. Agilent achieve yur best design.

2 Memry Design Challenges Explained Grdn Getty Agilent Technlgies Agilent Technlgies, 2012

3 Agenda 1) The Future f Memry Technlgy Memry technlgy has hit a wall because f physics limitatins- understand what these limitatins mean fr yur designs 2) New Lgic Analyzer capable f capturing DDR4 data Is yur equipment mving as fast as yur designs? The Agilent U4154A AXIe-based lgic analyzer mdule prvides the highest accuracy measurements n high-speed digital systems perating up t 4 Gb/s with eye penings as small as 100 ps by 100 mv. Dn t let yur designs be limited by the equipment yu use t test them. 3) DDR Prbing and Analysis Tl Memry system designers have huge cncerns n prbing meeting the high bandwidth requirement fr best signal fidelity. Understand the Agilent slutins ffered t make this as easy as pssible fr yu s yu can cncentrate n slving prblems, nt wndering where the prblems are.

4 Httest Memry Applicatins Cmputer System Mbile and Wireless Applicatins Smart phne SD UHS-I slt Servers- , web, database DDR3 Ntebks, Desktps DDR2/3 Faster data rate Lwer DRAM cst Higher density Lwer pwer Cnsumer prducts LPDDR2 DRAM Graphics card GDDR5 DRAMs Industry Radmap DDR & 2133Mt/s DDR4 (up t 3.2Gb/s, 1.2V) LPDDR1/2, DDR2, DDR3 Industry Radmap DDR4 LPDDR3 Wide I/O (~12Gb/s) SD UHS-I card - max strage

5 Current Memry Technlgy Types Memry Technlgy DDR Duble Data Rate GDDR Graphics Duble Data Rate LPDDR Lw Pwer Duble Data Rate QDR Quad Data Rate Where Used? Desktp Cmputing Servers Graphics Bards Embedded Systems (future) Mbile Embedded Standard JESD79E, JESD79-2E, JESD208, JESD79-3C JESD212 JESD209A, JESD209-2 Specialty QDR Cnsrtium Nand/Nr Flash Memry JESD79-2, JESD79-3 e-mmc /SD Embedded Multimedia Card Secure Digital Managed Flash Mass Strage Devices JESD84-B45 SD Card Assciatin

6 Memry Technlgy Types Memry Technlgy Where Used? DDR Duble Data Rate Desktp Cmputing Servers DDR3 Current speed = 2133 Mb/s May increase t 2.3 Gb/s Vdd ptins = 1.5, 1.35, 1.25 First 3DStack Big push t lwer pwer DDR4 (2012) Current speed = 2.4 Gb/s Gal is t increase t 3.2 Gb/s

7 Memry Technlgy Types Memry Technlgy Where Used? GDDR Graphics Duble Data Rate Graphics Bards Embedded Systems (future) GDDR: Graphics bards fr desktp cmputers Very high speeds Current speed = 6 Gb/s May increase t 8 Gb/s in 2012 GDDR5: Pint t pint cnnectin t help with signal integrity 1 st t implement errr feedback

8 Memry Technlgy Types Memry Technlgy Where Used? LPDDR Lw Pwer Duble Data Rate Mbile Embedded LPDDR2 Current speed = 800 Mb/s Fully specified t 1067 Mb/s LPDDR3 (~Dec 2011) Gal = 1600 Mb/s Pin ut cmpatible with LPDDR2 LLI (Lw Latency Interface) Serial ASIC t ASIC lw verhead memry bus (MIPI alliance)

9 Memry Technlgy Types Memry Technlgy Where Used? QDR Quad Data Rate Specialty Nand/Nr Flash Memry QDR (Quad Data Rate): Static memry, read/write t simultaneusly Nand: 100-1,000+ writes befre failure Tggle ONFI speed 400MT/s, BGA packages Nr: ~100,000+ writes befre failure As memry size increases the number f writes befre failure decreases

10 Memry Technlgy Types Memry Technlgy Where Used? emmc/sd Embedded Multimedia Card Secure Digital Managed Flash Mass Strage Devices emmc / SD (Managed): Can be embedded r remvable emmc = embedded multimedia card SD = remvable flash Next generatin = UFS, SDA UHS-II

11 Mb/sec per Pin N N+1 N+2 N+3 N+4 N+5 N+6 Gb/sec/chip Speed Dubles With Each Generatin Generatin Year

12 Faster Gb/s per Pin Memry is Finally Bxed In by Physics Signal Integrity Prblems Crsstalk Lss Reflectin Channel Thrughput (GBytes/sec) Signal Prpagatin Physics # I/O Pins

13 Gb/s per Pin Memry is Finally Bxed In by Physics Materials and Prcess Physics MFG issues Materials Reliability Higher density Channel Thrughput (GBytes/sec) Wider # I/O Pins

14 Gb/s per Pin Slutin? G Faster & G Wider Faster & Wider Current Memry Technlgy # I/O Pins

15 Key Memry Design Challenges Slutins Challenges Increased system failures Cmpliance t new standards Signal Integrity verificatin Margin testing Prbing issues Prbe lad reduces system margin Signal accessibility is limited Cnventinal prbing limits signal insights Prbing can cause signal reflectin and ther SI issues Slutins Fllw the signal flw Accurate captures Capture high data rates with small eyes Precise triggering Bus level signal integrity insight Minimize signal integrity issues caused by BGA prbing Verify adherence t standards

16 Agilent Memry Slutins-> Fllw the Signal Flw Cnnect Acquire View & Analyze Prbing Data Acquisitin Analysis Tl Signal Integrity Oscillscpe Interpsers BGA Prbes Mid-Bus Prbing SftTuch 4 Gb/s 2.5Gb/s Ultra High Speed Lgic Analysis Mdule 2 Gb/s High Speed Lgic Analysis Mdule Decder Prtcl Cmpliance Perfrmance Analysis Trigger Lgic Analyzer

17 Agilent Memry Slutins-> Fllw the Signal Flw Cnnect Acquire View & Analyze Prbing Data Acquisitin Analysis Tl Signal Integrity Oscillscpe Interpsers BGA Prbes Mid-Bus Prbing SftTuch 4 Gb/s 2.5Gb/s Ultra High Speed Lgic Analysis Mdule 2 Gb/s High Speed Lgic Analysis Mdule Decder Prtcl Cmpliance Perfrmance Analysis Trigger Lgic Analyzer

18 Capture High Data Rate Signals with small eyes Precise Triggering Accurate capture

19 U4154A Key Characteristics State Speed 4Gb/s n 68 Channels 2.5Gb/s n 136 Channels Data valid windw 100ps x 100mV Trigger Highlights Sequence Rate 2.5GHz Sequencer Levels 8 Burst recgnizers Burst f 8 x 4 Burst f 4 x 8 Burst f 2 x 16 Sampling Reslutin EyeScan Memry Depth Channels/Width Timing Speed Timing Zm 5ps by 5mv Clrized all signals HW Accelerate (>x10 speed) up t 200M per Channel 136 channels per mdule up t 3 mdules in a set 5 GHz 68 Channels 2.5 GHz 136 Channels 12.5 GHz Full Channel x 256K

20 New Qualified Clrized Scan Display all Signals Clrized Scalable Qualified HW accelerated 10x faster hurs t minutes 5psx5MVreslutin Earlier generatin

21 DDR EyeScan custmized views Grup signals n tabs Qualified DDR scan examples: Read / Write separatin Byte Lanes Burst Scans

22 Agilent Memry Slutins-> Fllw the Signal Flw Cnnect Acquire View & Analyze Prbing Data Acquisitin Analysis Tl Signal Integrity Oscillscpe Interpsers 4 Gb/s 2.5Gb/s Ultra High Speed Lgic Analysis Mdule BGA Prbes Mid-Bus Prbing SftTuch 2 Gb/s High Speed Lgic Analysis Mdule Decder Prtcl Cmpliance Perfrmance Analysis Trigger Lgic Analyzer

23 SI Measurement with Oscillscpe Memry Design Phases that requires SI testing Prttyping (alpha and beta) SI characterizatin t cmpare results with design simulatin and specificatin Margin testing varying temperature and vltage levels Pst Prductin Margin testing fr checking cmpatibility issues SI Validatin Tasks requires Highest Measurement Accuracy Tls Read and write data parametric testing Identify crss talk and ISI failures Track infrequent events Jitter characterizatin Cmpliance as per JEDEC standard

24 Memry Oscillscpe Measurement Tl Mst Cmplete Memry Test Tls DRAM DDR/SD Cmpliance Sftware Packages DDR/SD Fixtures and Prbes InfiniiScan+ InfiniiSim Serial Data Package 9000/90000 series Oscillscpe

25 DDR Prbing and Analysis Tl When Vias Are Nt Accessible Fr embedded system with tight bard spaces and fully ppulated DIMM cnfiguratin, BGA prbes prvides signal access Example 1: Scpe ptimized BGA prbe n DIMM cnfiguratin High BW fr accurate cmpliance measurements. Example 2: Flex wing BGA prbe access fr mst signals Quick cnnectin fr either lgic analyzer r scpe De-embedding is used fr parametric measurements

26 BGA prbe and Via prbing Cmparisn Befre de-embedding Channel 1: Prbing at VIA Channel 2: Prbing at scpe pad pint n adapter bard After de-embedding Channel 1: At VIA (DQS strbe) Channel 2: At scpe adapter bard Decrease in amplitude Skew caused by delay Nt acceptable fr SI check: Signal perfrmance is affected using the BGA prbe fr SI check. Hw d I simulate an ideal prbe? Turn n Bandwidth Limit t 4G n the channel t reduce the ringing effect due t high frequency cntent.

27 InfiniiScan+ dem 2 distinctive bursts pattern fr read & write cmmands read/write data

28 Custmer Measurement Experience / Sequence Bts may be unstable OS bts up Live applicatin/stress Pwer On Test Signal Integrity Basic Cmpliance (i.e. clck, vltages) Read/write timing LA training Bus Timing / Pwer management Memry training/initializatin Bus-wide SI scan FA- Subsystem / signal Islatin System Functinality LL SW Integratin Crss-bus traffic Perfrmance tuning Rt cause parametric failure analysis Detailed parametric characterizatin Cmpliance / Vendr qualificatin