Sequential Logic. Sequential circuits. Reuse circuit elements by storing bits in "memory." Introduction to Computer Yung-Yu Chuang

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1 Sequential Lgic Intrductin t Cmputer Yung-Yu Chuang Review f Cmbatinal Circuits Cmbatinal circuits. Basic abstractin = switch. In prciple, can build TOY cmputer with a cmbatinal circuit = 4,8 puts 2 48 rws truth table! n simple pattern each circuit element used at mst nce Sequential circuits. Reuse circuit elements by strg bits "memry." ALU cmbatinal with slides by Sedgewick & Wayne (trcs.cs.prcetn.edu), Nisan & Schcken ( and Harris & Harris (DDCA) Memry state 2 Cmbatinal vs. Sequential Circuits Cmbatinal circuits. Output determed slely by puts. Can draw with n lps. Ex: majrity, adder, ALU. Sequential circuits. Output determed by puts and previus puts. Ex: memry, prgram cunter, CPU. Flip-Flp Flip-flp A small and useful sequential circuit Abstractin that remembers ne bit Basis f imprtant cmputer cmpnents fr register memry cunter There are several flavrs 3 4

2 S-R flip flp Q=S+RQ R S Q Relay-based flip-flp Ex. Simplest feedback lp. Tw relays A and B, bth cnnected t pwer, each blcked by the ther. State determed by whichever switches first. The state is latched. Stable. put put2 put put2 5 6 SR Flip Flp SR flip flp. Tw crss-cupled NOR gates. Q=R(S+Q) R S Flip-Flp Flip-flp. A way t cntrl the feedback lp. Abstractin that "remembers" ne bit. Basic buildg blck fr memry and registers. Q R S Q Caveat. Need t deal with switchg delay. 7 8

3 Truth Table and Timg Diagram Truth table. Values vary ver time. S(t), R(t), Q(t) dente value at time t. Sample timg diagram fr SR flip-flp. SR Flip Flp Truth Table S(t) R(t) Q(t) Q(t+ ) Clck. Clck Fundamental abstractin: regular n-ff pulse. n: fetch phase ff: execute phase External analg device. Synchrnizes peratins f different circuit elements. Requirement: clck cycle lnger than max switchg time. cycle time Q R S time Clck n ff 9 Hw much des it Hert? Frequency is verse f cycle time. Expressed hertz. Frequency f Hz means that there is cycle per secnd. kilhertz (khz) means cycles/sec. megahertz (MHz) means millin cycles/sec. gigahertz (GHz) means billin cycles/sec. terahertz (THz) means trillin cycles/sec. Clcked S-R flip-flp Herich Rudlf Hertz ( ) 2

4 Clcked D flip-flp Stand-Alne Register 3 4 Register file terface Register file implementatin 5 6

5 Multiplexer When s=, return x; therwise, return y. Example: (Y S) (X S) X Y S mux Z Tw-put multiplexer 4-t- multiplexer x x x 2 4MUX z x 3 s s t- multiplexer 8-t- Multiplexer x x x 2 4MUX z x x 2MUX 2MUX z 2 N -t- multiplexer N select puts, 2 N data puts, put Cpies selected data put bit t put x 3 x 2 x 3 2MUX s s s s 9 2

6 8-t- Multiplexer 2 N -t- multiplexer N select puts, 2 N data puts, put Cpies selected data put bit t put 4-Wide 2-t- Multiplexer Gal: select frm ne f tw 4-bit buses Wide 2-t- Multiplexer Gal: select frm ne f tw 4-bit buses Implemented by layerg 4 2-t- multiplexer k-wide n-t- Multiplexer Gal: select frm ne f n k-bit buses Implemented by layerg k n-t- multiplexer 23 24

7 Register file implementatin Memry Overview Cmputers and TOY have several memry cmpnents. Prgram cunter. Registers. Ma memry. Implementatin. Use ne flip-flp fr each bit f memry. Access. Memry cmpnents have different access mechanisms. TOY has 6 bit wrds, 8 bit memry addresses, and 4 bit register names. Organizatin. Need mechanism t manipulate grups f related bits Register Register bit. Extend a flip-flp t allw easy access t values. Register Register bit. Extend a flip-flp t allw easy access t values. D W DW DW 27 28

8 Memry : Interface Memry bit. Extend a flip-flp t allw easy access t values. Memry : Switch Level Implementatin Memry bit. Extend a flip-flp t allw easy access t values. [ TOY PC, IR ] [ TOY ma memry ] [ TOY registers ] [ TOY PC, IR ] [ TOY ma memry ] [ TOY registers ] 29 3 Prcessr Register Prcessr register. Stres k bits. Register cntents always available n put bus. If enable write is asserted, k put bits get cpied t register. Ex. TOY prgram cunter (PC) hlds 8-bit address. Ex 2. TOY structin register (IR) hlds 6-bit current structin. Prcessr Register Prcessr register. Stres k bits. Register cntents always available n put bus. If enable write is asserted, k put bits get cpied t register. Ex. TOY prgram cunter (PC) hlds 8-bit address. Ex 2. TOY structin register (IR) hlds 6-bit current structin. 3 32

9 Prcessr Register Prcessr register. Stres k bits. Register cntents always available n put bus. If enable write is asserted, k put bits get cpied t register. Ex. TOY prgram cunter (PC) hlds 8-bit address. Ex 2. TOY structin register (IR) hlds 6-bit current structin. Memry Bank Memry bank. Bank f n registers; each stres k bits. Read and write frmatin t ne f n registers. Address puts specify which ne. lg 2 n address bits needed Addressed bits always appear n put. If write enabled, k put bits are cpied t addressed register. Ex. TOY ma memry. 256-by-6 memry bank. (fur 6-bit wrds) 6-bit put bus Ex 2. TOY registers. 6-by-6 memry bank. Tw put buses. 2-bit address 6-bit put bus Memry: Interface Memry: Cmpnent Level Implementatin (fur 6-bit wrds) 35 36

10 Memry: Switch Level Implementatin (fur 6-bit wrds) Summary Sequential circuits add "state" t digital hardware. Flip-flp. [represents bit] TOY wrd. [6 flip-flps] TOY registers. [6 wrds] TOY ma memry. [256 wrds] Mdern technlgies fr registers and ma memry are different. Few registers, easily accessible, high cst per bit. Huge ma memries, less accessible, lw cst per bit. Drastic evlutin f technlgy ver time. Next. Build a cmplete TOY cmputer The Clck Flip-flp clck signal tck tck cycle cycle cycle cycle In ur jargn, a clck cycle = -phase (lw), fllwed by a tck-phase (high) tck tck DFF (t) = (t-) A fundamental state-keepg device Fr nw, let us nt wrry ab the DFF implementatin Memry devices are made frm numerus flip-flps, all regulated by the same master clck signal Ntatinal cnventin: In real hardware, the clck is implemented by an scillatr In ur hardware simulatr, clck cycles can be simulated either sequential chip = (ntatin) sequential chip Manually, by the user, r Autmatically, by a test script. clck signal

11 -bit register (we call it ) register (cnt.) Objective: build a strage unit that can: (a) Change its state t a given put (b) Mata its state ver time (until changed) lad Interface Implementatin if lad(t-) then (t)=(t-) else (t)=(t-) lad lad MUX DFF DFF DFF if lad(t-) then (t)=(t-) else (t)=(t-) (t) = (t-) Basic buildg blck (t) = (t-)? (t) = (t-)? Wn t wrk Lad bit Read lgic Write lgic lad Multi-bit register if lad(t-) then (t)=(t-) else (t)=(t-) -bit register w lad... w-bit register if lad(t-) then (t)=(t-) else (t)=(t-) Register s width: a trivial parameter Read lgic Write lgic w Aside: Hardware Simulatin Relevant tpics frm the HW simulatr tutrial: Clcked chips: When a clcked chip is laded t the simulatr, the clck icn is enabled, allwg clck cntrl Built- chips: feature a standard HDL terface yet a Java implementatin Prvide behaviral simulatin services May feature GUI effects (at the simulatr level nly).

12 Randm Access Memry (RAM) lad RAM terface register lad register (wrd) address ( t n-) register 2. register n- RAM n Direct Access Lgic (wrd) 6 bits address lg 2 n bits RAMn 6 bits Read lgic Write lgic. RAM anatmy RAM 64 Needed: a strage device that can: (a) set its state t sme base value Cunter (b) crement the state every clck cycle RAM8 (c) mata its state (stp crementg) ver clck cycles (d) reset its state c lad reset Register... RAM 8 register. register register 8. RAM w bits PC (cunter) w bits If reset(t-) then (t)= else if lad(t-) then (t)=(t-) else if c(t-) then (t)=(t-)+ else (t)=(t-) Recursive ascent Typical functin: prgram cunter Implementatin: register chip + sme cmbatinal lgic.

13 Recap: Sequential VS cmbatinal lgic Cmbatinal chip cmb. lgic (ptinal) cmb. lgic Sequential chip time delay DFF gate(s) (ptinal) cmb. lgic clck signal tck Time matters tck cycle cycle cycle cycle Durg a -tck cycle, the ternal states f all the clcked chips are allwed t change, but their puts are latched tck tck = sme functin f () (t) = sme functin f ((t-), (t-)) At the begng f the next cycle, the puts f all the clcked chips the architecture cmmit t the new values. a Reg Implicatins: Challenge: prpagatin delays sel + Slutin: clck synchrnizatin b Reg2 Cycle length and prcessg speed. Perspective All the memry units described this lecture are standard Typical memry hierarchy Access time Cst SRAM ( static ), typically used fr the cache DRAM ( dynamic ), typically used fr ma memry Disk (Elabrate cachg / pagg algrithms) A Flip-flp can be built frm Nand gates But... real memry units are highly ptimized, usg a great variety f strage technlgies.