JABATAN KEJURUTERAAN ELEKTRIK

Transcription

1 JABATAN KEJURUTERAAN ELEKTRIK COURSE CODE EC302 COURSE NAME ELECTRONIC COMPUTER AIDED DESIGN COURSE WORK LAB WORK 5 TOPIC DIGITAL LOGIC SIMULATION DATE Learning Outcomes: Perform simulation of various analogue, digital and mixed-signal electronic circuits successfully using a particular simulation package. Laboratory Equipment: Computer / MicroSim Eval 8 CLOCK GENERATOR CIRCUIT. [CLO 2] The first circuit we will look at is an op-amp circuit that drives the clock of a JK flip-flop. Wire the circuit shown in Figure5.1. The parts contained in this circuit are given in table. The circuit is drawn as though we were going to wire the circuit in the lab. No special circuits are required between the analog circuitry and the digital logic states. Procedure: 1. Draw the schematic circuit shown as below: (Rubric : Circuit drawing 10 Marks)

2 ANALYSIS/RESULT: The J and K inputs of the flip-flop are held high so that the flip-flop toggles at each positive clock edge. There must be one important point that must not be overlooked. All sequential logic that has a preset or clear function must be preset or cleared at the start of the run. If you do not preset or clear the sequential logic, Pspice does not know what output state to start the logic in. Since the initial state is unknown, all future states are unknown and all the results of the simulation are meaningless. The digital source clears the flip-flop at the start of the run by having a logic value of zero for time equals 1us to 20us. For the remainder of the simulation, the source has the value of logic one. The attributes of this source are as in Figure 5.2: Figure 5.2 The pulsed voltage waveform, Vpulse, produces a 1 khz square wave that produces voltages between 1 and 1 volt. How to get the Vpulse part and how to set its attributes are shown in Figure 5.3a and Figure 5.3b below. Figure 5.3a Figure 5.3b The ideal op-amp circuit has a gain of 9 and produces a +-9 volt square wave of 1 khz at node Vo1. This wave goes into Zener clipping circuit that limits the voltage to +5.6 and 0.7 volts at node Vclamp. This voltage is TTL compatible and connected to the Schmitt Trigger input. The output of the Schmitt trigger should be 0 to 5 volts square waves at 500Hz. They should also be 180 degrees out of phase.

3 Since the frequency of the generator is 1 khz, we will run a transient simulation for 15ms to allow 15 cycles. Fill in the Transient setup dialog box as shown in Figure 5.4 Set automatically run probe as in Figure 5.5 Figure 5.4 Figure 5.5 Run simulation as shown below in Figure 5.6 Figure 5.6

4 Generating Timing Diagram For Analog & Digital Signals With Probe To display the traces, click Trace and then Add from the menu bar. Some of the traces are displayed differently in this dialog box. At analog nodes the traces are displayed as V(Vo1) or V(R6:1). The currents through analog components are shown as I(D1) or I(R5). The waveforms at digital nodes are shown as Vo3 or Vo4. This is how Probe allows you to distinguish between digital and analog nodes. To plot the analog and digital signal, highlight the nodes which are to be graphed by Probe. The highlighted node names will be displayed in the Trace Expression box. Probe will automatically separate analog and digital traces by plotting them on separate plots. Display the traces Vo1, Vclamp, Vo2, Vo3 and Vo4 by highlighting the node names one by one or by directly keying in the node names in the Trace Expression box as in Figure 5.7 Figure 5.7 Probe will graph digital signals Vo2, Vo3 and Vo4 together on one plot and analog signals V(Vo1) and V(Vclamp) together on a separate plot as in Figure 5.8 Figure 5.8 (Rubric : Analysis/Result 20 Marks)

5 Graphic Part Name escription ibrary R esistor val.slb VPULSE ndependent pulsed voltage source ource.slb BUBBLE UBBLE ort.slb AGND Ground ort.slb ua741 Operational amplifier val.slb dge triggered JK flip-flop val.slb 7414 nverting Schmitt Trigger val.slb Digital signal igital source ource.slb D1N750 volt zener val.slb HI onstant logic 1 ort.slb LO onstant logic 0 ort.slb Table 1 Component List Conclusion : Write the conclusion based on your findings. (Rubric: Conclusion - 5 Marks) PREPARED BY CHECKED BY APPROVED BY COURSE LECTURER COURSE COORDINATOR HEAD OF PROGRAM MOHD KAMIL ZAHARI NORHANANI ABD RAHMAN MOHAMMAD FADZIL BASIR AHMAD DATE : 20/1/2012 DATE : 20/1/2012 DATE : 20/1/2012