Week 4: Sequential Circuits

Transcription

1 Week 4: equential ircuits

2 omething to consider omputer specs use terms like 8 GB of AM and 2.2GHz processors. ú What do these terms mean? AM = andom Access Memory; 8GB = 8 billion ints 2.2 GHz = 2.2 billion clock pulses per second. ú But what does this mean in circuitry? How do you use circuits to store values? What is the purpose of a clock signal?

3 omething else to consider How does Tickle Me Elmo work?

4 Two kinds of circuits o far, we ve dealt with combinational circuits: ú ircuits where the output values are entirely dependent and predictable from the input values. Another class of circuits: sequential circuits ú ircuits that also depend on both the inputs and the previous state of the circuit.

5 equential circuits This creates circuits whose internal state can change over time, where the same input values can result in different outputs. Why would we need circuits like this? ú Memory values ú eacting to changing inputs

6 reating sequential circuits Essentially, sequential circuits are a result of having feedback in the circuit. ú How is this accomplished? ú What is the result of having the output of a component or circuit be connected to its input? Inputs Inputs ircuit Feedback ombinational ircuit torage Units Outputs Outputs

7 Feedback ircuit Examples ome gates don t have useful results when outputs are fed back on inputs. A A A T T A T T In these truth tables, T and T+ represent the values of at a time T, and a point in time immediately after (T+)

8 Feedback Examples Others have more interesting characteristics, which lend themselves to storage devices. A A A T T A T T

9 Feedback behaviour NAN behaviour NO behaviour A T T A T T What makes NAN and NO feedback circuits different? Unlike the AN and O gate circuits (which get stuck), the output T+ can be changed, based on A. However, gates like these that feed back on themselves could enter an unsteady state.

10 NAN waveform behaviour A A T T A

11 Latches If multiple gates of these types are combined, you can get more steady behaviour. A A B B These circuits are called latches.

12 latch Let s see what happens when the input values are changed ú Assume that and are set to and 0 to start. ú The input sets the output to, which sets the output to 0. ú etting to keeps the output value at, which maintains both output values

13 latch 0 0 (continuing from previous) ú and start with values of, when is set to 0. ú This sets output to, which sets the output to 0. ú etting back to keeps the output value at 0, which maintains both output values. Note: inputs of maintain the previous output state! 0 0 0

14 latch T T T+ T+ 0 0 X X 0 X X 0 0 X X and are called set and reset respectively. Note how the circuit remembers its signal when going from 0 or 0 to. Going from 00 to produces unstable behaviour! ú epending on which input changes first.

15 latch T T T+ T X X 0 0 X X 0 X X 0 0 In this case, and are set and reset. In this case, the circuit remembers previous output when going from 0 or 0 to 00. As with latch, unstable behaviour is possible, but this time when inputs go from to 00.

16 latch timing diagram Important to note that the output signals don t change instantaneously.

17 More on instability Unstable behaviour occurs when a latch goes from 00 to, or a latch goes from to 00. ú The signals don t change simultaneously, so the outcome depends on which signal changes first. Because of the unstable behaviour, 00 is considered a forbidden state in NAN-based latches, and is considered a forbidden state in NO-based latches.

18 eading from latches Now we have circuit units that can store high or low values. How can we read from them? ú For instance, when do we know when the output is ready to be sampled? ú If the output is high, how can we tell the difference between a single high value and two high values in a row? Need some sort of timing signal, to let the circuit know when the output may be sampled. à clock signals.

19 Break

20 lock signals locks are a regular pulse signal, where the high value indicates that the output of the latch may be sampled. Usually drawn as: voltage 5V But looks more like: time

21 ignal restrictions What s the limit to how fast the latch circuit can be sampled? etermined by: ú latency time of transistors etup and hold time ú setup time for clock signal Jitter Gibbs phenomenon Frequency = how many pulses occur per second, measured in Hertz (or Hz).

22 locked latch By adding another layer of NAN gates to the latch, we end up with a clocked latch circuit. The clock is often connected to a pulse signal that alternates regularly between 0 and.

23 locked latch behaviour ame behaviour as latch, but with timing: ú tart off with =0 and =, like earlier example. ú If clock is high, the first NAN gates invert those values, which get inverted again in the output. ú etting both inputs to 0 maintains the output values

24 locked latch behaviour ontinued from previous: ú Now set the clock low. ú Even if the inputs change, the low clock input prevents the change from reaching the second stage of NAN gates. ú esult: the clock needs to be high in order for the inputs to have any effect

25 locked latch This is the typical symbol for a clocked latch. This only allows the and signals to affect the circuit when the clock input () is high. Note: the small NOT circle after the output is simply the notation to use to denote the inverted output value. It s not an extra NOT gate.

26 locked latch behaviour T T+ esult no change reset 0 0 set 0???? 0 0 no change Assuming the clock is, we still have a problem when and are both, since the state of is indeterminate. 0 0 reset 0 set???? ú Alternative design: prevent and from both going high.

27 latch T T By making the inputs to and dependent on a single signal, you avoid the indeterminate state problem. The value of now sets output low or high.

28 latch This design is good, but still has problems. ú i.e. timing issues.

29 Latch timing issues onsider the circuit on the right: When the clock signal is high, the output looks like the waveform below: ú Output keeps toggling back and forth.

30 Latch timing issues Preferable behaviour: ú Have output change only once when the clock pulse changes. ú olution: create disconnect between circuit output and circuit input, to prevent unwanted feedback and changes to output.

31 master-slave flip-flop A flip-flop is a latched circuit whose output is triggered with the rising edge or falling edge of a clock pulse. Example: The master-slave flip-flop 0 0

32 master-slave flip-flop

33 Edge-triggered flip-flop flip-flops still have issues of unstable behaviour. olution: flip-flop ú onnect latch to the input of a latch. ú Negative-edge triggered flip-flop (like the )

34 Flip-flop behaviour Observe the behaviour: ú If the clock signal is high, the input to the first flip-flop is sent out to the second. ú The second flip-flop doesn t do anything until the clock signal goes down again. ú When it clock goes from high to low, the first flip-flop stops transmitting a signal, and the second one starts Z Z 0

35 Flip-flop behaviour ontinued from previous: ú If the input to changes, the change isn t transmitted to the second flip-flop until the clock goes high again. ú Once the clock goes high, the first flip-flop starts transmitting at the same time as the second flipflop stops

36 onfused yet? Maybe a demonstration will help

37 Edge-triggered flip-flop Alternative: positive-edge triggered flip-flops These are the most commonly-used flip-flop circuits (and our choice for the course).

38 Notation Latches with ontrol with 0 ontrol Master-slave flip-flops Triggered Triggered Triggered Triggered Edge-triggered flip-flops Triggered Triggered Note: While all these are possible, we mainly use edgetriggered flip-flops in our designs.

39 Other Flip-Flops The T flip-flop: ú Like the flip-flop, except that it toggles its value whenever the input to T is high.

40 Other Flip-Flops The JK Flip-Flop: ú Takes advantage of all combinations of two inputs (J & K) to produce four different behaviours: if J and K are 0, maintain output. if J is 0 and K is, set output to 0. if J is and K is 0, set output to. if J and K are, toggle output value.

41 equential circuit design imilar to creating combinational circuits, with extra considerations: ú The flip-flops now provide extra inputs tothe circuit Inputs ú Extra circuitry needs to be designed for the flip-flop inputs. ú which is next week s lecture J ombinational ircuit torage Units Outputs