Analysis of Clocked Sequential Circuits
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1 Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
2 Presentation Outline Analysis of Clocked Sequential circuits State and Output Equations State Table State Diagram Mealy versus Moore Sequential Circuits State and Timing Diagrams Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 2
3 Analysis of Clocked Sequential Circuits Analysis is describing what a given circuit will do The output of a clocked sequential circuit is determined by 1. Inputs 2. State of the Flip-Flops Analysis Procedure: 1. Obtain the equations at the inputs of the Flip-Flops 2. Obtain the output equations 3. Fill the state table for all possible input and state values 4. Draw the state diagram Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 3
4 Analysis Example Is this a clocked sequential circuit? YES! What type of Memory? D Flip-Flops How many state variables? Two state variables: and What are the Inputs? One Input: What are the Outputs? One Output: Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 4
5 Flip-Flop Input Equations What are the equations on the inputs of the flip-flops? and are the current state, and are the next state, The values of and will be and at the next clock edge Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 5
6 Next State and Output Equations The next state equations define the next state At the inputs of the Flip-Flops Next state equations? There is only one output What is the output equation? Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 6
7 State Table State table shows the Next State and Output in a tabular form Next State Equations: and Output Equation: Another form of the state table Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 7
8 State Diagram State diagram is a graphical representation of a state table The circles are the states Two state variable Four states (ALL values of and ) Arcs are the state transitions Labeled with: Input / Output Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 8
9 Combinational versus Sequential Analysis Analysis of Combinational Circuits Obtain the Boolean Equations Fill the Truth Table Output is a function of input only Analysis of Sequential Circuits Obtain the Next State Equations Obtain the Output Equations Fill the State Table Draw the State Diagram Next state is a function of input and current state Output is a function of input and current state Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 9
10 Example with Output = Current State Analyze the sequential circuit shown below Two inputs: and One state variable No separate output Output = current state Obtain the next state equation, state table, and state diagram Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 10
11 Example with Output = Current State Flip-Flop Input Equation: Next State Equation: 1 Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 11
12 Sequential Circuit with T Flip-Flops Circuit has two T Flip-Flops One Input One output Two state variables: and Obtain the T-FF input equations Obtain the next state equations Fill the state table Draw the state diagram Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 12
13 Recall: Flip-Flop Characteristic Equation For D Flip-Flop: 1 = For T Flip-Flop: +1 = () These equations define the Next State For JK Flip-Flop: +1 = + () D Flip-Flop T Flip-Flop JK Flip-Flop D Q(t+1) T Q(t+1) J K Q(t+1) 0 0 Reset 1 1 Set 0 Q(t) No change 1 Q'(t) Complement 0 0 Q(t) No change Reset Set 1 1 Q'(t) Complement Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 13
14 Sequential Circuit with T Flip-Flops T Flip-Flop Input Equations: = = Next State Equations: (+1 1 Output Equation: Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 14
15 From Next State Equations to State Table T Flip-Flop Input Equations: = = Next State Equations: +1 1 Output Equation: Notice that the output is a function of the present state only. It does NOT depend on the input Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 15
16 From State Table to State Diagram Four States: =00, 01, 10, 11 (drawn as circles) Output Equation: (does not depend on input ) Output is shown inside the state circle (/) Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 16
17 Sequential Circuit with a JK Flip-Flops One Input and two state variables: and (outputs of Flip-Flops) No separate output Output = Current state Obtain the JK input equations Obtain the next state equations Fill the state table Draw the state diagram Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 17
18 JK Input and Next State Equations JK Flip-Flop Input Equations: = and = = and = Next State Equations: +1 1 Substituting: 1 1 Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 18
19 From JK Input Equations to State Table JK Input Equations: =, =, = and = Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 19
20 From State Table to State Diagram Four states: =00,01,10,!" 11 (drawn as circles) Arcs show the input value on the state transition Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 20
21 Mealy versus Moore Sequential Circuits There are two ways to design a clocked sequential circuit: 1. Mealy Machine: Outputs depend on present state and inputs 2. Moore Machine: Outputs depend on present state only Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 21
22 Mealy Machine The outputs are a function of the present state and Inputs The outputs are NOT synchronized with the clock The outputs may change if inputs change during the clock cycle The outputs may have momentary false values (called glitches) The correct outputs are present just before the edge of the clock Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 22
23 Mealy State Diagram An example of a Mealy state diagram is shown on the right Each arc is labeled with: Input / Output The output is shown on the arcs of the state diagram The output depends on the current state and input Notice that State 11 cannot be reached from the other states Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 23
24 Tracing a Mealy State Diagram Cycle Inputx Present StateAB? ? Output z When the circuit is powered, the initial state (AB) is unknown Even though the initial state is unknown, the input x = 0 forces a transition to state AB = 00, regardless of the present state Sometimes, a reset input is used to initialize the state to 00 Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 24
25 False Output in the Timing Diagram Cycle Inputx Present StateA B? ? Output z A Negative edge-triggered B Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 25
26 Moore Machine The outputs are a function of the Flip-Flop outputs only The outputs depend on the current state only The outputs are synchronized with the clock Glitches cannot appear in the outputs (even if inputs change) A given design might mix between Mealy and Moore Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 26
27 Moore State Diagram An example of a Moore state diagram is shown on the right Arcs are labeled with input only The output is shown inside the state: (State / Output) The output depends on the current state only Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 27
28 Tracing a Moore State Diagram When the circuit is powered, the initial state (AB) and output are unknown 0 0 Input x = 0 resets the state AB to 00. Can also be done with a reset signal Cycle Inputx Present StateA B? ? Output z? Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 28
29 Timing Diagram of a Moore Machine Cycle Inputx Present StateA B? ? Output z? The output is synchronized with the clock. No false output (or glitch) can appear. Negative edge-triggered A B Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 29
30 Summary To analyze a clocked sequential circuit: 1. Obtain the equations at the Inputs of the flip-flops 2. Obtain the Next State equations For a D Flip-Flop, the Next State = D input equation For T and JK, use the characteristic equation of the Flip-Flop 3. Obtain the Output equations 4. Fill the State Table Put all the combinations of current state and input Fill the next state and output columns 5. Draw the State Diagram Two types of clocked sequential circuits: Mealy versus Moore Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Muhamed Mudawar slide 30
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