INVITED PAPER Mixed Signal SoC Era

Transcription

1 IEICE TRANS. ELECTRON., VOL.E87 C, NO.6 JUNE INVITED PAPER Mixed Signal SoC Era Special Section on Analog Circuit and Device Technologies Akira MATSUZAWA a), Member SUMMARY Application area of mixed signal technology is currently expanded to digital communication, networking, and digital storage systems from conventional digital audio and video systems. Digital consumer electronics are emerged and their markets are extremely increased. Rapid progress of integrated circuit technology has enabled a system level integration on a SoC. Thus mixed signal SoC becomes a majority in LSI industry. Almost all the analog functions should be realized by CMOS technology on SoC, yet some difficulties such as a low transconductance, a large mismatch voltage, and a large 1/ f noise should be solved. CMOS device has been considered as a poor device for the analog use, however in reality, it has attained a remarkable progress for analog applications. CMOS device has a variety of circuit techniques to address its own issues and also has an analog performance that increases rapidly with technology scaling. The mixed signal SoC needs a new development strategy and design methodology that covers from system level to device level for addressing tough needs for a shorter development time, a lower cost, and a higher design quality. The optimizations over analog and digital and over system to device must be established for the development success. Difficulty of low voltage operation of further scaled CMOS in analog circuits will be the most serious issue. This results in the saturation of performance and increase of cost. The system level optimization over analog and digital, digital calibration and compensation, and the use of sigma-delta modulation method will give us the solution. key words: CMOS, LSI, system LSI, mixed signal technology, analog circuit, LSI design, analog device 1. Introduction Recent rapid progress of integrated circuit technology has been going to integrate a whole system on a chip. A concept of System on a chip (SoC) is just realized as real products. Almost all of the systems have an analog part as well as a digital part, therefore mixed signal SoCs are essentially needed for current electronic systems. Bi-CMOS technology has been conventionally used for small mixed signal systems, however strong demands for large system integration require CMOS technology. This paper reviews and discusses the current roles of mixed signal technology, features of CMOS analog technology, progress of video-rate ADCs as an example of CMOS analog circuit technology, development strategy and design system to attain a short development time and a high design quality, and issues and possible solutions for the current and future mixed signal SoC technology. Manuscript received February 8, Manuscript revised March 6, The author is with Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan. a) matsu@ssc.pe.titech.ac.jp 1.1 Feature of Current Electronics Current electronics scene can be characterized from the following three keywords. 1) Digital consumer electronics 2) Digital communication and networking 3) System LSI (SoC) Digital consumer electronics has rapidly emerged. Almost all of products based on analog technology replaced by the digital ones. One example is a camera. Optical cameras replaced by digital cameras. The number of shipment of digital cameras for a month has exceeded that of optical cameras on Japanese market in The number of shipment of DVD recorders also exceeded that of conventional VTRs on Japanese market in the same year. Furthermore, plasma or liquid crystal displays with digital TVs are going to form a big market. A conventional TV with CRT display is going to fade away from the market rapidly. Common features of these digital consumer electronics products are using digital technology and System LSI (SoC) technology. Digital communication and networking technologies are widely used currently. ADSL and FTTH have become popular. 10 million houses use these digital networking to connect to the internet in Japan. Almost all of PCs are connected with Ethernet. Furthermore, wireless LAN also becomes popular. Home networking whose connects home appliances and control them will appear on the market in the near future. 1.2 Current Role of Analog and Mixed Signal Technology Mixed signal technology is essential for digital communication, digital networking, and digital storage. Figure 1 shows a block diagram of the Gigabit Ethernet, which is a major digital networking standard. This system uses mixed signal technology. Received signal is commonly deteriorated by signal echoes, cross-talks, and imperfect transfer characteristics. Thus, compensation and equalization are needed to obtain non-erroneous data from the erroneous damaged signal. Digital signal processing technique is a strong solution to solve these issues. It can equalize the damaged signal by an adaptive digital filter and can correct the data by some error correction techniques such as Viterbi decoder. Also, some analog circuits are still needed. A high-speed analog to digital converter is needed to obtain the digital value of

2 868 IEICE TRANS. ELECTRON., VOL.E87 C, NO.6 JUNE 2004 Fig. 1 Gigabit Ethernet system. Fig. 2 Digital read channel system for DVD. received signal as an input signal of the digital signal processor. Furthermore, a clock recovery circuit to extracts the clock signal from the data signal by using PLL technology is essentially needed. Therefore this Gigabit Ethernet system is based on the mixed signal technology. Another example is a DVD system as shown in Fig. 2. Pickup signal from digital storage media are often damaged. The signal eyes are unclear and the signal itself may contain many errors. These errors degrade the reconstructed picture quality and may cause a heavy damage to playback action in worst case. Digital equalizer and digital error correction circuits are the strong solution to reduce the error rate. An ultra-high speed analog filter and an analog to digital converter are needed to generate digital values from the pickup signals efficiently. Thus, the mixed signal processing method is also widely used in digital storage system. Owing to this method, we can obtain almost non-erroneous data, as shown in Fig. 2. Current digital consumer electronics products can be composed with only one or at most two SoCs and the input or output signals might be analog signals or digital networking signals or digital storage signals. Therefore, the mixed Fig. 3 Mixed signal SoC for DVD recorder. signal SoC becomes major LSI products. Figure 3 shows a mixed signal SoC for DVD recorders [1]. This SoC integrates a digital read channel system op-

3 MATSUZAWA: MIXED SIGNAL SOC ERA 869 erated at 500 MHz. Other parts are for digital signal processing and digital control for DVD record and playback. Using a 0.18 µm embedded DRAM process, it contains 24 M transistors including a 16Mb DRAM. The application area of the mixed signal technology has been expanded. Digital communication and networking systems, digital storage systems such as DVD and HDD, display systems such as LCD driver, input devices such as digital camera, and power supply systems such as switching power supply have already grown a big market. Furthermore, current digital CMOS circuit and memory need internal voltage regulators. Almost all of the electronics products need mixed signal technology. A very important change in the role of mixed signal technology is to expand its input signals from conventional natural analog signals such as natural images and sounds to digital signals such as in digital networking, communications, and storages. It can be concluded that not only conventional natural signals but also artificial digital signals are objectives for current mixed signal technology and this technology is promised to grow further along with the progress of digital technology. 2. CMOS as an Analog Device Bipolar technology has been a major technology for analog circuits and CMOS technology only has a limited use in analog area. However the wide use of CMOS technology for analog circuits becomes vital for the mixed signal SoC. Bi-CMOS seems as one candidate for realizing mixed signal SoC, however the wafer cost is expensive and the available design rule is one or two generation behind that of CMOS. Thus a strong demand for CMOS technology to integrate analog circuits with CMOS digital circuits has emerged recently. Table 1 compares CMOS and bipolar technologies in terms of their analog performance. Major issues of CMOS are a low transconductance, a large mismatch voltage, and alarge1/ f noise. On the other hands, the advantages of CMOS are the good switching capability, zero input current, easy implementation of switched capacitor circuits, easy use of analog and digital compensation techniques. In a short word, CMOS has some issues for analog application, however it has also several circuit techniques to address these own issues. High frequency characteristics of NMOS transistor has increased rapidly owing to rapid decrease of channel length as shown in Fig. 4. A maximum cutoff frequency is inversely proportional to the channel length and that of 0.13 µm NMOS reaches about 100 GHz. One order lower frequency must be available carrier frequency for conventional radio frequency application. 5 GHz Wireless LAN LSI has been already developed in CMOS technology [2]. 10 GHz or higher frequency wireless system will be possible with 0.13 µm CMOS technology. Operating frequency of digital circuits has also increased. About 1/60 of cutoff frequency of NMOS transistor gives a trend line for operating frequency in digital circuits. This performance increase has enabled the use of CMOS technology for radio frequency applications and GHz analog circuits, however there is a pit hole. The cutoff frequency, f T is given by (1) f T g m. (1) 2πC in And g m of bipolar and MOS can be described as g m = I c (Bipolar), (2a) U T g m = I ds ( ) (MOS), (2b) Veff 2 where I c and I ds are corrector current and drain current respectively, U T is a thermal voltage, V eff is an effective gate voltage. U T is 26 mv at room temperature and V eff /2 is conventionally set to be 100 mv and the minimum value is nu T, where n is a ratio between an ideal sub-threshold slope factor and an actual sub-threshold slope factor, conventionally takes 1.3 or 1.5. As a result, g m of MOS transistor is three or four times lower than that of bipolar transistor under the same current condition. Hence, higher f T of MOS transistor is due to small input capacitance of MOS transistor. Therefore an effect of parasitic capacitance of MOS transistor on high frequency characteristics is much larger than that of Table 1 Comparison between analog characteristics of CMOS and bipolar devices. Fig. 4 Cutoff and operation frequency trend in CMOS technology.

4 870 IEICE TRANS. ELECTRON., VOL.E87 C, NO.6 JUNE 2004 (a) Without parasitic (b) With parasitic (c) Optimized with parasitic Fig. 5 Group delay characteristics for CMOS CT filter. bipolar transistor. Layout in CMOS technology should be done carefully in order to reduce the parasitic capacitance. Figure 5 shows the parasitic capacitance effect on the group delay performance of the high frequency CMOS CT filter. Circuit simulation result before layout shows acceptably small group delay until 300 MHz. However the simulation with parasitic capacitance extraction after layout tells us the group delay becomes unacceptably large. Thus we optimized some circuit parameters including these parasitic capacitances. Other serious issues of analog CMOS technology are degradations of mismatch voltage and 1/ f noise at small gate area. V T mismatch of MOS transistor and 1/ f noise voltage can be approximately expressed by [3], [4]; V T T ox LW, (3a) Vnf 2 T ox 2 LW f. (3b) f Therefore the larger gate area is needed to reduce these values and this causes increase of cost and power consumption and decrease of frequency performance. Similar tendencies can be seen in capacitance and resistance. Capacitance mismatch and resistance mismatch are expressed by C C 1 1, (4a) S C R R 1, (4b) S where S is device area. Thus larger device area is needed to decrease mismatch of passive components. Therefore there is principal tradeoff betweenaccuracyandfrequencyperformance, power consumption, and cost. Cutoff frequency of intrinsic MOS transistor, f T in moderate gate bias and that in career velocity saturation condition are approximated as, f T 1 L 2 (in mod erate gatebias), (5a) f T 1 (in careervelocity condition), (5b) L therefore CMOS technology scaling increases cutoff frequency. V T mismatch trend can be expressed as following equation when constant current and constant effective gate voltage condition. V T T ox 1, (6) LW S c where S c is a scaling factor and conventionally set to 0.7 for one technology advance. The cutoff frequency of intrinsic MOS transistor will increase rapidly, yet degradation of mismatch is gradually. This suggests us that we should use technology scaling to increase frequency performance, to reduce power consumption, and to lower the occupied area. An issue of accuracy degradation should be addresses by circuit technology. 3. Video Rate CMOS ADC as an Example of Analog CMOS Circuit Technology Analog to digital converter (ADC) is the most important circuit block in mixed signal technology. Every digital signal processing needs ADC and the system performance depends on the performance of ADC strongly. It is not too much to say that the progress of CMOS ADC enabled mixed signal SoC. I would like to review the progress of video rate CMOS ADC, because this is a good example of analog CMOS circuit technology. In 1980, video rate 10 bit ADC was not realized by monolithic IC technology but realized by circuit board technology. Price was about $8,000 and power consumption was about 20 W. ADC was serious bottleneck to realize future consumer digital video equipments and multimedia products. In 1982, we succeeded to develop the world first monolithic video rate 10b ADC [5]. However it used parallel A/D conversion scheme and a large number of 1024 comparators are integrated in bipolar technology and power consumption was 2 W. This was a big progress; however the power consumption was not sufficiently small for the target. CMOS technology had been expected to reduce the cost and power consumption and to be integrated with digital circuits. Video-rate CMOS ADC in early days had not attractive performance. The resolution was 7 bit or 8 bit at most and power dissipation was larger than that of bipolar. One reason was the design rule was too large and other reason

5 MATSUZAWA: MIXED SIGNAL SOC ERA 871 Fig. 6 Fig. 7 CMOS chopper comparator circuit. Two step parallel ADC. is the tough trade off between accuracy and speed or power dissipation. The comparator used an input differential pair with latch like bipolar circuit. A remarkable progress has been made by using CMOS chopper comparator circuit shown in Fig. 6 [6]. In this circuit, CMOS inverter acts as an amplifier at the bias point. Switch 1 is closed in one clock period and switch 2 selects the input signal. In this condition, the capacitance voltage tracks the input voltage. In another clock period, switch 1 is opened and the switch 2 selects reference voltage. The input signal is sampled at the moment of the switch 2 is opened. The voltage difference between the sampled input voltage and the reference voltage is amplified and moreover the offset voltage of the inverter is cancelled through this action. This circuit can realize sample and hold action, comparison and amplification, and offset cancel in spite of simple circuit configuration. Since this circuit is almost free from the tradeoff between accuracy and high speed operation with low power consumption, we can reduce the device size and occupied area without serious degradation of accuracy. Furthermore operating voltage can be scaled along with digital circuits. Thus we can increase the operating speed and comparison accuracy, also reduce power dissipation and occupied area. Two step parallel A/D conversion scheme shown in Fig. 7 had been known as strong solution to reduce the number of elements, occupied area, and power dissipation. Bipolar technology however has serious difficulty to use this A/D conversion scheme, because of difficulty for realizing sample/hold function and switching for reference resistances. This scheme needs two conversion steps and input signal must be sampled and held during two conversion steps. The sample and hold circuit in bipolar technology is tough to be realized because of large base current and difficulty to make simple switch circuit. CMOS technology can realize no input current and simple switch circuit. Therefore the combination of this two step parallel conversion scheme and chopper inverter comparator circuit realized 8 bit video rate CMOS ADC of which occupied area and power consumption are superior to that of bipolar in 1989 [7]. The residual issue was increase of accuracy from 8 bit to 10 bit. We invented capacitive interpolation, pipelining amplification, and capacitive averaging. The low power 10 bit video rate CMOS ADC has been succeeded to develop in 1993 [8]. The power consumption is only 30 mw. During 13 years, drastic power reduction of about 1/600 has been attained. The cost has been also reduced. Current ADC core occupies very small area of about 0.2 mm 2. This low power consumption and small occupied area have made it possible ADC to be embedded in digital CMOS LSI. Ultra high speed ADCs of which resolution are 6 bit or 7 bit, yet the conversion rate is several hundred MHz are needed for digital storage systems such as HDD or DVD and digital networking systems such as Ethernet. In the past, an ultra-high speed ADC was realized by bipolar technology. Ultra-high speed CMOS ADCs have been developed, however power consumption and occupied area were not sufficient to be integrated in SoC. The chopper inverter technology is difficult to be applied to this ADC because of extremely high speed operation. Interpolation technique and averaging technique have been used to reduce the voltage mismatch instead of high speed chopping technique. We developed 6 bit, 800 MHz operation CMOS ADC in 2000 [9]. It could demonstrate ultra-high seed operation reaching GHz, even though using CMOS technology. However power consumption was 400 mw and this value can t be accepted for the use of SoC. This is because acceptable total power of consumer SoC is about 1 W and less than 100 mw should be acceptable for ADC. In 2002, we could develop an ultra-low power 7 bit 400 MHz CMOS ADC in 0.18 µm technology [10]. It consumes only 50 mw and occupied area is 0.3 mm 2. This significant power reduction is mainly due to the use of dynamic comparator circuit and gatewidth weighted interpolation circuit shown in Fig. 8 [10], [11]. This comparator circuit can compare the interpolated input voltages without static current consumption. Transistors m 1 to m 4 form interpolation circuit. Conductance of parallel connected transistors m 1 and m 2 in MOS linear region, G 1 and Conductance of parallel connected transistors m 3 and m 4 in MOS linear region, G 2 are given by [ W1 G 1 = K P L (V n 1 V th ) + W ] 2 L (V n V th ), (7a) [ W1 G 2 = K P L (CV n 1 V th ) + W ] 2 L (CV n V th ), (7b)

6 872 IEICE TRANS. ELECTRON., VOL.E87 C, NO.6 JUNE 2004 Fig. 8 circuit. Dynamic comparator with gate-width weighted interpolation Fig. 9 Interpolation method and circuits. where, K P is a proportional coefficient determined by the product of carrier mobility and gate capacitance, V th is a threshold voltage of NMOS transistor. This comparator compares these conductances at the moment when the clock signal is going to high and latching the output voltages. If the conductance G 1 is smaller than G 2, output terminal, V out becomes high and CV out becomes low. If the conductance G 1 is higher than G 2, output terminal, V out becomes low and CV out becomes high. Through this compare and latch actions, no static current flows. If we set the gate width ratio W 1 to W 2 is (m n): n, we can obtain the following relation at the comparison point. (m n) V n 1 + nv n m = (m n) CV n 1 + ncv n m This equation shows the comparator circuit can realize the interpolation action which can compare the equally divided input voltages between one and another input voltage, as shown in Fig. 9. This interpolation technique is very effective to improve the linearity of the ADC. One reason is an amplified input signal is fed to the comparator so that an input referred offset voltage of the comparator can be suppressedto1/gain where Gain is the voltage gain of preamplifier. Other reason is the effect of the offset voltage of pre-amplifier on differential non-linearity is reduced to 1/m where m is interpolation number. This interpolation technique can relax the requirement for the mismatch voltage of input transistors in the comparator and allows using small size transistors which has smaller capacitance. Therefore we can reduce power consumption drastically without scarify of degradation of accuracy. It can be seen that we can reduce power consumption drastically and increase conversion frequency by using scaled CMOS technology. In contrast, bipolar technology has difficulties to form this dynamic circuit which needs no static power consumption and to use the characteristics of voltage controlled conductance which is easily realized in CMOS circuit. Conventional interpolation technique that can be applied to bipolar circuit use series connected re- (8) sistors [12] consumes static power. In contrast, this gatewidth weighted interpolation method needs no static power. Using these circuit techniques that can be realized by only CMOS technology and using scaled CMOS, we could realize very high speed of 400 MHz 7 bit CMOS ADC with small power consumption of 50 mw and could integrates it on the scaled CMOS technology. Thus ultra-high speed mixed signal SoCs become promising. 4. Development Strategy and Design System for Mixed Signal SoC Figure 10 shows a recent developed mixed signal SoC for DVD systems [13]. Almost all the needed digital and analog circuits for DVD systems can be successfully integrated on this SoC. It has been fabricated in 0.13 µm technology with 6 cupper interconnect layers and contains 24M transistors. This SoC must be a goal of an idea of SoC in terms of full system integration. Since this SoC integrates not only large digital circuits but also large and high performance analog circuits on a technology edge 0.13 µm technology. Due to the sever requirement for time to market and development cost reduction in consumer electronics products, one-pass design is vital for the SoC development, even though it integrates large and high performance analog circuits, which need two or three redesign conventionally. A special SoC development strategy from system design to silicon fabrication must be established. 4.1 Development Strategy On the system design, fast of all, system should be optimized to reduce the analog area and to relax the performance requirement for analog without sacrifice of system performance. Thus a deep insight to system over analog and digital and fast and accurate mixed signal system simulator are vital. The strategy that analog circuits should be reduced and digital technology should be used as much as possible

7 MATSUZAWA: MIXED SIGNAL SOC ERA 873 Fig. 11 Collaboration between different development groups for SoC and making roadmap. Fig. 10 Mixed signal SoC for DVD application. seems right way. This is because shrinking of digital area and reduction of power consumption are still progressing along with the CMOS technology scaling. Furthermore programmability and accurate predictability of digital technology give us the faster parameter and algorism changes, high flexibility, and high robustness. Only essential analog circuits will survive in future SoC. Another important point in system design is to prepare the digital calibration circuits for analog circuits. Analog circuits must have some unknown parameters due to device fluctuation, imperfect parameter extraction, and some system issues. Therefore we need the adjustment circuits which work at actual use. In conventional analog IC, it is difficult to use the digital compensation technique which needs microprocessor, memory, and logic circuits. This results in increase of cost. In contrast, SoC has at least one microprocessor and area increase due to embedding the digital calibration must be negligible for current SoC. This gives a large opportunity to analog circuit design in mixed signal SoC. The analog circuits in SoC may overcome many issues using this good situation. On the circuit design, circuits should be designed to satisfy the performance target given by the system simulation. Some analog circuits could be designed automatically if the circuit size is not large and its circuit topology is almost fixed, however in reality almost all analog circuits must be designed by circuit engineers. The most important point on the analog circuit design in SoC development must be that the circuits should be verified to satisfy the required performance on the PVT (Process, Voltage, and Temperature) corners. Thus ultra fast and accurate circuit simulator is imperative to verify the circuits in acceptably short time. Moreover, post layout simulation is vital. This is because CMOS circuit is very sensitive to parasitic components in particular at high speed operation, as I pointed in Sect. 2. Process and device development should be mandated to the mixed signal SoC development strategy. High quality passive components often determine the system performance. For example, small mismatch and low voltage coefficient capacitor is vital for realizing high performance switched capacitor circuits and pipeline ADCs. Early and accurate analog parameter extraction or estimation is Fig. 12 Design flow for mixed signal SoC. strongly recommended to realize accurate circuit simulation and to shorten the design time. If we can t obtain the mismatch data, we can t design analog circuits with sufficient optimization. Lastly, some important analog parameters, such V T mismatch have to be controlled in wafer fabrication line, as well as conventional digital parameters. This SoC development process needs tough optimization for many different development groups, however unfortunately technology has been subdivided and it is difficult to have a global view. Thus much efficient corroboration and communication over different development groups are really needed [14]. In my experience, one effective way is to make technology roadmap by combining the different development groups, as shown in Fig. 11. First of all, application or system group shows future system demends. Next each development group shows some solutions, future issues, and tradeoffs. Lastly related groups should discuss how to solve the issues. Some effective solutions will be given by other development groups. For example, leakage current issue of device group can be addressed by adaptive body biasing and operating voltage control technique, proposed by circuit group. Current technical issues for SoC development is too much tough to be solved by single group, so that how to make corroboration and communication over different development groups is vital to SoC development success. 4.2 Design System A new design system should be established for an efficient mixed signal SoC design. Figure 12 shows one example. Main design flow covers system design, circuit design, and

8 874 IEICE TRANS. ELECTRON., VOL.E87 C, NO.6 JUNE 2004 Fig. 13 Digital read-write channel system for DVD. layout design. This line is a top down design flow. Furthermore a bottom up design flow is also needed. Post layout simulation is vital for current high speed CMOS design. Accurate extract of parasitic component and fast circuit simulation are needed. Also extraction of behavioral model from circuit simulator is very effective to increase the design productivity and quality on the system level design. On the circuit design, use of optimizer is effective to shorten the design time and increase design quality. This is because, an analog circuit has many tradeoffs over the performance and robustness, and furthermore optimization of circuit taking into account of layout is often to be needed. Accurate device parameter is an another key for success. Not only SPICE parameters for CMOS transistor, but also parameters for passive devices should be extracted with sufficient accuracy. Accurate noise and mismatch parameters are often neglected in digital circuit design, yet vital for analog circuit design. Package and cable modes are needed for high speed interface design or simulation of cross talk between I/O signal, power supply noise, and substrate noise. On the mixed system design, many system parameters should be optimized over analog and digital circuits. Figure 13 shows digital read-write channel system for DVD. Not only encoder/ decoder method and processing method, but also the number of taps and boost level of analog filter, resolution of ADC, the number of taps of digital filter, and the number of path metrics of Viterbi decoder must be optimized. Figure 14 shows the bit error rate (BER) as a function of signal to noise ratio (SNR) with different resolutions of ADC. This BER result shows 6 bit resolution is the best and higher resolution more than 6 bit will lose the effectiveness. The system is optimized by using an ideal signal waveform at early design stage and finally checked its robustness by using real discs signal data that contains many types of signals from the real problematic disc. Through these system design process, we can confirm the system optimization and its robustness. Use of mixed signal behavioral language such Verilog AMS gives us the opportunity of hole system description even if the system contains analog parts. One effective use is to simulate the system performance. Figure 15 shows one example. Target LSI is a CMOS analog front end for ADSL application. In this case, Matlab is used as a soft DSP to generate test signals and to decode the processed Fig. 14 Bit error rate vs. SNR with different ADC resolutions. Fig. 15 Virtual LSI test for ADSL system. signal for checking the CAM consternation and frequency spectrum. By using this virtual test system, we can check the DMT carrier-hole test which checks the channel separation. Through this virtual testing, we can determine the target specification for each circuit block. Circuit designers must design the needed circuits and check the consistency between the target specification and simulation result for designed analog circuit. This top down analog design methodology is very effective to reduce the development time and increase the design quality. 5. Issues and Possible Solutions for Current and Future Mixed Signal SoC Mixed signal SoC has emerged recently and become main stream in LSI industry. However some issues should be addressed in order to keep continuous growth in future. The most serious and fundamental issue must be a difficulty of operating voltage lowering. Figure 16 shows the technology load map for the technology node and operating voltage for digital circuit and analog circuit [15]. The operating voltage lowering of analog circuit would be saturated about 1.5 V, and further low voltage operation looks quite diffi-

9 MATSUZAWA: MIXED SIGNAL SOC ERA 875 Fig. 16 Technology roadmap for technology node and operating voltage. Fig. 17 SNR vs. capacitance for different signal swings. cult. One reason is headroom issue. Analog circuit often needs stacked circuit such cascode configuration, and furthermore regulated cascade that increases drain resistance by the use of voltage gain of Operational amplifier, if an extremely high voltage gain is needed for one stage operational amplifier, such application of pipeline ADCs. This results in increase of operating voltage. Other reason is to keep the high signal to noise ratio. Noise voltage appeared on capacitor in switched capacitor circuit is given by Vn 2 = nkt (9) C where n is the number of capacitances that affects the input referred noise. The signal power can be expressed as VFS 2 /8 therefore signal noise to ratio (SNR) can be described as; SNR (db) = 10 log CV2 FS 8nkT. (10) Figure 17 shows the SNR vs. capacitance for different full scale signal swings. This figure shows that we can obtain 12 bit dynamic rage with 1 pf capacitor when using 5V pp signal swing; however we should increase the capacitance up to 20 pf for keeping the same SNR if we use 1V pp signal swing. This result tell us that the use of low voltage operation does not always give us good performances like digital circuit but give us some serious problems, such as decrease of frequency performance, increase of occupied area and cost, and increase of power consumption. This difficulty of low voltage operation in analog circuit will limit the increase of frequency performance. Device physics tell us the tradeoff between cutoff frequency, f T and operation voltage, V op known as Johnson s limit [16]; f T V op = const. (11) The constant is fundamentally determined by the band gap voltage of the material and about volts/second for silicon. Therefore it is difficult to increase the cutoff frequency without decreasing operating voltage. Further increase of cutoff frequency looks quite difficult. Moreover the difficulty of low voltage operation results in difficulty of further area reduction using more highly scaled CMOS transistor. In addition, passive devices such resistor, capacitor, and inductor occupy large area, in particular small mismatch devices need larger area. Due to these issues, it must be not easy to reduce the analog area. Figure 18 shows estimated chip area and chip cost if a mixed signal SoC fabricated with 0.35 µm technology is shrunk with several different scaled technology, yet analog and I/O area is kept constant over several technology nodes and wafer cost increases with a ratio of 1.3 for one technology advance. The chip size will be reduced with technology advance; however chip cost will increase with technology advance after 0.13 µm technology. One of strong motivation for full integration of system is a cost reduction. Therefore reduction of analog area along with technology scaling is very vital for future mixed signal SoC. For the reduction of analog area, first of all, system optimization is needed over analog and digital circuits. Analog technology should be used to the only essentially needed parts, such as low noise amplification, high frequency mixing, signal oscillation, and A/D andd/a conversion. An analog filter can be replaced by digital filter, or at least the required performance of analog filter can be relaxed by increase of performance of digital filter or increase of sampling frequency. The digital calibration or compensation technique must be a very effective solution. One remarkable example has been reported from Iowa University [17]. 14 bit 100 MHz DAC has been successfully developed. Using 0.13 µm CMOS technology with 1.5 V operating voltage and digital calibration circuits, this DAC has realized extremely small occupied area of 0.1 mm 2 which is 1/50 compared with previous work and very small power dissipation of 17 mw which is 1/20 compared with previous work. Conventionally the high resolution DAC needs larger transistor to reduce the random current mismatch and this causes large occupied area and power dissipation. In contrast to this approach, this DAC uses scaled CMOS technology to reduce occupied area and power dissipation and to increase operating speed. The issue is decrease of linearity. INL error without calibration is ± 9LSB and can be suppressed to ± 0.4LSB by the digital calibration technique. A conventional issue when introducing the digital calibration is the increase of area overhead. However this can be improved with technology scal-

10 876 IEICE TRANS. ELECTRON., VOL.E87 C, NO.6 JUNE 2004 (a) Chip area (b) Chip cost Fig. 18 Estimated chip area and chip cost in different technology nodes. Fig. 19 Mixed signal egg. we can t treat the egg without shell. Shell, which is thrown away at cooking, sustains the egg. This is because yoke and white are too much delicate gels to sustain its form and to keep them fresh, like analog circuits. Digital calibration and compensation technique looks like a shell. They give the accuracy and keep the needed analog performance, even if device parameters or circuit environment are fluctuated or changed. I pointed out a current role of analog technology is to help the digital technologies, therefore now digital technology should help analog technology. In other words how to use the digital must be essentially important for further progress of analog circuit technology. 6. Conclusion ing micron technology has enabled negligibly small area overhead of 0.04 mm 2. This success demonstrates the usefulness of the digital calibration and compensation technique to reduce the occupied area and power dissipation in future analog circuits. In particular, almost no overhead will be realized on a SoC. This is because all SoCs have some CPU cores. Other important technique to address the low voltage design and decrease of dynamic range must be use of sigmadelta modulation technique. Many sigma-delta ADCs which use scaled CMOS technology such 0.13 µm and low operation voltage such 1.2 V have been developed for wireless communication systems [18], [19]. They have attained high dynamic rage of 70 db or 76 db in spite of low operating voltage of 1.8 V or 1.2 V. Power consumption is very small of 3 mw or 4.4 mw. The noise generated in analog circuits can be reduced effectively by taking higher over sampling ratio. High operating frequency with low power consumption of digital filter was not easy to be realized; however this can be improved drastically by the technology scaling. Only the technologies will survive if they accompany with technology scaling as I shown in the development of the video rate CMOS ADCs. One metaphor for future analog circuit technology would be given by an egg shown in Fig. 19. Analog must be a yoke and white and digital in analog function must be a shell. Needed parts of egg are yoke and white, however Almost all the electric system contains analog parts as well as digital parts. Conventional natural analog signals such image or sound signal and other sensor signals are needed. Uses of radio frequency communication and networking system have been increasing and the radio frequency signal is an analog signal. And furthermore in digital network systems and digital storage systems the received digital signals should be processed as an analog signal. ADC converts the damaged digital signal to digital value so that digital signal processing reconstructs waveform of which bit error rate is sufficiently small. Analog technology, as it were, helps digital technology. Many systems can be integrated on a SoC owing to rapid progress of integrated circuit technology. Almost all the electric systems will be integrated on SoCs. Thus the mixed signal SoC must be an ultimate form of integrated circuit. Integration of analog circuits on CMOS SoC must not be easy, however further progress will be continued. The system level optimization for mixed signal systems over analog and digital and over highly abstracted treatment and highly physical treatment must be most important works. Unfortunately technology has been subdivided and total optimization becomes quite difficult. A variety of knowledges should be integrated to solve this tough, yet important issue. Communication and corroboration over every persons who have different specialty must give us great success.

11 MATSUZAWA: MIXED SIGNAL SOC ERA 877 References [1] S. Gotoh, T. Takahashi, K. Irie, K. Ohshima, N. Mimura, K. Aida, T. Maeda, T. Yamamoto, K. Sushihara, Y. Okamoto, Y. Tai, M. Usui, T. Nakajima, T. Ochi, K. Komichi, and A. Matsuzawa, A mixedsignal 0.18 µm CMOS SOC for DVD systems with 432M samples/s PRML read channel and 16 Mb embedded DRAM, IEEE J. Solid- State Circuits, vol.36, no.11, pp , Nov [2] M. Zargari, D.K. Su, C.P. Yue, S. Rabii, D. Weber, B.J. Kaczynski, S.S. Mehta, K. Singh, S. Mendis, and B.A. Wooley, A 5-GHz CMOS transceiver for IEEE a wireless LAN systems, IEEE J. Solid-State Circuits, vol.37, no.12, pp , Dec [3] K.R. Lakshmikumar, R.A. Hadaway, and M.A. Copeland, Characterization and modeling of mismatch in MOS transistors for precision analog design, IEEE J. Solid-State Circuits, vol.21, no.6, pp , Dec [4] M.J. Knitel, P.H. Woerlee, A.J. Scholtem, and A.T. Zeges, Impact of process scaling on 1/ f noise in advanced CMOS technologies, IEEE International Electron Devices Meeting. Tech. Digest, pp , [5] T. Takemoto, M. Inoue, H. Sadamatsu, A. Matsuzawa, and K. Tsuji, A fully parallel 10-bit A/D converter with video speed, IEEE J. Solid-State Circuits, vol.17, no.6, pp , [6] A.G.F. Dingwall, Monolithic expandable 6b 15 MHz CMOS/SOS A/D converter, 1979 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp , [7] N. Fukushima, T. Yamada, N. Kumazawa, Y. Hasegawa, and M. Soneda, A CMOS 40 MHz 8b 105 mw two-step ADC, 1989 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.14 15, [8] K. Kusumoto, A. Matsuzawa, and K. Murata, A 10-b 20-MHz 30 mw pipelined interpolating CMOS ADC, IEEE J. Solid-State Circuits, vol.28, no.12, pp , [9] K. Sushihara, H. Kimura, Y. Okamoto, K. Nishimura, and A. Matsuzawa, A 6b 800 Msamples/s CMOS A/D converter, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp , [10] K. Sushihara and A. Matsuzawa, A 7b 450MSPS 50 mw CMOS ADC in 0.3 mm 2, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp , [11] T.B. Cho and P.R. Gray, A 10b, 20 Msample/s, 35 mw pipeline A/D converter, IEEE J. Solid-State Circuits, vol.30, no.3, pp , [12] H. Kimura, A. Matsuzawa, T. Nakamura, and S. Sawada, A 10-b 300-MHz interpolated-parallel A/D converter, IEEE J. Solid-State Circuits, vol.28, no.4, pp , [13] K. Okamoto, T. Morie, A. Yamamoto, K. Nagano, K. Sushihara, H. Nakahira, R. Horibe, K. Aida, T. Takahashi, M. Ochiai, A. Soneda, T. Kakiage, T. Iwasaki, H. Taniuchi, T. Shibata, T. Ochi, M. Takiguchi, T. Yamamoto, T. Seike, and A. Matsuzawa, A fullyintegrated 0.13 µm CMOS mixed-signal SoC for DVD player applications, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.38 39, [14] A. Matsuzawa, How to make efficient communication, collaboration, and optimization from system to chip, IEEE, 40th Design Automation Conference, pp , June [15] International technology roadmap for semiconductors, Technology Working Groups, Austin, TX, [16] E.O. Johnson, RCA Review, p.163, June [17] Y. Cong and R.L. Geiger, A 1.5 V 14b 100 MS/s self-calibrated DAC, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp , [18] K. Philips, A 4.4 mw 76 db complex sigma-delta ADC for Bluetooth receivers, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.64 65, [19] A. Dezzani and E. Andre, 1.2 V dual-mode WCDMA/GPRS sigma-delta modulator, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.58 59, Akira Matsuzawa received B.S., M.S., and Ph.D. degrees in electronics engineering from Tohoku University, Sendai, Japan, in 1976, 1978, and 1997 respectively. In 1978, he joined Matsushita Electric Industrial Co., Ltd. Since then, he has been working on research and development of analog and Mixed Signal LSI technologies; ultra-high speed ADCs, intelligent CMOS sensors, RF CMOS circuits, digital readchannel technologies for DVD systems, ultrahigh speed interface technologies for metal and optical fibers, a boundary scan technology, and CAD technology. He was also responsible for the development of a low power LSI technology, ASIC libraries, analog CMOS devices, SOI devices. From 1997 to 2003, he was a general manager in advanced LSI technology development center. On April 2003, he retired from Matsushita and became a professor on physical electronics in Tokyo Institute of Technology. He served as a guest editor in chief for special issue on analog LSI technology of IEICE transactions on electronics in 1992, 1997, and 2003, a vice-program chairman for International Conference on Solid State Devices and Materials (SSDM) in 1999 and 2000, a Co-Chairman for Low Power Electronics Workshop in 1995, a program committee for analog technology in ISSCC and a guest editor for special issues of IEEE Transactions on Electron Devices. He has published 23 technical journal papers and 42 international conference papers. He is co-author of 8 books. He holds 34 registered Japan patents and 65 US and EPC patents. He received a IR100 award in 1983, a R&D100 award and a remarkable invention award in 1994, an IEEE Fellow award in 2002, and an ISSCC evening panel award in He is an IEEE Fellow since 2002.