Mixed signal SoC: A new technology driver in LSI industry

Transcription

1 Mixed signal SoC: A new technology driver in LSI industry Akira Matsuzawa Matsushita Electric Industrial Co., Ltd (Tokyo Institute of Technology, after this April) ISCAS A. Matsuzawa 1

2 Contents Introduction Current electronics and mixed signal technology CMOS as an analog device Development strategy and design system for mixed signal SoC Issues of mixed signal SoC and solutions Summary ISCAS A. Matsuzawa 2

3 Current electronics and mixed signal technology ISCAS A. Matsuzawa 3

4 Image of current electronics Digital consumer electronics and networking drive current electronics. DAB IEEE 1394, USB, Blue tooth, Wireless LAN CS/BS Digital TV ITS ADSL, FTTH Network HII Station Digital TV Ethenet Home network W-CDMA Home Server DVC DVD ISCAS A. Matsuzawa 4

5 Mixed signal technology :Digital networkings Mixed signal technology enables high speed digital networking. Data conversion Data and clock recovery Equalization Noise cancellation Encryption Error correction Analog Line I/F DAC DAC DAC DAC Pulse Shaping 6b, 125MHz ADC, DAC Digital TX1 TX2 TX3 TX4 Side-stream Scramber & Trellis,Viterbi Symbol Encoder 250Mbaud (PAM-5) ADC ADC Clock Recovery FFE Slicer DFE Side-stream Descramber & Trellis, Viterbi decoder Analog circuit Digital circuit Echo Canceller 3-NEXTCanceller ISCAS A. Matsuzawa 5

6 Mixed signal tech. ;Digital read channel Digital storage also needs high speed mixed signal technologies. Variable Variable Gain Gain Amp. Amp. Analog Analog Filter Filter A to to D Converter Converter Digital Digital FIR FIR Filter Filter Viterbi Viterbi Error Error Correction Correction Data Out Data In (Erroneous) Pickup signal Voltage Voltage Controlled Controlled Oscillator Oscillator Clock Clock Recovery Recovery Analog circuit Data Out Processed (No error) Signal Digital circuit ISCAS A. Matsuzawa 6

7 Mixed signal SoC for DVD RAM system This enables high readability for weak signal from DVD RAM pickup. World fastest and highly integrated mixed signal CMOS SoC Analog for servo Digital Read channel 16Mb DRAM 0.18um- edram 24M Tr 16Mb DRAM 500MHz Mixed Signal Goto, et al., ISSCC 2001 ISCAS A. Matsuzawa 7

8 Recent developed mixed signal CMOS LSIs 5G RF LAN 12b 50MHz ADC 2ch 12b 50MHz DAC 2ch Digital network 1394b (1GHz) AFE (Analog Front End) AFE for Digital Camera 12b 20MHz ADC+AGC AFE for ADLS 12b 20MHz ADC+DAC 2GHz RF CMOS ISCAS A. Matsuzawa 8

9 Application area in mixed signal CMOS tech. Almost all the products need mixed signal CMOS LSI tech. Network Communication Recording Output Input Power supply Wireless Wired Cellular phone: PDC, W-CDMA RR-Net: Bluetooth, IEEE Broad cast: STB, DTV, DAB Optical:FTTH, OC-xx Metal: ADSL, VDSL, Power line modem Serial: IEEE1394, USB, Ethernet Parallel: DVI, LVDS DVD, VDC, HDD LCD, PDP, EL, Audio drive Camera, Others Switching supply, Every LSIs (On-chip) ISCAS A. Matsuzawa 9

10 Digital technology in real world Digital signal suffers heavy damage in real world. But, digital can address this issue by own advantages, but needs the help of analog tech. Pure digital Advantages of Digital Tech. High robustness Programmability Time shift (memory) Error correction High Scalability Media (Cable, Disc, Air, etc) Mixed Mixed signal signal technology (Analog+Digital) Noise Distortion Interference Limited bandwidth Real world Damaged digital Reconstruction Not only digital, but also analog; ADC, DAC, Filter, and PLL are needed Recovered digital ISCAS A. Matsuzawa 10

11 Progress in A/D converter; video-rate 10b ADC ADC is a key for mixed signal technology. We have reduced the cost and power of ADC drastically; 1/ 2,000 for Power and 1/200,000 for the cost! CMOS technology attained it. dulling past 20 years Now Conventional product World 1 st Monolithic World lowest power SoC Core Board Level (Disc.+Bip) 20W $ 8,000 Bipolar (3um) 2W $ 800 CMOS (1.2um) 30mW $ 2.00 CMOS (0.15um) 10mW $0.04 Analog Devices Inc. Our developed. Our developed. Our developed. ISCAS A. Matsuzawa 11

12 Progress in high-speed ADC High speed ADC has reduced its power and area down to be embedded. World fastest 6b ADC ISSCC 2000 ISSCC b, 1GHz ADC 2W, 1.5um Bipolar 10 World fastest CMOS ADC 6b, 800MHz ADC 400mW, 2mm umCMOS ISSCC 1991 Pd/2 N [mw] World lowest Pd HS ADC 7b, 400MHz ADC 50mW, 0.3mm umCMOS Reported Pd of CMOS ADCs 10mW/Gsps 1mW/Gsps This Work 1 order down 1 10 Conversion rate [x100msps] ISCAS A. Matsuzawa 12

13 Early stage mixed signal CMOS LSI for CE Success of CMOS ADC and DAC enabled low cost mixed signal CMOS LSI. This also enabled low cost and low power digital portable AV products Model: Portable VCR with digital image stabilizing 6b Video ADC Digital Video filter System block diagram 8b low speed ADC;DAC 8b CPU ISCAS A. Matsuzawa 13

14 CMOS as analog device ISCAS A. Matsuzawa 14

15 CMOS as analog device CMOS has many issues as analog device, but also has a variety of circuit techniques Switch action Low Input current CMOS Bipolar Comment High gm - + CMOS is ¼ of Bip. Low Capacitance + - This results in Cp issue f T + + Almost same Only CMOS can realize switched capacitor circuits Voltage mismatch CMOS is 10x of Bip. 1/f noise CMOS is 10x to 100x of Bip. Low Sub. effect - + Offset cancel Analog calibration Digital calibration Embed in CMOS CMOS has a variety of techniques to address the self issues ISCAS A. Matsuzawa 15

16 GHz operation by CMOS Cutoff frequency of MOS becomes higher than that of Bipolar. Over several GHz operations have attained in CMOS technology Frequency (Hz) 100G 50G 20G 10G 5G 2G 0.35um Cellular Phone 0.25um 0.18um CDMA 0.13um f T 5GHz W-LAN f T : CMOS f T : Bipolar (w/o SiGe) /10 (CMOS ) RF circuits f T /60 (CMOS ) Digital circuits f f T Tpeak gm 2πC v 2πL sat in eff 1G 500M IEEE 1394 D R/C for HDD 200M 100M Year ISCAS A. Matsuzawa 16

17 CMOS technology for over GHz networking Digital consumer needs over GHz wire line networking. CMOS has attained 5Gbps data transfer. DVC IEEE1394 STB DVI HD-DVD World first 1394b transceiver For 1Gbps networking 0.25um 3AL_CMOS Test chip for 5Gbps wire line 0.18um 4AL_CMOS FPD 200ps 5Gbps Eye pattern ISCAS A. Matsuzawa 17

18 f T : MOS vs. Bipolar Even if f T of MOS is same as that of Bipolar, f T of MOS is easily lowered by parasitic capacitance. Because, gm of MOS is ½ to ¼ of that of Bipolar at the same current. gm MOS Ids Veff 2 V = eff min 2nU T n: 1.4 Veff/2: mV (actual ckt.) f T gm 2πCin 1 1 gm CMOS <, gm Bip Cin CMOS, Cin Bip 2 4 Bipolar gm U T ISCAS A. Matsuzawa 18 Ic kt U T 26mV q < (Same f T ) (Same operating current)

19 Parasitic effect: CMOS CT filter High frequency ckt. with scaled device is strongly affected from parasitic. Circuit optimization with layout and parasitic effect is needed. SIM w/o parasitic C SIM with parasitic C Optimized with parasitic C NO LPE LPE LPE OPTIMIZED Group Delay 3.5E E E+00 OK Group Delay 3.5E E E+00 NG Group Delay 3.5E E E+00 OK 2.0E E E E E E E+09 Freq. 1.5E E E E+09 Freq. 1.5E E E E+09 Freq. ISCAS A. Matsuzawa 19

20 Transistor issue: V T mismatch Larger gate area is needed for small V T mismatch. Scaling and proper channel structure can improve this. ΔV T (σ:mv) ΔV T T ox LW Larger gate area 0.4um Nch Tox scaling 0.13um Nch Boron w. Halo* 0.4um Pch Channel engineering 0.13um Nch In w/o Halo* ( LW μm ) * Morifuji, et al., IEDM ISCAS A. Matsuzawa 20

21 Development strategy and design system for mixed signal SoC ISCAS A. Matsuzawa 21

22 Full DVD system integration in 0.13um tech. Advanced mixed signal SoC has been successfully developed. Okamoto, et al., ISSCC um, Cu 6Layer, 24MTr CPU1 System Controller VCO ADC CPU2 Front-End Analog FE +Digital R/C PRML Read Channel Servo DSP AV Decode Processor Pixel Operation Processor IO Processor Gm-C Filter Back -End Analog Front End ISCAS A. Matsuzawa 22

23 System: DVD player Current electrical system is complicated and needs analog and memory. High-speed Analog-Digital Analog Optical Disc Optical Head Driver Head Amp Pre Amp Analog Front End Red Laser Photo-receptive Compound Red Laser Unit Read Channel CD DEM ODC Memory 4M DRAM Demodulation ECC AV Decoder Copy Protection 32bit MCU DRAM Embedded 16M SDRAM MPEG 2 Video AC-3 3 Audio Media Core Processor MPEG Algorithm Video Output AC-3 3 Output Stereo Output Servo DSP Servo DSP System Controller MCU System Controller MCU Console Panel :First-Gen. :Second-Gen. :Third-Gen. :Fourth-Gen. OS API ISCAS A. Matsuzawa 23

24 Scaled CMOS technology Current Scaled CMOS technology is very artistic. Matsushita s 0.13um CMOS technology Gate SiO 2 Seven lattices Si 100nm Transistor Cu Interconnection ISCAS A. Matsuzawa 24

25 Development strategy and system Product time slot is narrow and development cost is huge. Conventional analog LSI needs 2 or 3 re-designs. This can not be accepted to mixed signal SoC Advanced development strategy and design system must be established. 12 Mon 12 Mon 12 Mon 6 Mon 6 Mon 3 Mon Sales (A.U) 6x DVD ROM 8x DVD ROM 16x 12x DVD ROM DVD ROM 2 nd G 2.6G RAM Combo Combo First DVD ROM 2.6G RAM 4.7G RAM 97 Time 00 ISCAS A. Matsuzawa 25

26 Strategy for the mixed signal SoC System design Digital calibration for analog adjustment and unknown parameters. System optimization to reduce analog area and increase robustness. System verification Fast and accurate mixed signal system simulator with behavioral model to verify and optimize the mixed signal system. Create the target performance for circuit blocks. Circuit design Ultra fast and accurate circuit simulation for P.V.T and fluctuation analysis to verify the performance and robustness. Circuit optimizer to find the sweet spot of the circuit. Automated creation of analog behavioral model for system sim. Process and device development Develop suitable analog option device Early analog parameter extraction ( mismatch, temp. and voltage chara.) Monitor and control the analog parameters in Fab. ISCAS A. Matsuzawa 26

27 Design flow for mixed signal SoC Design flow from System to layout with top down and bottom up process should be used for designing mixed signal SoC. Accurate and a variety of device parameters is an another key. Device parameters (SPICE, Noise, Mismatch) Transistors Passives Substrate Package Cable Top down flow Unified design flow controller System design (Mixed signal level) Required SPEC Circuit design (SPICE +Behavioral) Layout design (Semi/Full automated) Bottom up flow Actual Circuit model Optimizer Parasitic effect ISCAS A. Matsuzawa 27

28 Multi-language simulation Multi-language simulation is 56x faster than SPICE with same accuracy. This will contribute to shorter design TAT and higher design quality. SPICE+Verilog D+Verilog A ISCAS A. Matsuzawa 28

29 Mixed signal system design Needs mixed signal Simulation for total signal processing. Many parameters and processing methods should be optimized. Real disc signal Finally, system is checked by real disc signals. Encoder/Decoder Methods Analog # of Taps Resolution PRECODER ENCODER Digital Processing Method M-RANDOM BER Filter ADC PR EQUALIZER VITERBI DETECTOR DECODER NOISE Boost level # of Taps # of Path ISCAS A. Matsuzawa 29

30 System simulation Perfection of the mixed signal system should be verified and optimized by system simulation. ADC resolution effect EPR4ML BER vs SNR (AD ENOB) 1.0E+00 RLL (2, 10) recorded data 1.0E-01 PR(3,4,4,3) waveform BER 1.0E E-03 4b 5b 4bit 5bit 6bit 7bit Viterbi decoded result 1.0E E E SNR (db) SNR 6b 7b System verification ISCAS A. Matsuzawa 30

31 LSI design using behavioral language Example: Analog Front End chip for ADSL system. LNA Output driver Buffer Buffer D/A Filter Filter A/D VCXO cont. Control logic ISCAS A. Matsuzawa 31

32 Hierarchical and behavioral system design System should be described in behavioral language, hierarchically. Analog: Verilog-A Logic: Verilog-D Analog behavioral model ISCAS A. Matsuzawa 32

33 Virtual System test using Verilog AMS and Matlab Matlab DMT modulation We can test the designed mixed signal system virtually, by using Verilog AMS and Matlab. Matlab DMT demodulation Conste llation ENC IFFT FIR Target LSI Verilog-AMS FIR FFT Conste llation DEC Matlab is used as a soft DSP > 66dB Q I MTPR TEST (DMT Carrier hole) f QAM constellation ISCAS A. Matsuzawa 33

34 Fitting between behavioral and Spice The combination of Verilog AMS and SPICE assures system perfection. Function check In Verilog-AMS Specification Verilog-A Verilog-A Sim Circuit design (SPICE+Verilog AMS) Fitting check SPICE Behavioral model extraction SPICE sim If needed ISCAS A. Matsuzawa 34

35 Unified mixed signal circuit simulator New design system can increase design speed, 10x to 50x. System level Specification Optimization Simulation Results Design flow controller Verilog-AMS +SPICE Documentation Test bench PVT analysis Spec sheet Behavioral model Optimization Simulation flow ISCAS A. Matsuzawa 35

36 Controller for automated simulation Simulation controller enables fast and automated simulation steps Project name Test bench (20 types) Parameter seep Spec sheet -PLL simulation results -Behavioral modeling Behavioral model calibration Behavioral model generation Optimization Design procedure ISCAS A. Matsuzawa 36

37 Issues of mixed signal SoC ISCAS A. Matsuzawa 37

38 V dd and CMOS scaling limits in analog Lowest analog operating voltage must be 1.2V -1.8V. Thus 0.18um 0.13um must be a scaling limit for analog. This results in salutation of f T and area reduction. Technology node (0.1um) Supply voltage (V) Digital デジタル (Upper) ( 上限 ) Technology テクノロジーノード node Digital デジタル (Lower) ( 下限 ) Analog アナログ (Upper) ( 上限 ) ITRS 99 Analog アナログ (Lower) ( 下限 ) ISCAS A. Matsuzawa 38

39 Optimization in channel parameters Larger gate length is needed for small mismatch and small noise circuit. However, this results in increase of cost and decrease of performance. Internal capacitance Transistor area Log (Magnitude) Output resistance DC Gain Frequency characteristics 1/f noise V T mismatch Small Log L Large ISCAS A. Matsuzawa 39

40 Cost up issue by analog & I/O Cost of mixed A/D LSI will increase when using deep sub-micron device, due to the increase of cost of non-scalable analog and I/O parts. Large analog on SoC must be unacceptable in near future I/O Analog Digital 0.35um 0.25um 0.18um 0.13um (0.35um : 1) Wafer cost increases 1.3x for one generation 0.35um 0.25um 0.18um 0.13um Chip area Chip cost ISCAS A. Matsuzawa 40

41 Solution 1: Scaled CMOS and use of digital Use scaled CMOS and not accurate passives. Address the issues by M/S compensation and system optimization. 0.35um Tr Accurate passive 0.35um 0.18um_0.13um Tr Not accurate passive (If low Vdd is acceptable) 0.13um Scaled CMOS Solution Analog compensation Digital calibration System optimization Pros Small Small area area (low (low cost) cost) High High speed speed Low Low power power Cons Low Low accuracy Sensitive to to Process Large Large 1/f 1/f noise noise ISCAS A. Matsuzawa 41

42 Example: Analog+ digital calibration tech. Area and power are reduced drastically, by scaled CMOS and digital tech. Y. Cong and R. L. Geiger, Iowa state university, ISSCC b 100MS/s DAC 1.5V, 17mW, 0.1mm 2, 0.13um 0.5 LSB INL, SFDR=82dB at 0.9MHz, 62dB at 42.5MHz +/- 9 LSB +/- 0.4 LSB Area: 1/50 Pd: 1/20 Calibration ISCAS A. Matsuzawa 42

43 Solution 2: Advanced packaging technology Some advanced packaging technologies will give the solution. Analog: using not so much scaled technology. Digital: using scaled technology Connect with low parasitic cap. and inductance. area pads LSI A (DRAM) Analog + LSI B (MPU) Digital LSI chip A LSI chip B bumps Chip On Chip technology Same capacitance as on-chip interconnection. No interconnection inductance ISCAS A. Matsuzawa 43

44 Future step: Mixed signal egg. Analog helps digital (digital network and storage ). Next step is digital must help analog. Mixed signal egg ( Analog yolk and white with digital shell) Digital shell Sustain the analog egg. Calibration and adjustment. Analog yolk and white Ultra-low power signal processing Ultra-high speed signal processing But, very delicate and fancy (Weak inversion) ISCAS A. Matsuzawa 44

45 Summary The mixed signal (Analog+Digital) is essential for almost all the systems. Not analog only, not digital only. Effective modeling of analog parts and high speed concurrent simulation with digital is vital for design. CMOS is very powerful technology for analog, as well as digital, but scaling limitation is reaching. The collaboration between analog and digital, and advanced packaging technology will bring us effective solutions. ISCAS A. Matsuzawa 45