Oxide-based resistive memories: from nanoscale switching to memory circuit

Transcription

1 Oxide-based resistive memries: frm nanscale switching t memry circuit M. Bcquet, D. Deleruyelle, J-M. Prtal, and Ch. Muller IM2NP UMR CNRS 6242 & Institut Carnt STAR Plytech Marseille, Université de Prvence IMT Technpôle de Château Gmbert Marseille Cedex 20 e mail: damien.deleruyelle@im2np.fr Innvative Memry Technlgies Minatec Grenble France

2 Cllabratrs MDM (Milan Italy) S. Spiga, M. Fanciulli Plitecnic di Milan (Milan Italy) F. Nardi, and D. Ielmini CEA-Leti (Grenble France) S. Tiran, L. Pernila, J. Buckley and B. De Salv

3 Outline 1. ITRS classificatin and RRAM technlgy 2. Frm nanscale switching t memry circuit Nanscale switching (C AFM) Mdeling (uniplar) Circuit simulatin 3. Summary

4 Outline 1. ITRS classificatin and RRAM technlgy 2. Frm nanscale switching t memry circuit Nanscale switching (C AFM) Mdeling (uniplar) Circuit simulatin 3. Summary

5 Classificatin f Resistive Switching devices Resistive Switching devices can be classified accrding t: Vltage plarity (i.e. uniplar/biplar) type f RS material (i.e. inrganic, rganic, mlecular ) Nature f the RS phenmenn (i.e. thermchemical, redx r electrnic) Surce: ITRS ERD/ERM Technlgy Wrk Grups Reprt n Emerging Research Memry Technlgies (2010)

6 Integrated memry structures Pt\NiO\W cell R HRS, R LRS vs Plug size RRAM Cell LRS value is quite independent frm plug area TE BE Interpretatin in terms f physical mechanisms: SET: Frmatin f metallic CF (reductin f NiO int Ni) TE BE RESET: Thermally assisted rupture f CFs assisted by Jule effect Dumas et al., Thin Slid Films, vl. 519, n. 11, pp ,

7 Outline 1. ITRS classificatin and RRAM technlgy 2. Frm nanscale switching t memry circuit Nanscale switching (C AFM) Mdeling (uniplar) Circuit simulatin 3. Summary

8 Experimental Details HP 4156 Analyser Resistive switching at a nanscale Lcal I(V) characteristics SMU 1 SMU 2 Measured areas Subsequent current 100mV Lcally frmed cnductive areas F. Nardi, Plitecnic di Milan, Internship at IM2NP in Marseille (09/ /2010)

9 Resistive switching at a nanscale C-AFM Prcedure 1. Scan at increasing vltages 2. 1mV (Read) Sequential Frming/Reset peratins +1 pa Virgin cell + 1V fa-pa amp. t ADC -1 pa 500 nm + 3V + 4V + 4.5V Evidence fr discrete nm-sized CFs within NiO after frming In LRS CF with size<10nm cntribute t the ttal cell current Deleruyelle et al., Appl. Phys. Express, vl. 4, pp (1 3),

10 Persistence f the CFs at a nanscale Current maps n a electrfrmed area at increasing times Initial time + 48h + 30days Mean CF radius vs time 50 nm Radial shrink f CFs bserved ver time Prbable nging lateral xidatin f CFs Deleruyelle et al., Appl. Phys. Express, vl. 4, pp (1 3),

11 Micrmetric versus nanmetric Set Reset Insulating pristine state LRS: multiple cnductive regins within NiO film HRS: nly few residual cnductive filaments after reset Deleruyelle et al., Appl. Phys. Express, vl. 4, pp (1 3),

12 Outline 1. ITRS classificatin and RRAM technlgy 2. Frm nanscale switching t memry circuit Nanscale switching (C AFM) Mdeling (uniplar) Circuit simulatin 3. Summary

13 Physical mdel f RESET peratin Mdel f Reset peratin RESET Reset has already been successfully described by cnsidering a self-accelerated thermal prcess* Basically this mdel cnsists is slving: 1D Heat Equatin Lateral disslutin velcity f the CF Assuming a temperature dependent cnductivity f the CF + current cnservatin CF edge Ruptured CF SET RESET * U. Russ et al., IEEE Trans. On Elec. Dev, vl. 56, 2009

14 Physical mdel f SET peratin Mdel f Set peratin During SET, NiO is assumed t be reduced int Ni leading t the frmatin f a metallic CF: SET The reactin velcities fr bth reductin and xidatin prcesses may be expressed classically by the Bulter- Vlmer relatinship: Set and Reset prcess can be then cmbined in a single master equatin t cntinuusly accunt fr bth prcesses: di: /1.360 Redx-rate (SET) Thermal disslutin-rate (RESET) Bcquet et al., Appl. Phys. Lett., vl. 98, p ,

15 Cnfrntatin t exp. data Quasi-static I-V characteristics I Reset -I Set & R LRS -I Set dependency NiO 160nm [1] NiO 30nm NiO 30nm [2] [1] C. Cagli et al. Prc. IEEE IEDM 2008, p. 755, 2008 [2] M.J. Lee et al. Prc. IEEE IEDM 2007, p. 771, 2007 Cntinuus mdel accunting fr bth SET/RESET Excellent agreement with numerus quasi-static and dynamic experimental data Bcquet et al., Appl. Phys. Lett., vl. 98, p ,

16 Cnfrntatin t exp. data Quasi-static I-V characteristics V Reset /V Set vs ramp speed NiO 160nm [1] NiO 30nm NiO 30nm [2] [1] C. Cagli et al. Prc. IEEE IEDM 2008, p. 755, 2008 [2] M.J. Lee et al. Prc. IEEE IEDM 2007, p. 771, 2007 Cntinuus mdel accunting fr bth SET/RESET Excellent agreement with numerus quasi-static and dynamic experimental data Bcquet et al., Appl. Phys. Lett., vl. 98, p ,

17 Outline 1. ITRS classificatin and RRAM technlgy 2. Frm nanscale switching t memry circuit Nanscale switching (C AFM) Mdeling (uniplar) Circuit simulatin 3. Summary

18 ReRAM Nn vlatile Flip-Flp Flp (RNVFF) Pwer-dwn sme digital blck t save pwer in mbile applicatin Classical slutin : Retentin Flip-Flp Flp (balln r shadw latch) with pwer- gating * Y. Matsuya, et al., IEEE JSSC, vl. 32, 1997 RESET_EN MP1 READ_EN Intrductin f Nn-Vlatile Blck based n Uniplar ReRAM N Need fr pwer gating and virtual biasing, n leakage current during idle state IN MP2 RRAM SAVE_EN Nn vlatile blck 0 1 OUT D Q Flip-Flp (Master slave) CLK

19 ReRAM Nn vlatile Flip-Flp Flp (RNVFF) Nrmal peratin Save data Pwer-ff Restre data Nrmal peratin Pwer-n IN Nrmal peratin mde OUT IN OUT I RERAM Nrmal Nn-Vlatile blck fully islated. Flip-Flp Flp input (D) remains preserved.

20 ReRAM Nn vlatile Flip-Flp Flp (RNVFF) Nrmal peratin Save data Pwer-ff Restre data Nrmal peratin Pwer-n CLK edge 0 IN Save data mde OUT IN OUT Set ReRAM I RERAM Save (SAVE_EN = 1 ) ReRAM access t save data, while Flip-Flp Flp input (D) remains preserved

21 ReRAM Nn vlatile Flip-Flp Flp (RNVFF) Nrmal peratin Save data Pwer-ff Restre data Nrmal peratin Pwer-n IN OUT IN OUT I RERAM Pwer-ff ff (V DD = 0V) (V DD Data stred in ReRAM,, circuit biasing fully dwn (n electrical activity)

22 ReRAM Nn vlatile Flip-Flp Flp (RNVFF) Nrmal peratin Save data Pwer-ff Restre data Nrmal peratin Pwer-n CLK edge IN Read data & Reset mde 0 OUT IN OUT I RERAM Reset ReRAM Read & Reset (READ_EN = 0 RESET_EN = 0 ) Read ReRAM and start the reset prcess, the restred data is captured in the Flip-Flp Flp

23 ReRAM Nn vlatile Flip-Flp Flp (RNVFF) Nrmal peratin Save data Pwer-ff Restre data Nrmal peratin Pwer-n IN OUT I RERAM Reset ReRAM cnt Reset & Nrmal (RESET_EN = 0 ) ReRAM reset cntinues, while Flip- Flp input (D) remains preserved

24 ReRAM Nn vlatile Flip-Flp Flp (RNVFF) Nrmal peratin Save data Pwer-ff Restre data Nrmal peratin Pwer-n IN Nrmal peratin mde OUT I RERAM Nrmal Nn-Vlatile blck fully islated, while Flip-Flp Flp input (D) remains preserved

25 Outline 1. ITRS classificatin and RRAM technlgy 2. Frm nanscale switching t memry circuit Nanscale switching (C AFM) Mdeling (uniplar) Circuit simulatin 3. Summary

26 Summary Like ther ReRAM technlgies (i.e. ECM,VCM,EE ) integrated cells based n TCM are prmising candidates fr future sub 16-nm ndes: CMOS cmpatible Reset current can be scaled-dwn using 1T-1R structures Pssible integratin in 3D arrays / embedded r distributed applicatins Regarding physical mechanisms invlved in resistive-switching: Filamentary cnductin suggested by dc-characteristics n integrated memry structures was cnfirmed at a nanscale by C-AFM measurements A cntinuus physical mdel accunting fr bth SET/RESET peratins was develped, based n EC prcesses Implementatin f physical mdel in circuit simulatrs allws the investigatin f nvel embedded memry arrays r distributed cells in CMOS circuits

27 Thank yu fr yur attentin Institut Matériaux Micrélectrnique Nansciences de Prvence UMR 6242 CNRS, Universités Paul Cézanne, Prvence et Sud Tuln-Var