Computer System Structures cz:struktury počítačových systémů

Transcription

1 Computer System Structures cz:struktury počítačových systémů Version:. Lecturer: Richard Šusta ČVUT-FEL in Prague, CR subject AB35 Switch Hazards debouncing

2 ebouncing Switches What is switch bounce? -The non-ideal behavior of the contacts that creates multiple electrical transitions for a single user input. 3 Switch bounce from a single depress/release of switches ebouncing Switches [Source: L. Traylor: Computer Techniques, Oregon 29] 4 2

3 Simple ebouncing E2 - KEY[3..] +5 VC Input KΩ 74HC245 V CC V µf hysteresis V RC Integrator debouncer and initiator... After E2 board is switched on KEY[3..] will hold "" state for several milliseconds until their capacitors are charged. KEY inputs are useful for automatic initialization of your logic! 5 KEY[n] V CC KΩ u c (t) river E2 - debounced KEY inputs CMOS driver (74HC245) used in E2 gives output when input voltage is from 4% to 6% Vcc. true, false, driver output in FPGA led to input KEY[n] V µf u c (t)=v CC (-e -t /τ ), τ=r.c= =,s U c (t) capacitor C is discharged by resistance of switch contact press button τ 2τ 3τ Clock inputs can be driven by debounced KEY inputs, but not by switches SW. release button or switching on power 95% Vcc 86,3% Vcc 63,2% Vcc t - time 6 6 3

4 Mapping of Physical World When a button is pressed, it is usually asserted (true). However, its physical construction may output this as a LOW VOLTAGE. Logic value Button Logic value Button Pressed Pressed Released Released (a) Positive Logic (b) Negative Logic There are two logic levels (T - True and F- False or '' and '') and two voltage levels (H - High and L - Low) or button states (pressed, released). The digital designer may choose either voltage level or state (but not both!) to represent logic truth for each input or output; For example, an H may represent '' on input X, but H can be '' on output Y, if it is required. 7 Simple synchronous circuits Registers 4

5 Max-warning of Maxplus2 Avoid using and JK flip-flops circuits from maxplus2 library Prefer storage primitives of uartus, e.g. latch, dff, jkff, and tff! o not copy schematics from web - they were frequently designed for different logic circuits. 9 An example of its possible diagram 2bit register /5 FF FF Výstup Hodiny Inicializace FF= Flip-Flop Asynchronous clear on =''. Asynchronous clear is intended for initialization after power up, connect it to KEY[n] on E2 board If =, rising edge of samples i inputs a sends their values to i outputs. 5

6 An example of its possible diagram 2bit register 2/5 SCLR SCLR FF FF Výstup Asynchronous clear on =''. If = and SCLR=, then rising edge clears i outputs. If = and SCLR=, then rising edge of samples i inputs a sends their values to i outputs. An example of its possible diagram SL SCLR SL SCLR 2bit register 3/5 FF FF Asynchronous clear on =''. If = and SCLR=, then rising edge clears i outputs. If = and SCLR= and SL='', then rising edge of sets i outputs to ''. If = and SCLR= and SL='', then rising edge of samples i inputs a sends their values to i outputs. 2 6

7 Wrong register s Enable ENA-Enable Clock forbidden L SCLR o not insert any gates into clock path. Invertors are allowed, other gates can cause unwanted clock edges. 3 FFE - -flip-flop with Enable ENA-Enable Clock danger clock gating Flip-flop with enable E= E= ENA A -data ENA-Enable Clock Asynchronous clear active-low FFE PRN ENA inst8 Flip-flop with enable uartus primitive FFE FF register always stores information on positive clock transitions. This method is generally preferred over any type of clock gating, i.e. over any combinational logic inserted into clocks, since it avoids the potential for malfunctions of the circuit. 4 7

8 An example of its possible diagram SL SCLR EN FFE SL SCLR EN 2bit register 4/5 FFE ENA FFE ENA The inputs are the same as in the previous circuit, but all synchronnous operations will be enabled on EN=. Asynchronous clear = does not depend on clocks and it will appear immediately. 5 An example of its possible diagram SL SCLR EN 2bit register (FFEAS) 5/5 EN SCLR SL FFEAS PRN inst ENA ASATA ALOA SCLR SLOA FFEAS PRN inst ENA ASATA ALOA SCLR SLOA 8

9 You can freely use all synchronous inputs simultaneously, but not more than one asynchronous input! ata for ALOA and SLOA inputs Asynchronous load Synchronous clear Synchronous load Example of FFEAS FFE FFEAS PRN inst ENA ASATA ALOA SCLR SLOA Asynchronous set Asynchronous clear 7 Simple synchronous circuits Shift Registers for Snake 9

10 Shift Register shifting the binary information held in each cell to its neighboring cell... 9 Bidirectional Shift Register Serial-left-in Right-left Serial-right-in Serial-out Asynchronous clear active-low Clock 2

11 Bidirectional Shift Register with Synchronous Load SLOA RIGHT SLI SRI Serial - out A 2 2 Simple synchronous circuits Binary counters to 2 N- and frequency dividers modulo 2 N

12 2 3 4 carry <-> borrow 5 Inside: Natural number Outside: 4-bit encoding Counter Carry/Borrow Turn x notches counterclockwise to add x Turn y notches clockwise to subtract y 4 23 Counters are used for controling of sequences and program executions. There are two basic categories of counter behaviors: Asynchronous or ripple counters produce the outputs in sequence similar to a ripple effect. Outputs of synchronous counters are available at the same time. For cascading of such counters, ripple carry or look-ahead carry logic are used to accelerate their operations. Counters 24 2

13 + /5/24 General schematic of binary counter up n - bus width n-bits n-bit adder + n Register n-bits [n-..] [n-..] or KEY[n] On each rising edge to counter value is incremented by. It is possible utilize FF flip-flops or FFE flip-flops with enable inputs. 25 Adder + in hardware 26 3

14 + /5/24 bit adder+ S 2bit adder+ S 3bit adder+ S A A A S S Karnaugh maps of adder + A A A A A S Number of gates is O(n 2 ), where n is bus width of S. S2 A2 A A S=not A S=A xor A S2=A2 xor (A and A) Equation:S i = A i xor (A i- and A i-2 and A and A ); i=..n- 27 ivider by 2 bit adder Output Combinatorial Logic Clock signal '' Output 28 4

15 Simple synchronous circuit 29 Counter.. / ivider by 2 with enable enable bit adder +/+ xor = xor = not not necessary, but better '' Enable Hodiny Output On enable=, counter increments by, on enable=, counter inc]rements by +. Alternatively: We can use FFE flip-flop 3 5

16 Counter..3 / divider 4 2bit adder+ Output Clock 3 Counter..5 / ivider by 6 i = i xor ( i- and i-2 and and and EN); := xor EN (EN-enable) := xor ( and EN) 2:= 2 xor ( and and EN) 3:= 3 xor (2 and and and EN) 32 6

17 ripple effect Counter..5 / ivider 6 with iteration = xor C; C=EN; i = i xor Ci; Ci=Ci- and i-; 33 Ripple and lookahead in hardware 34 7

18 ripple (cz:drhlice) Etymology: Middle English repylle from old high German riffila=saw: a large instrument like a comb (cz:hřebínek) for removing seeds and other matter from flax or hemp (cz:len nebo konopí) Ripple () 35 ripple (cz: zvlnit, zčeřit) - become covered with or form in small waves or undulations (cz:vlnění), to flow in small waves, to fall in soft undulating folds or wavy lines Ripple Effect = omino Effect/Chain Reaction Ripple (2) 36 8

19 Ripple Counters asynchronous 37 J Recommended Flip-flops for Counters jkff dff Clk K Clk Clk divider by 2 Counters can be designed with either J-K or -type flip-flops, but they will be made from -flip-flops inside Cyclone II. Warning: Be very careful with schematics found on networks. Many of them suppose classic flip-flops from 74 series that have different behavior than uartus flip-flops primitives. 38 9

20 produces one pulse for every two clock pulses input. Counters The counter counts once for every two clock pulses. The frequency at is half of that at the clock. Sometimes called a divider. 39 ivide-by-4 Ripple (Asynchronous) Counter -Frequency divider not not Timing diagram... st FF can operate on rising or falling edges of clock signal, as required, the following FFs are trigged by falling edges to count up. 4 2

21 ivide-by-8 Ripple Counter Recycles back to 4 This ripple counter counts up ivide-by-6 Ripple Counter 2 Clock

22 ivide-by-6 Ripple Counter This ripple counter counts down! 2 Clock 2 3 To count down, subsequent FFs are trigged by rising edges. 43 ivide-by-6 Ripple (Asynchronous) Counter Ripple counter counting up 2 Clock 2 3 One bit only changes at a time > > > < If a next state is greater than current state, then all intermediate states will be less than current and next state -> we can easily decode next states (with exceptions of )

23 ivide-by-6 Ripple Counter (Cont d) Propagation delay happens in operations of flipflops. Time delay for all output clocks compared with their input clocks. Outputs are not available at the same time, it is an asynchronous counter. 45 ivide-by-6 Ripple (Asynchronous) Counter Counter down behaves by different way 2 Clock 2 3 Only one bit changes at a time < < < > All intermediate states form increasing sequence -> more difficult decoding of next states - counters up are more suitable for dividers

24 Counters modulo M 2 n 47 etector of binary number M Asynchronous divider modulo M N-2 N- M- M Modulo 2 N > M To detect number 6 = "", we create logical AN of O2 and bits

25 Asyn. Counters with MO no. < 2 n We have to use a ripple counter up 2 CLR CLR CLR Clock NAN Output MO-6 counter produced by clearing (a MO-8 binary counter) when count of - occurs, i.e. 6 or 7. The counter is cleared, so 7 will never occur. 49 MO-6 Clock NAN Output Temporary state of MO-6 counter 5 25

26 INPUT /5/24 ivider by 3 To create mod N<2 n divider: Create ripple counter up from n flipflops. etermine which flip-flops will be in state "" at count N and connect their outputs to inputs of NAN that clears all flip-flops. Library for AB35 - Structures of Computers System FF FF FF FF PRN NOT PRN NOT PRN NOT PRN NOT inst inst2 inst3 inst32 inst inst2 inst3 inst5 NAN3 inst4 OUTPUT IV3 decoding output "-", i.e. 3 and 5, because the counter never reaches 5. 5 Maximum frequencies of frequency dividers MO 2 n ripple counter used as a frequency divider, i.e. we are interested only in its main scale bit, has maximum input frequency equal to f max2 - maximum frequency of divider 2. MO M<2 n ripple counter used as a frequency divider has maximum input frequency f maxm that is determined by propagation times of the whole clear logic loop, i.e. f maxn < f max2 / n 52 26

27 Cascading Asynchronous Counters Larger asynchronous (ripple) counter can be constructed by cascading smaller ripple counters. Connect last-stage output of one counter to the clock input of next counter so as to achieve higher-modulus operation. Example: A modulus-5 ripple counter constructed from a modulus-5 counter and a modulus- counter and modulus counter. divider5asyn dividerasyn dividerasyn INPUT OUTPUT IV5 IV IV IV5 inst8 inst9 inst7 53 Synchronous Counters are different than asynchronous 54 27

28 + /5/24 General schematic of synchronous counter up n - bus with width n-bits n-bit adder + n Register n-bits [n-..] [n-..] etector of binary number M- SCLR or KEY[n] M-2 M- We detect number M-, just and of its bits. The detector output is connected to synchronous clear of register in its active level, usually. 55 Warning Asynchronous inputs of synchronous counters can be used only for power up initialization, not as working inputs

29 inst3 NAN2 /5/24 Synchronous counter 7462 with modulo LN A B C ENT A B C OUTPUT OUTPUT OUTPUT S62A S62B S62C ENP RCO etector of number 5 inst COUNTER OUTPUT S62 Now, we must test 5 for dividing by 6! 57 Is a synchronous input? Yes, signal path from is connected to inputs of FF, thus, changes of will have influence to outputs on rising edges of clocks -> is synchronous input. 29

30 Synchronous versus ripple counter Clock Grows to 4* Bit Bit 2 Bit 3 Bit 4 synchronous counter ripple (asynchronous) counter 59 Simulation of divider 5 6 3

31 Time Simulation ripple / synchronous Ax ripple divider MO-5 Sx synchronous MO-5 divider prolonged by output loads! Synchronous flip-flop receive clock request to change their outputs at one instance of time but they certainly change at very near instances of time. 6 Synchronous Counter/ivider Outputs can appear in different times Some possible changes of outputs any outputs from to are possible It is impossible to designed hazard free combination circuits for outputs of synchronous counters. 62 3

32 Synchronous counter o not use clearing mechanisim of asynchronous dividers with synchronous counters! It does not work! 63 eadly construction of counter MO-3 Suicide circuit Asynchronous clear surely resets all flip-flops to, i.e. kills them all to, but the designer s job may be dead as well! It can cause random glitches (hazards), especially on higher frequencies

33 inst34 AN2 /5/24 Synchronous Counter 7492 with Wrong Asynchronous Clear inst3 LN A B C N UP CLR 7492 A B C CON BON COUNTER OUTPUT OUTPUT OUTPUT S92A S92B S92C OUTPUT S92CLR Use great care with unknown circuits - e.g. counter 7492 above is synchronous but CLR and LN inputs are both asynchronous 65 Identifying type inputs from schema of 7492 Any inputs of circuits that have connection to asynchronous input CLR or PRE of flip-flops are asynchronous inputs. 33

34 Simulations only simulate! The both dividers divide by 6, but only on the screen, in hardware, the correct divider is only the circuit with 62 circuit Cascading synchronous counters 34

35 Cascading Counters Asynchronous: Main Scale Bit () of a lower counter is usually connected to the clock of a higher counter Synchronous: common clock + carry/borrow propagation logic carry-borrow propagation logic common clock 69 Cascading ecadic Counters 7492 Clock UP One clock input only can be in ""! Notice clear on ""! 7492 LN A A B B C C N CON UP BON CLR inst3 COUNTER GN 7492 LN A A B B C C N CON UP BON CLR inst5 COUNTER GN elic6 CON: carry BON: borrow by propagating carry/borrow 7 35

36 Cascading Counters Cascading of synchronous counters can be performed by many ways, see next slides, e.g. Carry/Borrow (7492, 7493), MinMax + Ripple Carry (749), Common Clk + ENT/ENP gates (7462) 7 Cascading ecadic Counters 7462 Hodiny INPUT inst inst inst3 inst4 LN A B C ENT ENP LN A B C ENT ENP 7462 COUNTER LN A B C ENT ENP COUNTER LN A B C ENT ENP 7462 COUNTER LN A B inst5 C ENT ENP 7462 COUNTER COUNTER A B C RCO A B C RCO A B C RCO A B C RCO A B C RCO with ripple mode of carry ENP=enable 72 36

37 37 Advance Cascading ecadic Counters 7462 Hodiny INPUT COUNTER A LN B C ENP ENT A B C RCO 7462 inst COUNTER A LN B C ENP ENT A B C RCO 7462 inst COUNTER A LN B C ENP ENT A B C RCO 7462 inst3 COUNTER A LN B C ENP ENT A B C RCO 7462 inst4 COUNTER A LN B C ENP ENT A B C RCO 7462 inst5 with the carry look-ahead 73 Summary: Synchronous/Asynchronous

38 The counter is referred as synchronous All outputs change synchronously with clock synchronous signal, but with possible hazards Hodiny Output The clock inputs of all flip-flops are connected together 75 The counter is referred as synchronous but with asynchronous clear All outputs change synchronously with clock Output synchronous signal, but with possible hazards Clock The asynchronous input has immediate influence to outputs, it does not depend on clocks 76 38

39 Asynchronous ripple counter The counter is referred as asynchronous/ripple counter synchronnous - the first flip-flop operates synchronously with clock 2 ripple s with increasing delays Synchronous inputs cannot be implemented. Why? 77 Inputs Precondition: Combinational circuits can produce unwanted outputs called hazards, see lecture 2. Rule: All inputs effecting outputs immediately, i.e. asynchronous and clock inputs, require hazard free signals. Conclusion: Outputs of combinational circuits must not be connected to asynchronous inputs or clock inputs. Exception: Well known, deeply analyzed cases, and situations, when possible hazards can be ignored, as changes of divider frequency

40 ASYNCHRONOUS COUNTER IS WELL KNOWN, EEPLY ANALYZE CASE OUTPUT A OUTPUT A CLOCK_5 INPUT JKFF PRN J K inst NOT inst6 JKFF PRN J K inst2 NOT inst5 JKFF PRN J K inst3 OUTPUT A2 inst NAN2 79 4