Counters. ENT 263 Digital Electronics
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1 Counters ENT 263 Digital Electronics
2 Objectives Describe the difference between an asynchronous and a synchronous counter Analyze counter timing diagram Analyze counter circuits Determine the sequence of a counter and more
3 Counting in Binary The next bit changes on every fourth number LSB changes on every number. The next bit changes on every other number. LSB MSB
4 Asynchronous Counter Operation In an asynchronous counter, the clock is applied only to the first stage. Subsequent stages derive the clock from the previous stage. Asynchronous binary counter 2-bit asynchronous binary counter 3-bit asynchronous binary counter 4-bit asynchronous binary counter Asynchronous decade counter
5 2-bit asynchronous binary counter
6 3-bit asynchronous binary counter
7 4-bit asynchronous binary counter
8 Asynchronous decade counter
9
10 Propagation Delay
11 Synchronous Counter Operation Clock signal supplied to all Flip-flops Synchronous binary counters 2-bit counter 3-bit counter 4-bit counter Synchronous BCD decade counter
12 2-bit synchronous binary counter 0 1 0
13 3-bit synchronous binary counter
14 ND gate utputs is IGH 4-bit synchronous binary counter
15 Synchronous BCD decade counter
16 Up/Down Synchronous Counters 3-bit up/down synchronous counter Up/down decade synchronous counter
17 3-Bit Up/Down Synchronous Counter
18
19
20 Up/Down Decade Synchronous Counter
21 Design of Synchronous Counters General clocked sequential circuit Next State Present State
22 Steps used in the design of sequential circuit 1. Specify the counter sequence and draw a state diagram 2. Derive a next-state table from the state diagram 3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop 4. Transfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop. 5. Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input. 6. Implement the expressions with combinational logic, and combine with the flip-flops to create the counter.
23 State diagram for a 3-bit Gray code counter
24 Next-state table for a 3-bit Gray code counter. Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q
25 Transition Table for a J-K flip-flop Output Transitions Flip-flop Inputs Q N Q N+1 J K X X 1 0 X X 0 Q N : present state Q N+1: next state X: Don t care
26 Example of the Mapping Procedure
27
28 Three-bit Gray code counter.
29 Example: Design a counter with the irregular binary count sequence as shown in the state diagram. Use J-K flip-flops
30 Next-state table Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q
31 Transition Table for a J-K flip-flop Output Transitions Flip-flop Inputs Q N Q N+1 J K X X 1 0 X X 0
32 K-MAP
33 THE COUNTER CIRCUIT
34 Example : State diagram for a 3-bit up/down Gray code counter.
35 J and K maps for Table The UP/DOWN control input, Y, is treated as a fourth variable.
36 Three-bit up/down Gray code counter.
37 CASCADE COUNTERS Two cascaded counters (all J and K inputs are HIGH).
38 A modulus-100 counter using two cascaded decade counters.
39 Three cascaded decade counters forming a divide-by frequency divider with intermediate divide- by- 10 and divide-by-100 outputs.
40 Example: Determine the overall modulus of the two cascaded counter for (a) and (b) For (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536 for (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400
41 A divide-by-100 counter using two 74LS160 decade counters.
42 Cascaded Counters with Truncated Sequences A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter) = 65,536 65,536 40,000 = 25,536 63C0 16
43 COUNTER DECODING * To determine when the counter is in a certain states in its sequence by using decoders or logic gates. Decoding of state 6 (110). Active High Decoding
44 Example: Implement the decoding of binary state 2 and binary state 7 of a 3-bit synchronous counter. Show the entire counter timing diagram and the output waveforms of the decoding gates. 2 = 010 (Q 2 Q 1 Q 0 ) 7 = 111 (Q 2 Q 1 Q 0 )
45 A 3-bit counter with active-high decoding of count 2 and count 7.
46 Decoding Glitches A basic decade (BCD) counter and decoder.
47 Outputs with glitches from the previous decoder. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.
48 The basic decade counter and decoder with strobing to eliminate glitches. Strobing: To enable the decoded outputs at a time after the glitches have had time to disappear. Using LOW level of active- HIGH clock to enable the decoder.
49 Strobed decoder outputs for the circuit
50 Counter Applications
51 Simplified logic diagram for a 12-hour digital clock.
52 Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).
53 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.
54 Functional block diagram for parking garage control.
55 Logic diagram for modulus-100 up/down counter for automobile parking control.
56 Parallel-to-serial data conversion logic.
57 Example of parallel-to-serial conversion timing for the previous circuit
58 Thank You Intan berlian walaupun di atas lumpur dia pasti akan bercahaya, akan tetapi najis ayam walaupun diletakkan di atas meja tetap akan berbau busuk jua - Cendikiawan
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