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1 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 1/11 Exam 2 Instructions: Turn off all cell phones, beepers and other noise making devices Show all work on the front of the test papers Box each answer If you need more room, make a clearly indicated note on the front of the page, "MORE ON BCK", and use the back The back of the page will not be graded without an indication on the front You may not use any notes, HW, labs, other books, or calculators This exam counts for 22% of your total grade Read each question carefully and follow the instructions You must pledge and sign this page in order for a grade to be assigned The point values for problems may be changed at prof s discretion Put your name at the top of this test page (and, if you remove the staple, all others) Be sure your exam consists of 11 distinct pages Sign your name and add the date below Good Evening! Welcome! Good luck & Go Gators!!! For each circuit design, equations must not be used as replacements for circuit elements For each mixed-logic circuit diagram, label inputs of each gate with the appropriate logic equations Boolean expression answers must be in lexical order,( ie, / before, before B, & D 3 before D 2 ) Label the inputs and outputs of each circuit with activation-levels For K-maps, label each grouping with the appropriate equation PLEDGE: On my honor as a University of Florida student, I certify that I have neither given nor received any aid on this examination, nor I have seen anyone else do so SIGN YOUR NME DTE (29 March 2010) Regrade comments below: Give page # and problem # and reason for the petition Page vailable Points TOTL 100

2 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 2/11 Exam 2 [1%] 1 Design a system that sequences through the following outputs: 3, 7, 0, 1, 3, 7, 0, etc The 2 min system must asynchronously reset to output the 3 when Start (active-low) goes true When the sequence output is 7, the active-low output Z should be true Use a JK-FF for the most significant bit of the design, a T-FF for the least significant bit, and a D-FF for any other bits you might need Note: ll the given FFs have active-low asynchronous clear and set inputs Use the minimum number of flip-flops and the minimum number of other SSI gates necessary to solve this problem 5 min a) Complete the next-state truth table You may not need all the rows and/or columns 5 min b) Find the required simplified (MSOP or MPOS) equations

3 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 3/11 Exam 2 5 min 1 c) Design the complete circuit, minimizing the total number of components, but using the JK-FF and T-FF (and D-FF(s), if necessary) as described previously ll inputs and outputs of the circuit should be clearly indicated coming into or out of the below box Your design must include the circuitry necessary to asynchronous re-start the system at output 3 when the Start(L) signal goes true

4 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page /11 Exam 2 [6%] 2 nswer the following questions about a state machine designed with one EEPROM, one J-K flip, and all other flip-flops of type D or T (2%) a) What is the size of the EEPROM [addresses x data bits] if the state machine has inputs, 2 min 3 outputs, and 5 states? (2%) b) What is the size of the EEPROM [addresses x data bits] if the state machine has inputs, 2 min 2 outputs, and 9 states? (2%) c) What is the size of the EEPROM [addresses x data bits] if the state machine has 0 inputs, 2 min 1 output, and states? [2%] 3 How do we protect a ROM (and the rest of a microcontroller system) from bad software? 2 min [5%] Draw a switch circuit for an active-low input 5 min signal, X(L) Draw the switch in the true position Do NOT draw a layout Draw a timing diagram of the bouncing that will occur on this non-debounced switch circuit as the switch goes from the true to false positions H X(L) L

5 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 5/11 Exam 2 [2%] 5 Draw an active-low LED circuit for an activelow output, Y(L) Do NOT draw a 1 min layout [2 3%] 6 D-FF with asynchronous set and clear is shown below dd the circuitry necessary to add min an active-high synchronous set, SET(H) Show your work [2 3%] 7 D-FF with asynchronous set and clear is shown below dd the circuitry necessary to add min an active-low synchronous clear, CLR(L) Show your work [2%] 8 What is the difference between a functional and a timing simulation in Quartus? 2 min [2%] 9 What is Top-Level Entity in Quartus? 2 min [3%] 10 If you build a counter that is meant to count down from 37 to 0, but with each single cycle of 2 min the clock input switch the count has the following sequence, 37, 35, 31, 27, 2, 20, 18,, what is the most likely problem?

6 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 6/11 Exam 2 [10%] 11 The following figure shows a simplified circuit diagram ssume that all of the inputs and 10 min outputs are active-high The ROM contents are given in the below table (This problem is nearly identical to a problem in homework 8 that was also done in class) (8%) a) Derive the SM chart for this circuit Show LL work, ie, use at least part of the below blank table (Do not miss part b below) Contents of the ROM ddr Value Hex Hex 0 $11 1 $11 2 $18 3 $0D $00 5 $00 6 $08 7 $07 (2%) b) If input X in part a is changed to active-low, describe all the changes in the truth table and SM (if any); you may want to redraw the SM (with the changes)

7 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 7/11 Exam 2 [11%] 12 nswer the following questions about the SM chart for the IEEE SoutheastCon 2010 Hardware Competition (Robot) controller The following signals are active-low: Charge, Cnt0, and Low; all the other signals are active-high (%) a) Draw the voltage timing diagram (showing all the relevant signals) when in the Start min state, Enough goes from false to true to false to true before the next active-clock edge (and stays there through the clock edge) What is the next state? 00 Charge Start 0 Enough 1 LdCnt Next state is (7%) b) Complete the next-state truth table Draw the minimum 5 min number of rows necessary The state bits should be entered in counting order E Cn F L Li Q 1 Q 0 Q 1 + Q 0 + C Ld D S R 0 0 DecCnt 01 lmost Scoot 0 Cnt Charging Charge 0 Full 1 10 Running Run 0 Low 1 0 Light 1

8 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 8/11 Exam 2 D Data Bits D 0 $00 $00 [20%] 13 Given as many 32x EEROMs as needed and only one 16x8 SRM, design a 8x8 memory 2 min module (with Chip Select, CS) that has 16x8 of SRM starting at address 0, followed immediately with 32x8 of EEPROM The 16x8 of SRM must start at address 0 and the first address of the 32x8 of EEPROM must immediately follow the last SRM address dd the minimum number of memory devices and the minimum number of additional (non-pld) components required ( %) a) Draw vertical and horizontal lines in the box below and label each resulting box with the 5 min memory type and size, using only the defined types and sizes given above lso, fill in the subscript on the D at the top left and the maximum address at the bottom right Increasing ddresses = max address ( %) b) What is the address and data ranges for each of the memory components drawn above (in 5 min binary and in hex)? 16x8 SRM: EEPROM(s):

9 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 9/11 Exam 2 ( %) 13 c) Design the required memory device below dd the minimum number of additional 5 min memory components and SSI gates necessary (no MSI gates or PLDs) dd address subscripts as needed and cross out unneeded address and data pins Use labels instead of wires for the design lso, write the equations for each CS; but you must make a complete circuit diagram Show all connections with either labels or wires, just as in Quartus 32 x EEPROM 16x 8 SRM CS D 0 D 1 D 2 D WE CS D 0 D 1 D 2 D 3 D D 5 D 6 D 7 D 0 D 1 D 2 D 3 D D 5 D 6 D 7 D 8 D 9 D 10 D 11 CE(L) R/W

10 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 10/11 Exam 2 [19%] 1 block diagram of your lab 6 is shown here The MUX C table has changed INPUT Bus REG Bus REGB Bus OUTPUT Bus CLK MS1 MS0 REG Bus Cin MSC2:0 MS1:0/ MSB1:0 Bus Selected as Input to Combinatorial Logic 00 INPUT Bus 01 REG Bus 10 REG B Bus 11 Output Bus Out + B + Cin (from switch) Out + B + previous Cout 3 MUX s REG MUX B s REG B Combinatorial Logic MUX C s MSB1 MSB0 CLK REGB Bus Cout OUTPUT Bus MSC ction 000 REG Bus to OUTPUT Bus 001 REGB Bus to OUTPUT Bus 010 complement of REG Bus to OUTPUT Bus 011 bit wise ND REG/REGB to OUTPUT Bus 100 bit wise OR REG/REGB Bus to OUTPUT Bus 101 shift REG Bus left one bit to OUTPUT Bus 110 sum of REG Bus & REGB Bus with Cin (switch) to OUTPUT Bus 111 sum of REG Bus & REGB Bus with Cin = previous Cout to OUTPUT Bus ( %) a) ssume that you can add small additional circuits to the circuit described with the above block diagram The purpose of these additional circuits is to enable the LU to be used to add two 8-bit numbers using two -bit additions (with other non-addition instructions possibly in between) Up to two more control word bits are allowed in this design The user can NOT manipulate the Cin switch to accomplish this task, ie, the design must be controlled by your circuit and the additional control bits Your job in this problem is to deal with the carry bit only 7 min dd the required new circuitry above (using labels to connect it to the original block diagram) Label all your signals including your new control bits Describe your plan below

11 University of Florida EEL 3701 Spring 2010 Dr Eric M Schwartz Page 11/11 Exam 2 (6%) 1 b) Use the table below to OR $ and 6 and then to complement the result Store the result min in B Describe what is accomplished in each step lso do this for parts c and d # MS MSB MSC Input Cin Reg RegB Output Cout Reg+ RegB+ Output+ Cout ( %) c) Use the table below to DD $ and 7, with no carry Store your solution in register B 3 min and show the carry output, eg, B = $ plus 7 with Cout Your adder should be ready to add two more -bit numbers using the possible carryout from this addition You can assume that Reg and RegB already have been loaded with $ and 7, respectively # MS MSB MSC Input Cin Reg RegB Output Cout Reg+ RegB+ Output+ Cout ( %) d) dd the two 8-bit numbers $2 and $37 ssume that part b has already run to add $ and 7 with appropriate carryout) ssume that Reg and RegB have already been loaded 3 min with 2 and 3, respectively Put the high nibble of the solution in B and show the carry output, ie, B = previous Cout with carryout Your adder should be ready to add two more -bit numbers using the possible carryout from this addition # MS MSB MSC Input Cin Reg RegB Output Cout Reg+ RegB+ Output+ Cout