ECE 3401 Lecture 12. Sequential Circuits (II)

Transcription

1 EE 34 Lecture 2 Sequential ircuits (II) Overview of Sequential ircuits Storage Elements Sequential circuits Storage elements: Latches & Flip-flops Registers and counters ircuit and System Timing Sequential circuit analysis and description: State tables & State diagrams

2 ounters ounter: a special type of register that incorporates an incrementer or decrementer, which allows it to count upward or downward. We shall examine VHL code for the following counters: Up counter own counter VHL for Up-ounter Library ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_unsigned.all; ENTITY upcount IS GENERI ( N : INTEGER := 4 ); PORT ( lock, Resetn, Enable : IN ST_LOGI; Q: BUFFER ST_LOGI_VETOR (N- OWNTO )); EN upcount; RHITETURE cnt OF upcount IS SIGNL count : ST_LOGI_VETOR (N- OWNTO ); BEGIN PROESS (Resetn, lock) BEGIN IF Resetn = '' THEN count <= ( OTHERS => ); ELSIF (lock'event N lock = '') THEN IF Enable = '' THEN count <= count +; ELSE count <= count; EN IF; EN IF; EN PROESS; Q <= count; EN cnt; 2

3 Timing iagram for Up-ounter Synchronous ounters Internal Logic Incrementer: Q+ or Q+ ontraction of a ripple carry adder with one operant fixed at X Symbol for Synchronous ounter TR 4 Incrementer 2 EN Q Q 3 Q 2 Q 3 O Symbol 3

4 Synchronous ounters (ontd.) ontraction of carry-lookahead adder Reduce path delays alled parallel gating Lookahead can be used on Os and ENs to prevent long paths in large counters EN Q Q Q 2 2 Q 3 3 O Logic iagram-parallel Gating ounter with Parallel Load Load ount ction Load Hold Stored Value ount Up Stored Value X Load ount Q dd path for input data enabled for Load = Load TR4 Q dd logic to: When Load = disable count logic (feedback from outputs) When Load = and ount = enable count logic ount 2 3 Q Q Q 2 Q 3 O 2 Q 2 3 Q 3 lock arry Output O 4

5 B ounter architecture Behavioral of bcd_counter is signal regcnt : std_logic_vector(3 downto ); begin count: process(reset,clk) is begin if ( reset='' ) then regcnt <= ""; elsif ( clk'event and clk='') then regcnt <= regcnt+; if (regcnt = "") then regcnt <= ""; end if; end if; end process; end Behavioral; Overview of Sequential ircuits Storage Elements Sequential circuits Storage elements: Latches & Flip-flops Registers and counters ircuit and System Timing Sequential circuit analysis and description: State tables & State diagrams 5

6 Flip-Flop Timing Parameters t w - clock pulse width t s - setup time: Equal to a time interval that is generally much less than the width of the triggering pulse t h - hold time - Often equal to zero t px - propagation delay Same parameters as for gates except Measured from clock edge that triggers the output change to the stabilization of the output to a new value t wh t wh,min t wl t wl,min Q t s t h t p-,min t p-,max Edge-triggered (negative edge) Triggered ircuit and System Level Timing onsider a system comprised of ranks of flipflops connected by logic If the clock period is too short, some data changes will not propagate through the circuit to next flip-flop inputs before the setup time interval begins LOK Q Q' Q Q' Q Q' Q Q' Q Q' Q Q' Q Q' Q Q' Q Q' Q Q' LOK t p t pd,ff t pd,omb t slack t s 6

7 ircuit and System Level Timing (ontd.) Timing components along a path from flip-flop to flipflop t p t pd,ff t pd,omb t slack t s Edge-triggered (negative edge) Timing Equations t p = t slack + (t pd,ff + t pd,omb + t s ) t p max (t pd,ff + t pd,omb + t s ) for all paths from flip-flop output to flip-flop input alculation of llowable t pd,omb ompute the allowable t pd,omb for a circuit using edge-triggered flip-flops Parameters t pd,ff (max) =. ns lock frequency = 25 MHz, t p = /clock frequency = 4. ns t s (max) =.3 ns for edge-triggered flip-flops for a gate, average t pd =.3 ns alculations: Edge-triggered: t pd,omb +.3 =>t pd,omb 2.7 ns, approximately 9 gates allowed on a path 7

8 Overview of Sequential ircuits Storage Elements Sequential circuits Storage elements: Latches & Flip-flops Registers and counters ircuit and System Timing Sequential circuit analysis and description: State tables & State diagrams Example Input: x(t) Output: State: y(t) ((t), B(t)) x Next State Q Q Output Function? y(t) = x(t)(b(t) + (t)) Next State Function? (t+) = (t)x(t) + B(t)x(t) B(t+) = (t)x(t) P Output Q Q' B y 8

9 Example (ontd.) Where in time are inputs, outputs and states defined? y(t) = x(t)(b(t) + (t)) (t+) = (t)x(t) + B(t)x(t) B(t+) = (t)x(t) State Table haracteristics The state table can be filled in using the next state and output equations: (t+) = (t)x(t) + B(t)x(t), B(t+) = (t)x(t) y(t) = x (t)(b(t) + (t)) Present State Input Next State Output (t) B(t) x(t) (t+) B(t+) y(t) 9

10 State iagram Present State Input Next State Output (t) B(t) x(t) (t+) B(t+) y(t) / / S S / / S 2 / / / S 3 esign Procedure for Sequential ircuits Formulation: Obtain a state diagram or state table State ssignment: ssign binary codes to the states Flip-Flop Input Equation etermination: Select flip-flop types, derive flip-flop input equations from next state entries in the table Output Equation etermination: erive output equations from output entries in the table Optimization - Optimize the equations Technology Mapping - Find circuit from equations and map to flip-flops and gate technology Verification - Verify correctness of final design

11 Formulation: Finding a State iagram State: an abstraction of the history of past-applied inputs to the circuit (including power-up or system reset) synchronous reset normally resets to the initial state In specifying a circuit, states remember meaningful properties of past input sequences that are essential to predicting future output values, e.g.: State represents the fact that a input has occurred among the past inputs. State B represents the fact that a followed by a have occurred as the most recent past two inputs. Example: Sequence Recognizer Procedure sequence recognizer: produces an output value whenever a prescribed pattern of inputs occur in sequence Steps: Begin in an initial state (typically reset state), when NONE of the initial portion of the sequence has occurred dd states that recognize each successive symbol occurring the final state represents the input sequence occurrence. dd state transition arcs which specify what happens when a symbol not in the proper sequence has occurred. dd other arcs on non-sequence inputs which transition to states. The last step is required because the circuit must recognize the input sequence regardless of where it occurs within the overall sequence applied since reset..

12 Example: Recognize efine states for the sequence to be recognized Starting in the initial state (""): / / / B Finally, output on the arc from means the sequence has been recognized, To what state should the arc from state go? Remember:? The final in the recognized sequence is a sub-sequence of. It follows a which is not a sub-sequence of. Thus it should represent the same state reached from the initial state after a first is observed. / / B / Example: Recognize (ontd.) The other arcs are added to each state for inputs not yet listed. Which arcs are missing? State transition arcs must represent the fact that an input subsequence has occurred. Note that the arc from state back to implies that State means two or more 's have occurred. / / / B Present Next State / State x= x= Output x= x= B B B 2

13 Example: Moore Model For Moore Model, outputs are associated with states. rcs now show only state transitions dd a new state E to produce the output State E produces the same behavior in the future as state B, but it gives a different output at the present time. Thus these states do represent a different abstraction of the input history. The Moore model for a sequence recognizer usually has more states than the Mealy model. / / B / / / B/ / / E/ Example: Moore Model (ontd.) / B/ / / E/ Present State Next State x= x= B B E E Output y 3

14 VHL Example: Sequential Recognizer VHL for the sequential recognizer follows library ieee; use ieee.std_logic_64.all; entity seq_rec is port (LK, RESET, X: in std_logic; Z: out std_logic); end seq_rec; architecture process_3 of seq_rec is type state_type is (, B,, ); signal state, next_state: state_type; begin VHL Example (ontd.) --process : implements positive edge-triggered flipflop with asynchronous reset state_register: process (LK, RESET) begin if(reset = '') then / state <= ; elsif (LK'event and LK = '') then state <= next_state; end if; end process; / B / / --process 2: implement output as function of input X and state output_function: process (X, state) begin case state is when => Z <= ''; when B => Z <= ''; when => Z <= ''; when => if X = '' then Z <= '; else Z <= '; end if; end case; end process; 4

15 VHL Example: (Process 3) --process 3: next state-function implemented as a function of input X and state next_state_function: process (X, state) begin case state is when => if X = '' then next_state <= B; else next_state <= ; end if; when B => if X = '' then next_state <= ; else next_state <= ; / B / end if; when => if X = '' then next_state <= ; else next_state <= ; end if; when => if X = '' then next_state <= B; else next_state <= ; end if; end case; end process; end architecture; / / 5