Fundamentals of Computer Systems
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1 Fundamentals of omputer Systems Sequential Logic Martha A. Kim olumbia University Spring /1
2 2/1
3 Bistable Elements Equivalent circuits; right is more traditional. Two stable states: /1
4 S Latch S S S /1
5 S Latch 0 1 S S 1 0 S Set ( = 1) /1
6 S Latch 1 0 S S 0 1 S Set ( = 1) eset ( = 0) 1 1 4/1
7 S Latch 0 (0 + )= S S 0 (0 + )= S 0 0 Hold previous value Set ( = 1) eset ( = 0) 1 1 4/1
8 S Latch 1 0 S S 1 0 S 0 0 Hold previous value Set ( = 1) eset ( = 0) Bad. o not use. 4/1
9 S Latch S S S Bad. o not use eset ( = 0) Set ( = 1) 1 1 Hold previous value 5/1
10 Latch 0 X /1
11 A hallenge: Build a traffic light controller Want the lights to cycle green-yellow-red. Y G oes this work? 7/1
12 8/1
13 8/1
14 8/1
15 8/1
16 8/1
17 8/1
18 8/1
19 9/1
20 9/1
21 9/1
22 9/1
23 9/1
24 Positive-Edge-Triggered Flip-Flop M Master S Slave M 0 S transparent opaque 10 / 1
25 Positive-Edge-Triggered Flip-Flop M Master S Slave M 0 S transparent opaque 10 / 1
26 Positive-Edge-Triggered Flip-Flop M Master S Slave M 0 S transparent opaque opaque transparent 10 / 1
27 Positive-Edge-Triggered Flip-Flop M Master S Slave M 0 S transparent opaque opaque transparent 10 / 1
28 Positive-Edge-Triggered Flip-Flop M Master S Slave M transparent opaque transparent 0 S opaque transparent opaque 10 / 1
29 Positive-Edge-Triggered Flip-Flop M Master S Slave M transparent opaque transparent opaque 0 S opaque transparent opaque transparent 10 / 1
30 The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
31 The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
32 The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
33 The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
34 The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
35 The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
36 The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
37 The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
38 The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
39 The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
40 The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
41 Flip-Flop with Enable 0 1 E E " 0 X " " X X 1 X X E What s wrong with this solution? 13 / 1
42 Asynchronous Preset/lear PE L PE L 14 / 1
43 The Traffic Light ontroller w/ Async. eset ESET PE L PE L Y PE L G 15 / 1
44 The Synchronous igital Logic Paradigm Gates and flip-flops only INPUTS OUTPUTS Each flip-flop driven by the same clock STATE L Every cyclic path contains at least one flip-flop LOK NEXT STATE 16 / 1
45 ool Sequential ircuits: Shift egisters A A X X X X 1 0 X X X X X X / 1
46 Universal Shift egister L S 1 S0 S 1 S L S 1 S 0 Operation 0 0 Shift right 0 1 Load 1 0 Hold 1 1 Shift left 18 / 1
47 ool Sequential ircuits: ounters ycle through sequences of numbers, e.g., / 1
48 Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change t su 20 / 1
49 Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h 20 / 1
50 Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h Minimum Propagation elay: Time from clock edge to when might start changing t p(min) 20 / 1
51 Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h Minimum Propagation elay: Time from clock edge to when might start changing t p(min) t p(max) Maximum Propagation elay: Time from clock edge to when guaranteed stable 20 / 1
52 Timing in Synchronous ircuits L t c t c : lock period. E.g., 10 ns for a 100 MHz clock 21 / 1
53 Timing in Synchronous ircuits L Sufficient Hold Time? t p(min,ff) t p(min,l) Hold time constraint: how soon after the clock edge is liable to start changing? Min. FF delay + min. logic delay 21 / 1
54 Timing in Synchronous ircuits L t p(max,ff) Sufficient Setup Time? t p(max,l) Setup time constraint: when before the clock edge is guaranteed to have stabilized? Max. FF delay + max. logic delay 21 / 1
55 lock Skew: What eally Happens L 1 2 Sufficient Hold Time? 1 2 t skew t p(min,ff) t p(min,l) 2 arrives late, creating potential hold time violation 22 / 1
56 lock Skew: What eally Happens L 1 2 Sufficient Setup Time? 1 2 t skew t p(max,ff) t p(max,l) 2 arrives early, creating potential setup time violation 22 / 1
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