Eng. Mohammed Samara. Fall The Islamic University of Gaza. Faculty of Engineering. Computer Engineering Department

Transcription

1 Fall 2011 The Islamic University of Gaza Faculty of Engineering Computer Engineering Department ECOM Digital Systems Design Lab Lab 7: Prepared By: Eng. Mohammed Samara

2 Introduction: A counter is a sequential component that increments or decrements a stored value. Counters can be used in many digital circuit applications. For example, if an application requires a given operation to be performed on a number of items of data or to be repeated a number of times, a counter can be used to keep track of how many items have been processed or how many times the operation has been performed. Counters are also used as timers, by counting the number of intervals of a fixed duration that have passed. A simple form of counter is composed of an edge-triggered register and an incrementer, as shown in the Figure 1. The value stored in the register is interpreted as an unsigned binary integer. The counter increments the stored value on every clock edge. When the stored count value reaches its maximum value (2 n - 1, for an n-bit counter), the incrementer yields a result of all zeros, with the carry out being ignored. This result value is stored on the next clock edge. Thus, the counter rolls over to zeros after reaching its maximum value. Mathematically speaking, the counter increments modulo 2 n. Figure 1: Simple Counter VHDL Modeling for Counters: We can use a process that represents the counter. It is similar in form to a process for an edge-triggered register. The difference is that the value assigned to the count value output on a rising clock edge is the incremented count value. count_value <= count_value + 1; The assignment to count value represents the update of the value stored in the register, and the addition of 1 represents the incrementer. Note: Anything other than the counter must be modeled outside the counter process. 1 Counters

3 Free-Running Counters: The free-running counters are simple counters with no control over the count value which will be incremented till it reaches the maximum value. Example 1: Design a circuit that counts 16 clock cycles and produces a control signal (ctrl) that is 1 during every eighth and twelfth cycle. We need a 4-bit counter, since 16 = 2 4. The counter counts from 0 to 15 and then rolls back to 0. During the eighth cycle, the counter value is 7 (0111) 2, and during the twelfth cycle, the counter value is 11 (1011) 2. We can generate the control signal by decoding the two required counter values and forming the logical OR of the decoded signals. As shown in Figure 2. Figure 2: Free-Running Counter VHDL Modeling: library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; entity decoded_counter is port ( clk : in std_logic; ctrl : out std_logic ); end entity decoded_counter; 2 Counters

4 architecture rtl of decoded_counter is signal count_value : unsigned(3 downto 0); begin counter : process (clk) is begin if rising_edge(clk) then count_value <= count_value + 1; end if; end process counter; ctrl <= '1' when count_value = "0111" or count_value = "1011" else '0'; end architecture rtl; Notes: We note the ctrl assignment is done outside the counter process. We used the standard Numerical Package (ieee.numeric_std.all) for the unsigned integers. Non-Free-Running Counter: By adding some modifications to the free-running counters, we can have control over the count value. These modifications can be adding Reset Signals (to reset the count value), Count-Enable Signals (to control the counter state ON/OFF), or Terminal-Count Signals (to notify the systems when the counter reaches it maximum/zero value). 3 Counters

5 Example 2: Develop a VHDL model for an interval timer (down counter) that has clock, load and data input ports and a terminal-count output port. The data must be loaded to the counter when the load is enabled and the counter should count down from the loaded data to zero. When the counter reaches zero, it reloads the previously loaded value. The timer must be able to count intervals of up to 1000 clock cycles. We need 10-bits down counter, since it is the minimum number of bits needed to represent 1000 counts. library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; entity interval_timer is port ( clk, load : in std_logic; data : in unsigned(9 downto 0); tc : out std_logic ); end entity interval_timer; architecture rtl of interval_timer is signal load_value, count_value : unsigned(9 downto 0); begin count : process (clk) is begin if rising_edge(clk) then if load = '1' then load_value <= data; count_value <= data; elsif count_value = '0' then count_value <= load_value; 4 Counters

6 else count_value <= count_value 1; end if; end if; end process count; tc <= '1' when count_value = 0 else '0'; end architecture rtl; Ripple Counters: As shown in Figure 3, it is somewhat different in structure from the synchronous counters we have previously discussed. Like those counters, it has a collection of flip-flops for storing the count value. However, unlike them, the clock signal is not connected in common to all of the flip-flop clock inputs. Rather, the clock input just triggers the flip-flop for the least significant bit, causing it to toggle between 0 and 1 on each rising clock edge. When the Q output changes to 0, the Q output changes to 1, triggering the next flip-flop to toggle between 0 and 1. This flip-flop behaves similarly, causing the third flip-flop to toggle when it (the second flip-flop) changes from 1 to 0. Figure 3: N-bit Ripple Counter 5 Counters

7 In general, we can think of the flip-flops for bits 0 to i as forming an i-bit counter. The most significant bit of this counter changes from 1 to 0 when it overflows. When that happens, the next flip-flop, for bit i, toggles between 0 and 1. The timing diagram of the ripple counter is shown in Figure 4. Figure 4: 3-bit Ripple Counter Timing Diagram VHDL Modeling: 1. We need one process for each flip-flop (10-bit ripple counter needs 10 processes). 2. The sensitivity list for the first process (bit 0) contains the clock. 3. The sensitivity list for each of the other processes contains the inverted output of the previous flip-flop (Q ). Exercises: 1. Develop a VHDL model of the modulo 12 counter. 2. Develop a VHDL model for a free-running counter that counts 32 clock cycles and produces a control signal that is 1 during every 4th, 20th and 24th cycle. 6 Counters

8 3. Develop a VHDL model of a 12-bit up counter with synchronous count-enable, reset and load-enable inputs, and a terminal-count output. Homework: Develop a VHDL model of a 3-bit Ripple Counter. 7 Counters