A GENERALIZED TWO-INPUT FLIP-FLOP AND ITS REALIZATION'

Transcription

1 R 602 Philips Res. Repts 2, , 966 A GENERALIZED TWO-INPUT FLIP-FLOP AND ITS REALIZATION' Abstract by N. C. de TROYE.,This paper deals with a classificatin f flip-flp circuits having tw input cnditins. It is shwn that by permutatin and/r negatin f the input cnditins 20 essentially different flip-flp circuits having the. utput states "0", ""," Q."", "Q"" and" " and 55 essentially different ' flip-flp circuits having the states "0", "", "(2"" and "Q"" can be fund..an example f a circuit which can generate the 55 last-mentined types has been given. It is built up frm NAND circuits.. Intrduetin A flip-flp is ~ circuit, perating n tw-valued vltage levels, having m input iines [~,..., Im- and ne utput line Q (fig. I).. The flip-flp has à separate clck-pulse line CP and is s designed that all changes f the input and utput lines take place between the clck pulses. The time that the clck pulse is present will he called the bit time. fr cp r " ( -----rlrne Fig.. A flip-flp circuit with In input lines 0,, Im_ h a clck-pulse line CP and ne utput line Q. The clck pulse has an idealized shape. The time that the clck pulse is present will be called the bit time. '., Accrding t Mntgmery 'Phister ) ne can characterize a flip-flp as fllws: () the state f a flip-flp is defined by the state (i.e. the vltage level) f its utput line; (2) the state f a flip-flp is defined nly during the bit time; (3) the state f a flip-flp at a particular bit timeis a functin f (a) the state f the flip-flp and f ifs input lines during the previus bit time and ' (b) the lgical prperties f the flip-flp, which express hwthe state f the flip-flp is ;elated t its input lines.

2 A GENERALIZED TWO-INPUT FLIP-FLOP' AND ITS REALIZATION.-._ '--'._----'---'------' ' 39 This is mre precisely expressed ill table I. On the left there are the 2m+ pssible- states fthe inputlines In,..., Im_n and the utput line Qn, in which the superscript dentes the bit time and the subscript the n~mber f the input line. On the right there are indicated the resu'ting states f the flip-flp at bit time n +, i.e. Qn+. TAB...Èr 0. 0 J.. I' In the state Sj ne can expect 3 pssibilities: () the 'flip-flp will be set in "zer" at bit time n' + regardless f its state at time n, i.e. Qn+ = 0; \ (2) the flip-flp will be set in "ne" at bit time n + regardless f its state at time n, i.e. Qn+ = '; (3) the flip-flp will have an indeterminate state, i.e. Qn+ =? The infrmatin in the table can be expressed bya Bean equatin Qn+': " «r.i«n) - JO,0,..., m-i, where f represents a Bean functin f Qn, In,..., Im_n. If there are restrictins n the allwable cmbinatins f the input lines ne expresses this by anther Bean functin.. f (Qn, In,..., Im_n) = O. (2). Accrding t Mntgmery Phister 2), () will be called the characteristic equatin f the flip-flp. Frm the characteristic equatin, i.e. (), it fllws that Qn+ = g (In,..., Im_n)Qn + gl (In,..., 'Im_n)Qn (3).and frm eq. (2) it fllws that ()

3 392 N. C. de TROYE g3(in,..., Im.:..In) are Blean functins.f the input variables nly. Equatin (4) shws that the indeterminate states are depending n, amng thers, the state Qn r Qn r bth. Because in the scpe f this paper flip-flps having an indeterminate state are nt imprtant, ne can prpse that the indeterminate state is regardless f Qn r Qn, s (2) can be written as 2 (In,..., Im_n) = O. This means that table I can be reduced t table IT. (5) TABLE IT I m _ I n I m _ 2 n In the state Sj ne can expect nw ~ pssibilities: () Qn+I';' 0; (2) Qn.+ = ;, (3) Qn+ = Qn, i.e. the flip-flp will stay in its state; (4) Qn+ = Qn, i.e. the flip-flp will change its state; (5) Qn+I =?, i.e. the flip-flp has an indeterminate state. Ntice that the subscriptj f Sj crrespnds t the numerical valuej f the binary representatin f the input variables Im-I n,, In. Due t permutatins and/r negatins f the input variables the numerical value f the binary representatin will change in general, but as a cnsequence the subscriptj f Sj will change t. If ne defines a state sequence as the set f rdered states ne btains by reading the clumn Qn+ in the abve-mentined table upwards frm belw, it is clear that the state sequence ne riginally starts with (S2m_l'..., s) after permutatins and/r negatins f the input variables, als changes. This newly btained state sequence will be dented by a2m_l,..., a. By mapping the states 0,, Qn, Qn and? nt the integers 0,, 2, 3 and 4, respectively, the.state sequence a2m_l>'..., a frms a number in which the

4 A GENERALIZED TWO-INPUT FLIP-FLOP AND ITS REALIZATION 393 digits al can have the value 0,, 2, 3 r 4. One can rder all state sequences in this way, their rder being., 2m-l K= ~ a 5 =0 The list f rders K = 0()5 2m - therefre uniquely represents all state sequences. It is imprtant t intrduce the cncept f equivalence classes, i.e. the set f all state sequences a2m_l,., a, which can be derived frm each ther by permutatins and/r negatins f the input variables. In rder t determine the number f equivalence classes ne culd use the fllwing prcedure: take frm the list f rders K = O. In this case aj = 0 fr 0 ~j ~ 2 m -. Permutatins and/r negatins f the input variables have n influence n aj' s the state sequence f K = 0 frms the whle equivalence class O. This is marked in the list by an asterisk. The next state sequence is that with K =.In this case a = and aj = 0 fr ~j ~ 2 m -. The state sequence with K = is marked in the list. Nw ne takes all permutatins and/r negatins f the variables In,, Im_ln and in this way btains all state sequences f equivalenee class. These are all remved frm the list f rders. The next state sequence t be marked is that with the smallest K that is nt remved frm the list and s n. 2. The tw-input flip-flp In the case m = 2 ne has t deal with 2 input lines In and Iln a state sequence S3S2SlS0 as shwn in table. and thus with TABLE ill Iln In Qn+l 0 0 S 0 St 0 S2 S3 The list f rders K = 0() = 0()624 is given in table IV *). The first clumn gives the state sequences rdered in the way described in the intr- *) As Mr H. J. Hek pinted ut t me, frm table lne can derive in fact 3 23 = 656 pssible state sequences. This number reduces hwever. t 625 by using eq. (5).

5 394. N. C. de TROYE TABLE IV a3a2alao Eq.CI. S a Eq.CI. S , ' & ' , : ' 8 -, , ' Hi , ' : : ; " ' ,, 45. > 0203, ,

6 , A GENERALIZED TWO-INPUT FLIP-FLOP AND ITS REALIZATION 395 TABLE IV (cntinued) a3a2aao ' Eq.CI. S a3a2aao Eq.CI. S " ' ' , , ' '76 ' l : ' , , t Q , , , , ' , 29, , , ,, ",

7 396 N. C. de TROYE TABLE IV (cntinued) a3a2aao Eq.CI. S a3a2aao Eq.CI. S I

8 , A GENERALIZED TWO,INPUT ELIP-I;LOP AND ITS REALIZATION 39.7 _, a3a2aao TABLE IV (cntinued) Eq.CI. S 'a3a2aao Eq.Cl. S , , - I " , _ , , 'i \ 244 ; _ ,70.' ' , , ' ' I , '

9 398 N. C. de TROYE TABLE IV (cntinued) a3a2alao Eq.CI. S a3a2alao Eq.CI. S : :

10 A GENERALIZED TWO-INPUT FLIP-FLOP AND ITS REALIZATION 399 TABLE IV (cntinued) a3a2alao Eq.CI. S a3a2alao Eq.CI. S , TABLE V 0 d g gl 2 g gl 2 Ó' Ó' ~ ~ lll lll + lll lll lll lll lll + lll 3 0 lll 28 lll lll = 0 29 lll lll + lll lll = lll lll lll = 0 6 lll lll = 0 70h 32 0 lll llt = 0 8 lll lll lll = 0 33 lll 0 lll = lll lll = 0 0 lll lll 35 lll + lll 0 llt 0 lll = lh lll lll = 0 38 lh + lll lll = 0 39 lll + lll 0 lll = 0 5 lh + lh lll + lll 40 lll lll lll + lll 42 0 lh 8 lll + lll lll 9 lll + lll lll + lll lll= 0 44 lll lll llt = 0 20 lll + lll lll. 45 lh 0 lll = llt = lh llt = 0 23 lh + lll 0 48 lll u. lll = 0 24 lll + lll lll lh =0 49 lll 0 ~,= 0

11 . 400 N. C. de TROYE TABLEV (cntinued) ti g gl ' /2 ti t:ï' g gl 2 ~ ~ 50 0 lll + lll 75 lll + lh 5 lll lh 52 lll lll + lll lll + lll lll lll = lll + lll lll = lll lll = h 0 lll = 0 8 i, t; + Ir 57 lll lll lll = 0 82 i, 0 lll = lll = i; lll + lll lll = lll = lll lll = Tll+0=0 85 lll':' lh lll = 0 6 lll lll JOl +0=0 86 h. lll =0 62 lll 0 0h+ll=0 87 lll + lll I 63 0 lll \ lll +0=0 88 lll + lll = 0 89 lh 65 I 90 lll 0 + lll = h 9 lll + lll 0+ lll lll + lll i, lll = lll = 0 93 lll 0+ lll = lll i, =0 70 l lll + lll 0i+ lll lll +0= i, lll = 0 96 lll + lll lll lll +0= lll lll + lll lll +0= lll = 0 98 lll lll 0+ = 0 74 = t:ï' Eq.CI. g gl ' lll lll =0 02 h 03 i, lll lll = 0 04 i, 0 = 0 05 lll + ~ lll lll lh lll + lll lll = lll lll = 0 09 lll 0 0,= 0 0 lll lll = 0 lll + lll Ö lll + lll =s 0 2 lh lll lll + llt ='0.. 3 lh 0 + = i 5, 0 07-' 0~'70',, II6 0 =0 ". II7 l' " 0 lll + lll lll +- 0 = 0.,, 8 0 lll 0 + = O J" II9 0 0 \ Jl + lll + lh + lll = ,.'

12 A GENERALIZED TWO-INPUT FLIP-FLOP.AND ITS REALIZATION 40 ductin. The secnd clumn gives the equivalence class (Bq. Cl.) t which the state sequence belngs. The third clumn gives the ttal number S f the state sequences belnging t a certain equivalence class, Only the fust representative f the equivalence class is labeled with an S. They are in fact the asterisks described in the intrductin. In table V the characteristic equatin f the fust representative f an equivalence class has been given. Fr this purpse () is written as ' in which g and gl are Blean functins f 0",.., InI-" In clumn j', the restrictins n the allwable cmbinatins f the- input variables are given. They are nt used t minimize the expressins g and g l' As ne can see, there are 20 equivalence classes fr the tw-input-line flipflps having the states 0,, Q", Q" and? Tw-input-line flip-flps nt having the state? can be classified int 55 equivalence classes. They belng t thse equivalence classes which have n restrictins given in the clumnj', f table V. Frm nw n attentin is paid nly t the last 55 types. 3. Realizatin f flip-flp circuits with NAND lgic In fig. 2 a set-reset flip-flp built up frm NAND lgic 3) *) has been given. It is suppsed that a number f set lines (J, ', (Jk and a number f reset lines e,..., el are available. T set r t reset the flip-flp it is necessary that either all set lines (Jp r all reset lines eq are "ne". In rder t describe the flip-flp by means f a table ne can intrduce ne set line Sn and ne reset line Rn defined as (6) (7) and (8) Fig. 2. A set-reset flip-fîp built with NAND circuits. If all the inputs (J; ':, (Jk are "ne", the flip-flp will be set t "ne"; if all the inputs (J,, (JI are "ne", the flip-flp will be set t "zer"; if ne r mre f the inputs (J, ', (Jk and Il,, III are "zer", the flipflp will stay in its state; and finally if all inputs (J,, (Jk and Il,, III are "ne", the flip-flp will be defined as indeterminate. *) The symbl fr the NAND lgic used in this paper is taken frm ref. 3.

13 402 N. C. de TROYE If the clck pulse CP is "zer" the utput vltages f line A and line Bare "ne" whatever the states f Rn and S", and the flip-flp will stay in a stable state. If the clck pulse is "ne" the flip-flp will be set t "ne" r reset t "zer" r will stay in the same state depending n the states f Sn and Rn as given in table VI. TABLE VI Rn sn Qn+l 0 0 Qn 0 0 0? Ntice, hwever, that the "state" given in the table is nt exactly the definitin f "state" given in the intrductin, fr the flip-flp is set r reset during the time that the clck pulse is "ne", i.e. during the bit time. The characteristic equatin f this set-reset flip-flp is with the restrietin that Fr (9) ne may write by using (0) (9) (0) s with the restrietin Qn+l = RnsnQn + RnQn + RnsnQn, () (2) The flip-flp given in fig. 3 is a set-reset flip-flp which meets the definitins LMasterfliP-fIOP ] L Slavt' flip-flp j Fig. 3. A set-reset flip-flp which meets the definitin f "state" and the "characteristic equatin". It is built up frm a master and a slave flip-flp. During the bit time the master flip-flp is set t its prper state and the slave flip-flp is blcked. If the clck pulse is absent the master flip-flp is blcked and its infrmatin is transferred t the slave flip-flp.

14 A GENERALIZED TWO-INPUT FLIP-FLOP AND ITS REALIZATION 403 f "state" and is characterized by eq. (). It is built with tw set-reset flip-flps 'as given in fig. 2. The first flip-flp will be called the master flip-flp, the secnd ne the slave flip-flp. The master flip-flp is set r reset by the clck pulse CP, the slave flip-flp by the inverse clck pulse CP. If CP =, the master flipflp will be set t a state as given by table VI. During that time, CP = 0 and the vltages n the lines C and D are "ne", which means that the slave flipflp stays in its state. If CP = 0, the master flip-flp will stay in its state, but nw CP = and thus the infrmatin f the master flip-flp will be transferred t the slave flip-flp. Althugh CP can be frmed frm CP by adding ne extra NAND circuit, ne can see that it is nt necessary t d this. By using the fact that transfer f infrmatin frm the master flip-flp t the slave flip-flp is allwed if CP = 0 r if Rnsncp = (i.e. during the clck pulse the master flip-flp des nt change because Rn = S" = 0), ne derives the fllwing relatin: TI = CP + Rnsncp = CP + Rns n = (CP + sn) (CP + Rn) = = CPsnCPRn, in which TI dentes transfer f infrmatin is allwed. Frm fig. 3 it fllws that A=CPS and B= CPR, thus with (3) TI = CP + Rnsncp = AB, (4) s instead f using CP ne can use the utputs A and B. Figure 4 nw gives the simplified set-reset flip-flp. Attentin will be paid nw t ther types f flip-flps. If ne takes I and (j =Jn, (jl = (2n, e = K", el = Qn, (3) CP >-~--~~~--~ ~----~ >~--.Q R---.., Fig. 4. A set-reset flip-flp which meets the definitin f "state" and the "characteristic equatin". During the bit time the slave flip-flp is blcked by using the utput lines A and B.

15 404 N. C. de TROYE it fllws frm (7) and (8) that and. '(IS) One sees that in this case Rn = S" = 'I never can ccur due t the fact that 'Qn and Qn are used in S" and Rn, respectively. Substitutin f (5) a~cï(i6) in the characteristic equatin () gives' I '.. s.., (7)... This is the characteristic equatin f the well-knwn JK flip-flp: The flip-flp itself is shwn in fig. 5. (6) Fig. 5. A JK flip-flp. By intercnnecting J and KaT flip-flp arises and by intercnnecting A and K and discnnecting the input Qa D flip-flp aris~s. The states S, S' S2 and S3 fthe JK:flip-flp are Qn,O, and Qn, respectively. The state sequence therefre is Qn 0 Qn, and its rder is 203. Reference t table IV shws that the flip-flp is a member f equivalence class 4. Permutatins and/r negatins f the variables J and K gives all ther members f the equivalence class 4. The states f the JK :flip-flp are given in table VII. TABLE VII i«. Kn Qn+ 0 0 Qn Qn

16 ,\ A GENERALIZED TWO-INPUT FLIP-FLOP AND ITS REALIZATION 405,, One can see that by making J" = K" a flip-flp arises with a state table as given in fable VTII, i.e. the state table f the T flip-flp 4). By making J" = j(n a flip-flp arises with a state table as given in table IX, i.e. the state table f the D flip-flp 5). TABLE VTII TABLE IX The T flip-flp can be derived frm the JK flip-flp by intercnnecting the J and K input lines. The D flip-flp can be derived by' putting an additinal NAND between the J and K input lines r by intercnnecting (see fig. 5) the utput line A with the input line K and discnnecting the input line Q. The Tflip-flp belngs t equivalence class 02, the D ûip-fip t equivalence class 5. A new type f flip-flp, the D(elay) T(rigger) flip-flp with a state table as given in table X, TABLE X Dn Tn Qn+l 0 0 Qn 0 Qn 0 0 is a cmbinatin f the D and T flip-flp. Frm table X it fllws that if D" = 0, the flip-flp acts as à Tfip~flp, but if D" = it acts' asa D flip-flp.

17 406 N. C. de TROYE Fig. 6. A DT flip-flp. Here use is made f 2 NAND circuits A and B t reset the flip-flp. The DT flip-flp belngs t equivalence class 27, thus it cannt be derived frm the JK flip-flp by permutatins and/r negatins f J" and K". The realizatin f the DT flip-flp is shwn in fig. 6. One sees that the slave flip-flp can be reset by several cmbinatins f the input variables D and T because tw NAND circuits A and B are cnnected t that NAND circuit f the flip-flp n which it can be reset. Frm fig. 6 it fllws that (8) and Rn. IJnTnQn + nnyn. (9) As ne can see frm (8) and (9) the cnditin R'S" = 0 is fulfilled. Substitutin f (8) and (9) int () gives the characteristic equatin f the DTflipflp: 4. A generalized tw-input flip-flp Qn+ = TnQn + (DnTn + IJnyn)Qn. In sec. 3 fur flip-flp circuits belnging t different equivalence classes have been described. It is f curse pssible t design 55 separate flip-flp circuits each representing ne equivalence class. In fig. 7 a six-input-line flip-flp has been given which can generate all 55 different flip-flp circuits by chsing the prper input lines. The slave flip-flp can be set r reset by several cmbinatins f the input variables X, Y, Z r Xl> Y h Z' respectively. Frm fig. 7 it fllws that (20) s and (2) Rn = Qnxn(xl n + yn + ZIn + Zn) + QnZ O nz l ny I n(x n + y I n+z n + Zn), SO (22)

18 - -- _----- A GE_NERALIZED TWO-INPUT FLIP-FLOP AND ITS REALIZATION 4Q7 TABLEXI Eq.Cl. X YO Z Xl Y Zl utput used remark Q nt imprtant i, Q Q Q nt imprtant i, 0 Q Q 7 7 h 0 i, 0 Q Q i, 0 t, t, Q Q nt imprtant. 6 see I I I I 0 Q I Q 20 see 7 Q 2 see 6 Q 4 22 I 0 I I I 0 Q I Q 25 see 8 Q 26 see 7 Q 27 see 23 Q 5 i. 0 0 Q. Q 6 28 t, 0 0 Q t, Q Q t, Q Q Q Q Q Q Q. 26 ;; Q nt imprtant Q i, 0 0 Q nt imprtant 65 see 0 Q nt 'imprtant 66 see 2 Q 67 see 3 Q nt imprtant 69 see 9 Q 70 see 0 Q 72 see 2 Q nt imprtant 75 see 35 Q 76 see 37 Q 77 see 38 Q 79 see 40 Q 80 see 42 Q.,

19 408 N. C. de TROYE TABLE XI (cntinued) Bq.CI. X Y Z Xl Y I Zl utput used remark 8 see 43 Q 87 see 50 Q nt imprtant 88 see 52, Q 89 see 53 Q nt imprtant Q Q Q Q Q Q nt imprtant X---~ ra -'"""""~--I Z "... Q X, Yt Zt ---H~ L.!:::===::t:::=t:;l Fig. 7. A general tw-input flip-flp. By a prper chice f the input lines X Y Z and Xl> Yl> Z ne can generate the 55 essential different flip-flps having tw inputs. Substitutin f (2) and (22) int () give's the characteristic equatin f. the general tw-input-line flip-flp:. Qn+l = (XnYn + XnZn + XnYnZn)Qn + + (xlnyln + xlnzn + XlnZl~ + XlnYinZinZOn)Qn. (23) Table XI shws hw t cnnect the input lines X YZ and Xl Y l Z with the input variables 0 and t btain a state sequence belnging t a certain. equivalence class.' Permutatins and/r negatins f the input variables give all.ther state sequences belnging t the same equivalence class. It is, hwever, nt necessary t make 55 different input cmbinatins t btain 55 different equivalence classes. Take e.g..the tw state tables as given in tables xn and xm. -

20 A GENERALIZED TWO-INPUT,FLIP-FLOP AND ITS REALIZATION 409 TABLE XII, TABLE XIII I n In Qn+ I n In Qn Qn 0 Qn 0 Qn 0 Qn Qn Qn In table XII a state sequence belnging t equivalence class 43 and in table XIII a state sequence belnging t equivalence class 8 have been given. Inthe case I n = In = 0 the state Qn+ in table XII and table XIII are ppsite. If ne uses the utput Q t represent this state in the equivalence class 43 (i.e. Qn+ = 0) ne can use the utput Q t represent that state in the equivalenee class 8 (i.e. Qn+ = ). In the remaining cases the states SI' S2 and S3 in bth tables are equal, i.e. Qn r Qn. They give infrmatin whether the flipflp will d nthing r will change, respectively. But this means that if Qn+ = = Qn, bth utputs Q and Q will d nthing and if Qn+ = Qn bth utputs Q and Q will change. S the utput Q can be used t represent all states f equivalence class 43 and the utput Q can be used t represent all states f equivalence class 8.. Frm table XI it fllws that 34 different input cmbinatins are necessary t btain the 55 state sequences f different equivalence classes. Amng them there are state sequences representing flip-flps which are frm a technical pint f view nt imprtant. These have states cnsisting f Qn nly r cmbinatins f Qn and 0 r Qn and, s the latter tw flip-flps will at mst change their state nce. Acknwledgement Thanks are due t my clleagues J. R. Brandsma, Dr H. J. Heijn and H. J. Hek fr many valuable discussins. 'Eindhven, June 966 REFERENCES ) Mntgmery Phister, The lgical design f digital cmputers, Jhn WHey and Sns, New Yrk, 963, p, 5..'. 2) Ibid., p. 7. 3) Gerald A. Mal ey and Jhn Ear le, The lgical design f transistr digital cmputers, Prentice Hall, Englewd Cliffs N.J., 963, p. 7. ~) Mntgmery Phister, ref., p. 27. " 5) Ibid...p. 26.