1967 FIRST PRODUCTION MOS CHIPS 1969 LSI ( TRANSISTORS) PMOS, NMOS, CMOS 1969 E-BEAM PRODUCTION, DIGITAL WATCHES, CALCULATORS 1970 CCD

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1 HISTORY OF VLSI 1948 TRANSISTOR INVENTED (SHOCKLEY AT&T) GERMANIUM-GOLD CONTACT 1954 SILICON TRANSISTOR (TEAL TI) HIGHT TEMP TRANSISTOR COMPUTER (CRAY) 1958 FIRST MONOLITHIC CIRCUIT (IC) BJTs (KIRBY - TI & NOYCE - FAIRCHILD) 1960 SSI (< 100 TRANSISTORS) MOSFET - PMOS, METAL GATE (BELL LABS) 1961 TTL (PACIFIC MICROTEL) - 25UM FEATURE SIZE 1962 ECL (MOTOROLA) 1964 OPAMP (WILDAR - FAIRCHILD U709) 1965 PDP-8 < $20, MSI ( TRANSISTORS)

2 1967 FIRST PRODUCTION MOS CHIPS 1969 LSI ( TRANSISTORS) PMOS, NMOS, CMOS 1969 E-BEAM PRODUCTION, DIGITAL WATCHES, CALCULATORS 1970 CCD (BELL LABS), MICROPROCESSOR (HOFT - INTEL) 1971 ION IMPLANTATION 1972 I 2 L (IBM), 16 BIT MICROS 1975 VLSI (10, ,000 TRANSISTORS) SELF-ALIGNED PROCESSES 1975 SPICE DEVELOPED (U CAL. BERKLEY) 1980 s ULSI (> 100,000 TRANSISTORS) ASICS, PLD, TRENCH CAPS, DUAL WELL, BIMOS, HVICS FEATURE SIZE 2UM 1990 s > 1,000,000 TRANSISTORS 64-bit MICROS, MICROMACHINING, FPGA SYNTHESIS, VHDL, FEATURE SIZE 0.5UM

3 STATE OF THE ART DRAMS 64MBIT, 10NS (SDRAM) SRAMS 16MBIT, 16K GaAs - < 1NS ROMS 64MBIT PLDS 100K USABLE GATES EPROMS 64MBIT

4 EEPROMS 64MBIT MICROS 64 BIT > 8M TRANSISTOR CISC > 300 MIPS RISC GATE ARRAYS 1M AVAILABLE GATES STANDARD CELLS UP TO 2M TRANSISTORS

5 FUTURE OF VLSI DENSITY 2X/YEAR > 2X s DECREASING 1990 s SPEED 2X MIPS/YEAR CHIP SIZE > (800 MIL.)**2 WSI - 12 WAFERS

6 BARRIERS COMPLEXITY > 100K TRANSISTORS TESTING INTERCONNECT DEVICE.1 U PHYSICAL 5 IN./ NS SPEED OF LIGHT LATE 1990 S 1 GBIT RAMS > 1000 MIPS PROCESSORS 10M TRANSISTOR ASIC

9 VLSI IN CANADA INDUSTRIAL STANDARD PARTS - SMALL ASIC - GROWING LSI, MOTOROLA, NCR CAPTIVE MARKETING - BIG IN COMMUNICATIONS NTE, MITEL, MICROTEL PACIFIC SASK. SMALL ASIC MARKET - COST, RELIABILITY, SPACE, PERFORMANCE PENETRATION - ALL OR NONE, HIGH NRE

10 UNIVERSITY MITEL <--> CMC <--> UNIVERSITIES (~25) NSERC CMC SERVICES - VLSI MESSAGE NETWORK - TOOLS SUPPORT - RESEARCH SUPPORT - DESIGN STATIONS - TEST STATIONS - SOFTWARE DISTRIBUTIONS - DEVELOPMENT CONTRACTS - DESIGN VERIFICATION - DESIGN SUBMISSION

11 TECHNOLOGIES CMOS1B 5µ 1983 CMOS3 3µ 1986 CMOS4 1.5µ 1989 CMOS4S 1.2µ 1991 CMOS5.8µ 1993 BIMOS.8µ 1993 GaAs 1.2µ 1993 BIPOLAR 3µ 1988 CHIP SIZE (4000µ) 2 PACKAGES 40 PIN DIP -> 100 PIN PGA 3-4 SUBMISSIONS EACH YEAR JAN 88 SUBMISSIONS 21 UNIVERSITIES 87 DIFFERENT CHIPS > 500 CHIPS DELIVERED

12 MOS TRANSISTOR PHYSICAL CHARACTERISTICS

14 VIEWING TRANSISTORS AS IMPERFECT SWITCHES Figure 1.2 nmos and pmos switch symbols and characteristics

15 Complementary Switch: Transmission Gate Figure 1.3 A complementary CMOS switch

16 Figure 1.4 A CMOS inverter CMOS Logic Inverter

17 Series: Switch Combinations:

18 Parallel:

19 NAND Gate

20 NAND Gate (con t)

21 NAND Gate (con t)

22 NOR Gate

23 NOR Gate (con t)

24 NOR Gate (con t)

25 Figure 1.8 Construction of function F = ((A.B) + (C.D))

26 Figure 1.8 (con t)

27 Figure 1.11 Connection of components for a simple CMOS flip-flop

28 CMOS flip-flop (con t)

29 CMOS flip-flop (con t)

30 Multiplexer

31 heykids.wav Figure 1.14 Digital design domains and levels of abstraction

32 Figure 1.16 An abstract view of the physical representation of a CMOS adder

33 Figure 1.21 The design flow for a CMOS chip

34 Behavioral Representation - describes how design should respond to a set of inputs - e.g. boolean equations, truth tables of I/O values, high level computer algorithms, HDL (e.g. VHDL, Verilog) Structural Representation - examples of hierarchy in this type of representation: : module level, gate level, switch level, circuit level - SPICE, SPECTRE-----circuit simulators using a structural representation of circuit Physical Representation - defines how part is to be constructed to yield specific structure and behavior - layout of mask layers - lowest level is photomask information used to manufacture device-----rectangles for various layers e.g. metal, contacts, diffusions, poly, etc - module level-----geometry -----call to sub modules e.g. trans, wires, contacts

35 CIRCUIT REPRESENTATION 1. BEHAVIORAL e.g. F = ((A.B) + (C.D)) 2. STRUCTURAL How the components are interconnected to achieve desired behavior A: Schematic diagram B: Description suitable for computer representation (for simulation, etc) Part inv (in) -> out Nfet out in vss Pfet out in vdd End Type Drain Gate Source Nfet out in vss

36 Example using a NAND gate: Behavioral Structural (schematic) out = -(a&b) out = (not (and a b)) Structural (for modelling) Part nand2 (a, b) -> out Signal il Nfet il a vss Nfet out b il Pfet out a vdd Pfet out b vdd End

38 Part nand2 (a, b) -> out Signal il End Nfet il a vss Nfet out b il Pfet out a vdd size = 2 Pfet out b vdd size = 2 Capacitance a 100 Capacitance b 100 Capacitance out 200

39 The circuit simulator that SPICE uses a similar form:.subckt NAND2.VDD A B OUT MN1 I1 A VSS VSS NFET W=8U L=4U AD=64P AS=64P MN2 OUT B I1 VSS NFET W=8U L=4U AD=64P AS=64P MP1 OUT A VDD VDD PFET W=16U L=4U AD=128P AS=128P MP2 OUT B VDD VDD PFET W=16U L=4U AD=128P AS=128P CA A VSS 5OfF CB B VSS 5OfF COUT OUT VSS 100fF.ENDS wiring capacitance capacitance computed from areas

40 HIERARCHICAL DESCRIPTIONS Part inv (in) -> out Nfet out in vss Pfet out in vdd End Part tg (a, c, cb) -> b Nfet a c b Pfet a cb b End Part flipflop (in, ld, ldbar, q, qbar) Signal a tg (in, ld, ldbar) -> a inv (a) -> qbar inv (qbar) -> g tg (q, ldbar, ld) -> a End

41 Hierarchical Descriptions (con t) Part flipflop (in, ld, ldbar, q, qbar) Signal a tg (in, ld, ldbar) -> a inv (a) -> qbar inv (qbar) -> q tg (q, ldbar, ld) -> a End

42 3. Physical Representation How is it constructed? Represents Gate Electrode Represents n-diffusion Source and Drain n-transistor

43 Symbolic Level p-transistor

45 Topics to Cover Design Representations Basic Manufacturing Process Fabrication Technology CMOS Process CMOS3/CMOS4S

46 USE OF HIERARCHY IN PHYSICAL REPRESENTATION

47 Use of Hierarchy in Physical Representation (con t)

48 Use of Hierarchy in Physical Representation (con t)

49 THE MANUFACTURING PROCESS In simplified form, the manufacturing is done by producing the required features on silicon by a process of implantations, diffusions, and metalization (depositing metal) under the control of mask. It is the masks which must be designed with the aid of the CAD system. A common step involves depositing an insulating layer of SiO 2, then using a mask to selectively expose a portion of the underlying substrate by etching:

50 The Manufacturing Process (con t)

51 The Manufacturing Process (con t) Resist

52 Expose resist through mask The Manufacturing Process (con t)

53 The Manufacturing Process (con t)

54 Czochralski Method - most common method - large wafers - high throughput - approx o C - cut and polish Figure 3.1 Czochralski method for manufacturing silicon ingots

55 FLOAT ZONE CRYSTAL GROWTH - no crucible, avoids contamination - difficult to get large waffers - generally requires long time to form final ingots Figure 3-12 The apparatus for float-zone crystal growth

56 PREPARATION OF MASKS The tape produced by the layout CAD tool is sent to a mask house which has a machine called a pattern generator (the input tape for this machine is called a PG tape ). This machine produces a reticle for each mask, usually at 10 times the real size on the photographic plate. This is not unlike the photoplotter used to make printed circuit artwork.

57 Preparation of Masks (con t)

58 The pattern generator exposes the film by flashing rectangular patterns. when the plate is developed we get a 10X reticle for one mask layer:

59 From the repticle, a 1X master mask is made using a step and repeat camera ( photorepeater ) producing a mask (1X size). This mask contains an array of identical layout patterns which will be used to produce working plates or working masks by contact printing.

60 The working masks are used during the fabrication to expose a whole wafer of silicon at a time, which will be subsequently divided into chips. These chips will be tested and packaged as individual integrated circuits.

61 *rest of process continued on next slide

62 *process continued from previous slide

63 Lithographic Projector - finer control - slower - more control over a number of different types of chips - more expensive * see next slide for diagram

64 Figure Schematic of a demagnifying electron projection printing system

65 CHEMICAL VAPOR DEPOSITION - pyrolysis as gaseous material comes in contact with substrate surface - typically used to deposit SiO 2 and polysilicon - can be used to grow silicon crystals (epitaxial growth) - low temperature * see next slide for diagram

67 ION IMPLANTATION Figure 7.20 The essential components of an ion-implantation system - low temperature - can implant through other layers - fine control of implant profile - expensive - can cause damage to substrate at high energy levels

68 Sputtering - materials energized in a high energy field (also vacuum) - substrate is anode while deposition material is cathode - insulators can be sputtered by mixing with sputtering gas (reactive sputtering) * see next slide for diagram

70 Typical p-well CMOS process with the appropriate masks

71 Typical p-well CMOS process with required masks (con t)

72 Typical p-well CMOS process with the appropriate masks (con t)

73 Typical p-well CMOS process with required masks (con t)

75 Figure 3.7 Layout and process cross section of transistors and inverter in p-well CMOS technology

77 THE CMOS PROCESS (COMPLEMENTARY MOS) In the CMOS process, NMOS and PMOS transistors are used in complementary pairs on the same substance. Original substrate is n-type and p-tubs (or p-wells) are made (for the NMOS transistors) by diffusing the p-type material with a mask. * see next slide for diagram

78 The circuit we are illustrating is and inverter, which uses one of each type of transistor in series.

79 Notice in the actual implementation that there are additional diffusions to connect the sources of each transistor to the substrate (the PMOS transistor) or the p-well (NMOS). The substrate is, in fact, at +5V and the p-well is grounded. This ensures that all PN junctions (which act as diodes) are back biased and do not conduct (i.e. short ).

80 P-well N-well Figure C.1: CMOS3 DLM Process for a Simple Inverter and Capacitor (steps 1 and 2)

81 Figure C.1: CMOS3 DLM Process for a Simple Inverter and Capacitor (steps 3 and 4)

82 Figure C.1: CMOS3 DLM Process for a Simple Inverter and Capacitor (steps 5 and 6)

83 Figure C.1: CMOS3 DLM Process for a Simple Inverter and Capacitor (steps 7 and 8)

84 Figure C.1: CMOS3 DLM Process for a Simple Inverter and Capacitor (steps 9 and 10)

EECS150 - Digital Design Lecture 2 - CMOS

EECS150 - Digital Design Lecture 2 - CMOS January 23, 2003 John Wawrzynek Spring 2003 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor