EECS 270 Homework the Last Winter 2017

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1 EECS 270 Homework the Last Winter 2017 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. NOTES: 1. This is an individual assignment. 2. Recall that you will get to drop one individual homework and one group homework. 3. This is would be a reasonable final 4. This assignment, like all the others, will be scored out of 30. You ll get your score divided by 3 (so up to a 33.3) as your score out of 30. Be sure to show work and explain what you ve done when asked to do so

2 1. Fill in each blank or circle the best answer. [12 points, -2 per wrong or blank answer, min 0] a. The 4-bit 2 s complement representation for -3 is. b. Write as a decimal number. c. A*!B + A*C in canonical sum-of-products form is. d. B*C *D / A *C *D / A*D / A *C*D is an implicant of A *B *C + B*D. e. The truth table for a 4-input XOR gate has maxterms. f. In static CMOS you d need at least transistors to implement a 3-input OR gate. g. In the SPI bus, data sent to the initiator of an SPI transaction is generally placed on the SS / SSEL / MOSI / MISO / 007 wire. h. A set that allows for the correction of a 2 bit error would have a Hamming Distance of at least 2. Consider the an error correction scheme where P( ) is the even one s parity function (as in class) and there are 4 bits of data {ABCD}. If we are correcting 1 bit of error, and two of the error correction bits are sent as X=P(B,C,D), Y=P(A,C,D) then it must be the case that: Z=P( ) or Z=P( ) [4 points] 3. In the time period of the 7400 series chips, JK flip flops were commonly used. Now they are not. Why is that? What has changed? Your answer is to be no more than 40 words. [5 points]

3 4. On Logical Minimization and the Jargon Thereof. [9 points] Consider the following logic function represented in a Karnaugh map: ab/cd d 1 1 a) List all of the Prime Implicants (provide as a comma separated list such as AB, AC, D) for this function: b) List all of the distinguished ones (provide the binary value of each distinguished one) for this function. c) Provide a minimal sum-of-products for this function: 5. Draw a state-transition diagram for the following state machine. [6 points] X D Q CLK Out

4 6. Write a Verilog module called Shift_Right6. It is to implement a six-bit shift-right register. o Inputs are clock, data_in and shift_enable o Output is the shift-register s value, Q[5:0]. The shift register should shift to the right on the rising edge of the clock if shift_enable is 1, placing the value of data_in into the most significant bit. Otherwise the register should hold its value. You will be graded for correctness, syntax and efficiency of you design and code. [8 points]

5 7. Find the minimal sum-of-products of F using the Quine-McClusky algorithm. For this problem we ll be grading your answer primarily based on your work so be sure to be careful, clear and neat. Use the format provided. [12 points] F=ΣA,B,C,D(0,6,9,11,12,13,14,15) Column I Column II Column III List of Prime Implicants (Provide in the form AB, AC, D) List of distinguished ones (provide the binary value of each distinguished one): Minimal sum-of-products:

6 8. In class we discussed building a JK-flip flop using a D flip-flop module. Here we would like to build a configurable flip-flop out of a D flip-flop. Depending on two mode bits, it will either act like a T flip-flop, a JK flip flop, or a D flip flop. Examine the table below. mode flip-flop type I[1] I[0] 00 T flip-flop T don t care 01 JK flip-flop J K 10 D flip-flop D don t care So if mode=01, the device would work like a JK flip-flop with I[1] being treated as the J input and I[0] being the K input. We have provided part of an answer. There are three blanks you need to fill in below. [12 points] module conf_ff(clock,i,mode,q); input clock; input [1:0] I,mode; output Q; wire X; assign X = ( )? I[1] : (mode[0])? : (I[1] & ~Q & Q); Dff D1(clock, X, Q); endmodule

7 9. You were given the following FPGA implementation for two functions, F and G. [16 points] P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 D A B C E C G F a) Write these functions in sum-of-products form. [8 points, F is 3 points, G is 5] F = G = b) Modify the above diagram tables so that H=(D*!A)+(D*!B) by only adding things to blank spaces. If that cannot be done, explain why. [8]

8 10. Design a circuit which takes a 4-digit 2 s complement number X[3:0] and outputs a 5-digit two s complement Z[4:0] number which is twice the absolute value of X. If the result overflows, Z[5:0] s value does not matter. There is also an output called overflow which should be a 1 if, and only if, the output overflows. Your design must use the 4-bit adder shown and may use no more than 10 additional gates (2- input OR, AND, XOR as well as NOT gates). Remember that bubbles count as NOT gates. You may freely use ground and power. Answers that use more than 10 gates or use devices other than those 10 gates will receive no credit. [16 points] 4-bit adder A3 A2 A1 A0 B3 B2 B1 S3 S2 S1 S0 Cout B0

EECS 270 Final Exam Spring 2012

EECS 270 Final Exam Spring 2012 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points 2 /20 3 /12 4 /10 5 /15