Digital Integrated Circuits EECS 312. Review. Combinational vs. sequential logic. Sequential logic. Introduction to sequential elements

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1 IBM ES9000 Bipolar Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CC Cyber 20 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(SIP) NTT Fujitsu M-780 Year of announcement IBM RY CMOS Jayhawk(dual) IBM RY7 Prescott T-Rex Mckinley Squadro IBM GP IBM Z9 Pentium Typical Current raw 1 sec Heartbeat 30 beats per sample Sampling and Radio Tramission 9-1 ma Radio Receive for Mesh Maintenance 2-6 ma Heartbeat Low Power Sleep 1-2 ma ma Time (seconds) igital Integrated Circuits EECS Review Teacher: Robert ick Office: 2417-E EECS dickrp@umich.edu Phone: Cellphone: HW engineers SW engineers GSI: Office: Current (ma) Shengshou Lu 272 BBB luss@umich.edu What is charge sharing? Why are there two different expressio for the voltage to which V out settles? Is leakage a significant factor in charge sharing? How can it be prevented? What is volatile memory? What is non-volatile memory? What is static memory? What is dynamic memory? Power deity (Watts/cm 2 ) erive and explain. 2 Robert ick igital Integrated Circuits Combinational vs. sequential logic Sequential logic No feedback between inputs and outputs combinational Outputs a function of the current inputs, only Feedback sequential clock q flip flops plain old combinational logic Outputs depend on current state and (maybe) current inputs Next state depends on current state and input For implementable machines, there are a finite number of states Synchronous State changes upon clock event (traition) occurs Asynchronous State changes upon inputs change, subject to circuit delays 4 Robert ick igital Integrated Circuits Robert ick igital Integrated Circuits Flip-flop introduction Introduction to sequential elements Stores, and outputs, a value. Puts a special clock signal in charge of timing. Allows output to change in respoe to clock traition. More on this later. Timing and sequential circuits Feedback and memory. Memory. Latches. 6 Robert ick igital Integrated Circuits 7 Robert ick igital Integrated Circuits

2 Feedback and memory Bistability Feedback or physical state are the root of memory. Can compose a simple loop from inverters. However, there is no way to switch the value. 8 Robert ick igital Integrated Circuits 9 Robert ick igital Integrated Circuits TG and NOT-based memory TG and NOT-based memory Can break feedback path to load new value However, potential for timing problems Can break feedback path to load new value. How can this be made more area-efficient? Resize traistors, remove traistors, use state? Robert ick igital Integrated Circuits 11 Robert ick igital Integrated Circuits Reset/set latch Reset/set timing R S R S 0 Reset Hold Set Reset Set Race R Utable state Utable state S 13 Robert ick igital Integrated Circuits 14 Robert ick igital Integrated Circuits

3 RS latch state diagram Clocking terms output= input=r S 11 Input T su T h Clock Clock Rising edge, falling edge, high level, low level, period Setup time: Minimum time before clocking event by which input must be stable (T SU ) Hold time: Minimum time after clocking event for which input must remain stable (T H ) Window: From setup time to hold time 1 Robert ick igital Integrated Circuits 16 Robert ick igital Integrated Circuits Gated RS latch Gated RS latch S S R R ENB ENB 17 Robert ick igital Integrated Circuits 18 Robert ick igital Integrated Circuits Memory element properties Active high traparent Active low traparent Type Inputs sampled Outputs valid Unclocked latch Always LFT Level-seitive latch Clock high LFT (T SU to T H ) around falling clock edge Edge-triggered flip-flop Clock low-to-high traition elay from rising edge (T SU to T H ) around rising clock edge CLK Positive (rising) edge CLK CLK Negative (falling) edge CLK 19 Robert ick igital Integrated Circuits 21 Robert ick igital Integrated Circuits

4 Timing for edge and level-seitive latches Latch timing specificatio Clk edge Minimum clock width, T W Usually period / 2 Low to high propegation delay, P LH High to low propegation delay, P HL Worst-case and typical level 22 Robert ick igital Integrated Circuits 23 Robert ick igital Integrated Circuits Latch timing specificatio FF timing specificatio Example, negative (falling) edge-triggered flip-flop timing diagram T su 20 T h T su 20 T h Clk T w 20 T plh C» 27 1 T phl C» 2 14 Minimum clock width, T W Usually period / 2 Low to high propagation delay, P LH High to low propagation delay, P HL T plh» 27 1 T phl» Robert ick igital Integrated Circuits 2 Robert ick igital Integrated Circuits FF timing specificatio RS latch states Example, positive (rising) edge-triggered flip-flop timing diagram Clk T su 20 T h T w 2 T su 20 T h S R + + Notes utable T plh 2 13 T phl Robert ick igital Integrated Circuits 27 Robert ick igital Integrated Circuits

5 Falling edge-triggered Edge triggered timing Use two stages of latches When clock is high First stage samples input w.o. changing second stage Second stage holds value When clock goes low First stage holds value and sets or resets second stage Second stage tramits first stage + = One of the most commonly used flip-flops 0 Positive edge t riggered FF Negative edge t riggered FF 29 Robert ick igital Integrated Circuits 30 Robert ick igital Integrated Circuits RS clocked latch Storage element in narrow width clocked systems. angerous. Fundamental building block of many flip-flop types. Minimizes input wiring. Simple to use. Common choice for basic memory elements in sequential circuits. 31 Robert ick igital Integrated Circuits 32 Robert ick igital Integrated Circuits Toggle (T) flip-flops Asynchronous inputs State changes each clock tick Useful for building counters Can be implemented with other flip-flops with XOR feedback How can a circuit with numerous distributed edge-triggered flip-flops be put into a known state? Could devise some sequence of input events to bring the machine into a known state. Complicated. Slow. Not necessarily possible, given trap states. Can also use sequential elements with additional asynchronous reset and/or set inputs. 33 Robert ick igital Integrated Circuits 34 Robert ick igital Integrated Circuits

6 Schmitt triggers Reason for gradual traition A B A traition B A logic stage is an RC network Whenever a traition occurs, capacitance is driven through resistance Coider the implementation of a CMOS inverter 36 Robert ick igital Integrated Circuits 37 Robert ick igital Integrated Circuits ebouncing ebouncing Mechanical switches bounce! What happe if multiple pulses? Multiple state traitio Need to clean up signal V Schmidt trig. RC e e e+00.0e e-03 1.e-03 T (s) 38 Robert ick igital Integrated Circuits 39 Robert ick igital Integrated Circuits Latch and flip-flop equatio Review RS T + = S + R + = + = T What are t su and t h? efine Level-seitive. Edge-triggered. Latch. Flip-flop. What is the symbol for a falling edge triggered? Show a circuit design for a Schmitt-trigger inverter. erive and explain. 40 Robert ick igital Integrated Circuits 41 Robert ick igital Integrated Circuits

7 istributed loads and Elmore delay More on traistor sizing erive the propagation delay of an aluminum wire that is 2 cm long and 00 nm wide. oes using a lumped model introduce significant error? You may assume a sheet resistance of 0.07 Ω/. erive the propagation delay of a copper wire with the same shape. State, and verify, any assumptio. f (a, b, c) = ab + c erive and explain. erive and explain. 42 Robert ick igital Integrated Circuits 43 Robert ick igital Integrated Circuits Volatile memory Non-volatile memory SRAM cell and architecture overview. RAM cell and architecture overview. ROM. EPROM. EEPROM. Flash. 4 Robert ick igital Integrated Circuits 46 Robert ick igital Integrated Circuits Floating gate technology Hot floating gate implementation UV erase. Electrical erase. Block erase. Was once difficult to design uniform-thickness thin oxide layers. Tunneling-based programming was difficult. Avalanche injection (hot electron) based programming used. UV erasure. Pure tunneling later became practical (EEPROM). Flash uses hot electro for programming and tunneling for erasing. 47 Robert ick igital Integrated Circuits 48 Robert ick igital Integrated Circuits

8 Array memory architecture Block-based memory architecture 49 Robert ick igital Integrated Circuits 0 Robert ick igital Integrated Circuits Memory timing Review What are the different ways a floating-gate memory cell can be erased? What are the different ways a floating-gate memory cell can be programmed? What are the two main RAM bit cell organizatio, and their advantages? Why is it difficult to economically put RAM on the same die as a processor? Why are decoders and MUXs used in memory arrays? erive and explain. 1 Robert ick igital Integrated Circuits 2 Robert ick igital Integrated Circuits NOR ROM schematic NOR ROM layout Program using active layer. 4 Robert ick igital Integrated Circuits Robert ick igital Integrated Circuits

9 NOR ROM layout NAN ROM schematic Program using contacts. 6 Robert ick igital Integrated Circuits 7 Robert ick igital Integrated Circuits NAN ROM layout NAN ROM layout Program using metal layer. Program using implants. 8 Robert ick igital Integrated Circuits 9 Robert ick igital Integrated Circuits RAM RAM 61 Robert ick igital Integrated Circuits 62 Robert ick igital Integrated Circuits

10 RAM side view ifferential see amplifier Useful for SRAM, can use two stages. 63 Robert ick igital Integrated Circuits 64 Robert ick igital Integrated Circuits Latch see amplifier Charge pump Useful for RAM. 6 Robert ick igital Integrated Circuits 66 Robert ick igital Integrated Circuits Upcoming topics assignment I Theoretical foundatio for sizing. 31 October: Read Sectio 6.3 and 7.1 in J. Rabaey, A. Chandrakasan, and B. Nikolic. igital Integrated Circuits: A esign Perspective. Prentice-Hall, second edition, November: Read Sectio 7.2.2, 7.2.3, 7.3.1, 7.3.2, and in J. Rabaey, A. Chandrakasan, and B. Nikolic. igital Integrated Circuits: A esign Perspective. Prentice-Hall, second edition, November: Project Robert ick igital Integrated Circuits 69 Robert ick igital Integrated Circuits

11 assignment II 12 November: Read Sectio , , and in J. Rabaey, A. Chandrakasan, and B. Nikolic. igital Integrated Circuits: A esign Perspective. Prentice-Hall, second edition, November: Read Sectio , , , and in J. Rabaey, A. Chandrakasan, and B. Nikolic. igital Integrated Circuits: A esign Perspective. Prentice-Hall, second edition, November: Robert ick igital Integrated Circuits