A Proposal for the LDPC Decoder Architecture for DVB-S2

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1 A Proposal for the LDPC Decoder Architecture for DVB-S Harihara S.G, M.Girish Chadra, B.S. Adiga, D.N. Praod, P. Balauralidhar bedded Systes Group, ata Cosultacy Services, Bagalore, INDIA. { harihara.g,.gchadra, bs.adiga, praod.d balaurali.p}@tcs.co Abstract- Low Desity Parity Check (LDPC) codes have becoe very popular i recet ties due to their capacity approachig perforace ad are cosidered i the ext geeratio digital video broadcastig DVB-S stadard. his paper presets a architecture for the decoder after a careful ad detailed study of the Stadard, exploitig the structure ad regularities of the stadardized code. I. INRODUCION LDPC codes are liear block codes origially proposed by Gallager i the early 960s [. heir parity check atrix is sparse havig low desity of oe () etries. Regular codes have uifor colu ad row weight i a parity check atrix; other wise the codes are referred to as irregular [4,[,[3. hese codes have eerged as copetitors for turbo codes, with perforace away fro capacity liits by a fractio of a db. he popularity of LDPC codes fro the past couple of years led ito the proposals for utilizig the code for various applicatios ad stadards (both for wireless ad wired), oe exaple beig the DVB-S [9,[0,[ stadard, which is the latest digital video broadcastig stadard, where S stads for satellite ad for secod geeratio. Siilar to turbo codes, the good perforace of LDPC codes is achieved with a proper choice of code ad decodig sigal processig. he popular LDPC decodig algorith is the Belief Propagatio (BP) algorith (also referred to as Su- Product algorith). his ca be viewed as a essage passig algorith operatig o the aer graph [4, which is a bipartite graph represetig the parity check atrix, ad cosistig of variable odes ad check (or costrait) odes. he algorith starts with iitializatio ad i each iteratio essage passig occurs fro each check ode to all adjacet variable odes (first half of iteratio) ad the i the secod half, fro each variable ode to its adjacet check odes. he decodig perforace is achieved through repeated iteratios of the essage passig alog the edges of the graph, with soe stoppig criterio [4,[5. Sice error cotrol codig is a iportat copoet of the oder day couicatio systes, it is atural to see vigorous research ad efforts are put ito VLSI/ASIC/FPGA realizatios of the LDPC decoders ad ecoders. Cocetratig o the decoders, oe ca see the proposals of differet structures o various platfors [5,[6,[7,[5,[6. here are differet issues to be cosidered i the realizatio like, serial, parallel or sei-parallel architectures, edge eory (eory to store essages passed alog the edges of aer graph) requireet, processig uit coplexity (for check ode processig), ad so o [6. Sice satellite dowlik is a power liited chael ad further, error rate requireets of DVB-S are rather striget 7 (the packet error rate of 0 is the requireet for the MPG packets trasitted), a powerful error cotrol codig i the cobiatio of outer BCH code ad ier LDPC code has bee suggested after closely exaiig several cadidates i ters of perforace ad estiated ASIC size [0. he outer BCH code clea up additioal errors (up to errors) ad will iprove the overall perforace (aily reducig the error floor) [0,[. Siulatio results reflectig the (packet error rate) perforace of DVB-S LDPC codes are well docueted i the literature [0, [. his paper, o the other had, presets soe discussio ad results required for the hardware ipleetatio of DVB-S LDPC decoder. We cocetrate o a sei-parallel architecture for the decoder. I the directio of proposig this architecture, it is very essetial to carry out a careful ad detailed study of the Stadard, exploitig the structure ad regularities of the stadardized code. hese are the required to be traslated ito a hardware appig. he paper is orgaized as follows: i Part II, a brief etio is ade about the essage passig algorith ad ways to realize the decoder, brigig out the ecessity of sei-parallel architecture for DVB-S codes. Sice a proper architecture deads the structure of the code to be exploited, Part III presets few relevat details of the stadardized LDPC codes i this directio. Part IV cocetrates o hardware appig. Coclusios are give i Part V. II.MSSAG PASSING DCODING AND SMI- PARALLL ARCHICUR he Su-Product origially proposed by Gallager hiself, ca be writte i the sig-agitude processig for as

2 follows [6, [4. he algorith is ow well uderstood ad very eat iterpretatios of the echais of algorith operatio are ow available (see pp.8-9 of [; see also [0 ad [3). he algorith uses log-likelihood ratios (LLRs), that is, the values hadled are LLRs. he algorith operates by passig essages o the aer graph associated with the parity check atrix of the code. he steps ivolved are (the otatio is adopted fro [6 with slight odificatio; see also [8): Iitializatio: Iteratio: ( 0) = I ; For iteratio couter updates ( 0) = 0 l =,, Ll, do the followig Check ode update rule ( ) ( ) ( l) l l ( ) Φ Φ( ) sg,, () ax = Ν ( )\ Ν ( Variable ode update rule: Last variable ode update rule: ( l ) = I )\ + ( l) Μ ( )\ ( l ) ( l ) = I + Μ ( ) I the above,, is the iforatio set by a variable ode to its coected check ode ;, is the essage passed fro check ode to the coected variable ode (iforatio give by the parity check o bit ); Μ () is the set of check odes coected to variable ode ; Ν () is the set of variable odes coected to check ode ; x Φ( x) = log tah with x > 0. I is the chael LLR value ad ca be obtaied depedig o the chael (Additive White Gaussia Noise (AWGN), biary syetric, etc) [4,[6. \ is the usual exclusio sybol. l idicates the l iteratio uber with ax beig the uber of iteratios. It ca be observed that check ode coputatio is ore coplex. he oliear fuctio Φ (x) is ipleeted usig the look-up table (LU). here are differet variatios (approxiatios) of the above su-product algorith, which is referred to as regular suproduct algorith. See [6, [ ad the refereces there i for the said variats. he ai challege i the LDPC code decoder hardware ipleetatio is how to effectively aage the essage passig durig the iterative BP decodig [5. Decoder ipleetatio fall ito three categories: () Parallel () Serial ad (3) Sei Parallel. Fully parallel decoders directly istatiate the bipartite graph of the LDPC code to the hardware. ach idividual variable ode or check ode is physically ipleeted as ode fuctioal uit, ad all the uits are coected through a itercoectio etwork reflectig the bipartite graph coectivity. here is o eed for cetral eory blocks to store the essages. hey ca be latched close to the processig uits [5. Such fully parallel decoders ca achieve very high decodig throughput i ters of bits per secod. But, area of ipleetatio (due to the ipleetatio of all the processig uits) ad itercoect routig ake this approach ifeasible for large block legths (ore tha couple of thousads of bits). Further, the parallel hardware desig is fixed to a particular parity check atrix. his prohibits the recofigurability required whe the block legth or rate of the code chages (both chage the parity check atrix). Fully-serial architecture has the sallest area sice it is sufficiet to have just oe variable coputatio uit (VCU) ad oe check coputatio uit (CCU). he fully-serial approach is suitable for DSPs i which there are oly a few fuctioal uits available to use. However, the speed of decodig is very low i a serial decoder. Partially parallel or sei-parallel decoder targets o appropriate trade-offs betwee hardware coplexity ad decodig speed [5,[5. hey cosist of a array of ode coputatio uits to perfor all the ode coputatio (i tie-divisio ultiplexig ode) ad a array of eory blocks to store all decodig essage. he essage passig that reflects the bipartite graph coectivity is joitly realized by the eory address geeratio ad the itercoectio aog eory blocks ad ode coputatio uits. hey ca support flexible code rate cofiguratios ad degree distributios. Sice the stadardized DVB-S LDPC codes are log ad there is a requireet to work with differet rates ad block legths (see ext sectio), a sei-parallel architecture is the suitable oe for DVB-S. But, for sei-parallel desigs, the parity check atrix should be relatively structured i order to eable re-usability of coputatio uits [5. I the ext sectio we preset few details relevat to the stadardized code, ad also brig out certai structure ad regularity (see also Sectio IV). III.DVB-S LDPC COD AND SOM RLAD SRUCUR DVB-S fixes the legth of the ecoder output ad there are two forward error correctio (FC) fraes defied- oral frae of legth ad short frae of legth 600. Noral fraes ca be ecoded i eleve differet rates ad short fraes i te [9,[0,[. I order to facilitate systeatic ecodig ad produce irregular LDPC that are especially suitable for high code rates, DVB-S uses a class of LDPC codes called exteded irregular repeat accuulate (eira) codes [0, [4. With irregular codes iproved perforace is possible, sice variable odes with higher degrees (degree is uber of adjacet odes) collect ore iforatio fro their adjacet check odes ad they get corrected first after few iteratios. hey the help

3 other variable odes to get corrected through iterative decodig, siilar to wave effect [0. Whe all variable odes have the sae degrees, as i regular codes, this wave effect is ot preset ad all variable odes ca get stuck durig the decodig process [0. I the Stadard, variable odes ca be of degree up to 3 (depedig o the rate) [9,[0. We have worked out check-ode degree distributio for the stadardized code for differet rates [3. Sice these stadardized codes are very log, certai structure is iposed o parity check atrices H, to facilitate the descriptio ad easy ecodig. More specifically H is of the for [0, [: H = [ H H () where, H is a sparse ( N K ) K atrix ad H is staircase lower triagular atrix of diesio ( N K ) ( N K ) H = O O O : I the above, N is the block legth ad K is the uber of essage bits (legth of iforatio block); ( N K ) is the uber of parity bits added. his restrictio of H portio of the atrix leads to egligible (withi 0. db) perforace loss with respect to a geeral parity check atrix [0. Additioally, H is related to differetial ecodig or accuulatio; LDPC codes are eira codes. With this structure, ecodig ca be carried out usig the parity check atrix with liear coplexity (ot the geerator atrix, which beig dese results i quadratic ecodig coplexity) by otig Hc = 0 (4) ad recursively solvig for parity bits [0. I (4), c is the code word. For the reduced storage of H, adjacet check odes of oly oe variable ode i a group of 360 are tabulated i the stadard. he check odes coected to the first variable ode of the group are i geeral radoly chose so that the resultig LDPC code is cycle-4 free ad occurrece of cycle-6 is iiized to the extet that a solutio ca be foud (by the decoder) withi a reasoable search tie [0. he addresses of the other 359 parity check odes are geerated usig the equatio [9: { x q} od ( N K ) (3) od (5) where, x deotes the address of the parity bit ode correspodig to the first bit of the group ad is the variable bit ode uber like,, L, 359 ad 36, 35, L, 79, so o. I (5), N K q = ad sice i DVB-S ecoder output 360 legth is fixed, K ad hece q vary with the rate. For rate /3, for which soe uerical results are preseted i the paper, q is 60. he choice of rate /3 is due to the fact that aog the rates specified i the Stadard, it is either too low or too high. he factor q is a iportat factor for recofigurig the proposed architecture for differet rates as we will see. Based o the details provided oe ca defiitely expect soe structure ad regularity i the aer graph coectivity for the stadardized LDPC codes. his is the sae as regularity of the addresses of the eighbors of check odes ad variable odes. Further, beig eira codes, the hardware decoder structure ca be elegatly apped as suggested i [4. hese issues are cosidered i detail i the ext sectio. IV. DCODR HARDWAR MAPPING ISSUS MOIVAION For the decoder hardware appig issues, a good startig poit is to view the aer graph as a collectio of variable odes o oe side (usually left) of a edge iterleaver ad check odes o the other side (see for istace [6, [3). dge iterleaver or perutatio etwork realizes the coectio betwee the odes. A further ehaceet is possible whe eira ature of the DVB-S codes are cosidered; the resultig structure is as i Fig. of [4. As suggested i [4, for the eira codes, variable odes ca be grouped ito three categories, depedig o the degree values; degree, degree 3, ad degree J, where J depeds o the rate. For rate /3 of DVB-S code, for exaple, J is 3. Beig a irregular LDPC code, the optial check ode degree of a eira code ca be proved to be cocetrated o oe or two degrees [, pp.53. For rate /3 code, out of 600 check odes, we have 599 odes with degree 0 ad oe with degree 9. Siilar degree distributios are observed for other rates [3 ad thus DVB-S codes are optial i ters of check-degree distributio. he choice of variable ode degrees ad coectivity also appears to be close to optiu as suggested by their ear capacity perforace [0, Fig.3, akig these codes a very powerful kow LDPC codes. Goig further with the structure, it is to be oted that the uber of variable odes with degree is ( N K ) ad they follow a zig-zag patter of coectivity with each of the check odes. he said zig-zag patter is visible i the H portio of the parity check atrix (see (3)). hese ( N K ) variable odes are referred to as parity odes (PN) ad the reaiig variable odes as iforatio odes (IN) i [4. he coectivity of IN ad PN variable odes to check odes ca be represeted by separate perutatio etworks Π ad Π ; see Fig.. As these etworks are disjuctive [4, IN ad PN processig ca be doe separately.

4 Sice a sei-parallel architecture is cosidered i this paper, we have certai uber of VCUs ad CCUs, each of the perforig several ode coputatios. VCUs ca be further divided ito IN ad PN coputatioal uits as etioed earlier, dividig the etire decoder architecture ito two parts; IN ad PN brach (see Fig.). Due to the siple ature of zig-zag etwork Π, the iportat desig aspect lies i hardware appig of IN processig. PROCSSING LMNS he ode coputatioal uits ca be serially (oe iput ad at ost oe output i a clock cycle) or parallely ipleeted. I serial processig all icoig edges of the ode are processed sequetially. he serial processig is used i our desig as it relaxes the costraits o the eory orgaizatio [6. Further, serial coputatioal uits ca be easily pipelied ad hece they are ot i the critical path [4. Additioally, the sequetial processig is advatageous whe it is required to hadle differet degrees as i the case of irregular DVB-S code. he structure of the processig eleets is described i ore detail i [3. Sice the fuctio Φ (x) defied i Sectio II is ivertible (i fact Φ ( x) = Φ( x) ), there is a possibility to ipleet total su first ipleetatio withi the serial structure [6. We have chose this ipleetatio for the processig eleet architecture. A good uber issues i the ipleetatio of VCU ad CCU i geeral ca be foud i [6 (pp.46-50). DCODR ARCHICUR he base eira decoder architecture is depicted i [4. But, the choice of uber of processig eleets ad hece the uber of eory baks, as well as the coectio echais betwee these to achieve aer graph coectivity eed to be worked out for the DVB-S code. I arrivig at the iteded structure, i this paper, we have cocetrated our study o the oral fraes. By the extesive ad detailed study carried out, it is foud that the addresses of the eighbors of a check ode as well as those of a variable ode are related to the rate-depedet paraeter q. As far as IN portio coectivity is cocered, for check odes, the address values geerally get icreeted by oe after every q check odes. For exaple, for rate /3, the addresses of the eighbors of the 60 th check ode are oe icreeted values of that of the 0 th ode. Siilar patter is also observed geerally for the addresses of the eighbors of the variable odes. he word geerally etioed twice accouts for the wrap aroud which takes place whe the address is a ultiple of 360. For exaple, while icreetig, if the address obtaied is 360, it becoes zero, if the address is 70, it becoes 360 ad so o. hat is, there is a decreet of 360. Based o this observatio it is decided to use 360 eleets each for IN, PN ad CN (check ode) processig i the serial-parallel architecture, with a coectio echais to take care of the wrap aroud proble. his coectio echais is depicted i Fig.. A siple icreet cotrol ca result i the ecessary zig-zag coectivity for PN portio (see Fig.); see [3 for ore elaboratio. I Fig., the etries show i the eory baks are the addresses of variable odes ad check odes. he 360 processig uits work i parallel ad fetch the iputs oe-byoe based o the etries give i the bak selector, which selects the bak ad the locatio poiter, which suggests the locatio withi the selected bak. he uber of addresses i the baks is rate depedet (hece o q). Fig. shows the addresses for rate /3; hece there are 4300 variable odes (for IN portio) ad 600 check odes. he reaiig 600 variable odes are i the PN portio. he uber of etries i the locatio-poiter register ad the bak selector apart fro rate depedet, vary durig the iterative procedure. he etries show are for rate /3 ad for the first 360 checkode processig operatios; the check odes i this set are 0, 60, 0,, 540 (see Fig.). For the ext 360 (, 6,, 54), differet etries eed to be loaded ito these registers. o elaborate the iterative procedure further, assue that the etire frae of received values is scaled ([4, [) to get appropriate LLRs ad are stored i baks (of IN ad PN portios) as suggested by addresses i Fig.. he check-ode uits ca the start processig. hey get the eight values sequetially fro IN portio (Fig.) ad the reaiig oe or two values fro the PN portio. For exaple, the eight values for check ode 0 are take fro zeroth locatio of zeroth bak, zeroth locatio of 356 th bak etc. 360 check ode uits ca get the values this way. Oce the processig is copleted, they geerate the sae uber of outputs as iputs ad these are put ito the eory baks i the CN portio i the respective addresses. he processig for the ext 360 check odes ca the be take up by loadig differet relevat etries ito the bak selector ad locatio poiter. A ovel cotributio i this paper is atheatical expressios, obtaied after careful study, for the etries of the locatio poiter ad bak selector (for the architecture of Fig.);. For each group of 360 check odes the locatio poiter ca be obtaied fro [ I od( I, 360) LP C = (5) 360 where I is the address of the iforatio ode coected to a particular parity check ode [3. he etries ca be worked out by pickig ay parity-check ode i the group. With this the zeroth bak for ay processig uit is the exactly opposite bak i Fig. ad the reaiig are couted dowwards i circular fashio. Further, i (5) od( I, 360) gives the bak selector value. All the differet register etries required for differet rates are available i [3. Oce all the check-ode processig is copleted, the variable ode processig ca be started agai 360 at a tie; both i IN ad PN portios, fetchig the values fro the CN eory baks. he ovel expressio for locatio poiter values is:

5 Fig. Proposed Scheatic of Decoder Architecture [ C od( C q), LP V = (6) q where C is the check-ode address ad agai ( C,q) od is the bak selector value. his copletes the decoder architecture desig ad i ipleetatio a cotroller is required to ake sure that all the uits are sychroized. V. CONCLUSIONS A sei-parallel decoder architecture for DVB-S LDPC code is preseted i the paper, exploitig structure ad regularities of the stadardized code. Further work is goig o i the directio of fie-tuig the proposed structure for differet approxiatios (see [) of the regular belief propagatio algorith ad fidig a suitable uber of bits for fixed-poit ipleetatios. RFRNCS [ R. G. Gallager, Low Desity Parity Check Codes, PhD dissertatio MI, 963. [ M. Girish Chadra, Harihara S.G, B.S. Adiga, Balauralidhar. P, P.S. Subraaia ffect of Check Node Processig o the Perforace of Message Passig Algorith i the Cotext of LDPC Decodig for DVB-S, ICICS 005, Dec.005 (ACCPD). [3 M. Girish Chadra, Harihara S.G, B.S. Adiga, Balauralidhar. P, P.S. Subraaia LDPC Decoder Desig for DVB-S, CS echical Report, July 005. [4 W.. Rya A Itroductio to LDPC Codes, i CRC Hadbook for Codig ad Sigal Processig for Recordig Systes (d. B. Vasic), CRC Press, 004. [5 M. Karkooti, J.R. Cavallaro, Sei-Parallel Recofigurable Architectures for Real-ie LDPC Decodig, ICC 004. [6 F. Guilloud, Geeric Architecture for LDPC Codes Decodig, PhD hesis uder SPRING project, July 004. [7. Yeo, B. Nikolic, ad V. Aathara, Architectures ad Ipleetatios of Low-Desity Parity Check Decodig Algoriths, I Iteratioal Midwest Syposiu o Circuits ad Systes, August. 00. [8 J. R. Barry,.A. Lee, D.G. Meeserschitt, Digital Couicatio, hird ditio Kluwer Acadic, 004. [9 uropea elecouicatios Stadards Istitute. Fial Draft SI N v.. DVB (005-0); Secod Geeratio Fraig Structure, Chael Codig ad Modulatio Systes for Broadcastig, Iteractive Services, News Gatherig ad other Broadbad Satellite Applicatios. [0 M. roz, F-W Su ad L-N Lee, DVB-S Low Desity Parity Check Codes with Near Shao Liit Perforace, IJSC, Ju 004. [ M. C. Valeti, S. Cheg, ad R. I. Seshadri, Digital Video Broadcastig, [ M. Ardakai, fficiet Aalysis, Desig ad Decodig of Low-Desity Parity-Check Codes, PhD hesis, 004. [3 G. Lecher, Covergece of the Su-Product Algorith for Short Low-Desity Parity Check Codes, Diploa hesis, Viea Uiversity of echology, April 003. [4 F. Kiele, N. Whe Desig Methodology for IRA Codes, Proceedigs of ASP-DAC 04, 004. [5 H. Zhog,. Zhag, Desig of VLSI Ipleetatio-Orieted LDPC Codes, I Seiaual Vehicular echology Coferece (VC), Oct [6 G. Lecher, A. Bolzer, J. Sayir, ad M. Rupp, Ipleetatio of a LDPC Decoder o a Vector Sigal Processor, Proc. 38 th Asiloar Cof. o sigals, Systes, ad Coputers, Nov. 004.