ELCT 501: Digital System Design

Transcription

1 ELCT 5: Digital System Lecture 8: System Dr. Mohamed Abd El Ghany,

2 Algorithmic State Machine (ASM) For large machines, the designers often use a different form of representation, called the algorithmic state machine chart. An ASM chart is a type of flowchart that can be used to represent the state transitions and generated outputs for an FSM. ELCT 5: Digital System Winter 2 2

3 Elements used in ASM Charts State name State box Output signals or actions (Moore type) (false) (true) Condition expression Decision box Conditional outputs or actions (Mealy type) Conditional output box ELCT 5: Digital System Winter 2 3

4 From FSM to ASM chart Reset A w B C w Z w ELCT 5: Digital System Winter 2 4

5 From FSM to ASM chart Reset A B w z w ELCT 5: Digital System Winter 2 5

6 Example A Bit-Counting Circuit to count the number of bits in a register Pseudocode for the bit counter B = ; While A do if a = then B= B+; end if; Right-shift A; End while; ELCT 5: Digital System Winter 2 6

7 ASM chart for the pseudo-code Reset S B = ; While A do if a = then B= B+; end if; Right-shift A; End while; Load A B<-B+ B <- s S2 Shift right A A=? a s S3 Done ELCT 5: Digital System Winter 2 7

8 Datapath for the ASM chart Data n log 2 n LA EA w L E Shift register LB EB L E Counter Clock A log 2 n n z a B ELCT 5: Digital System Winter 2 8

9 ASM chart for the control circuit Reset S S2 LB s EA s S3 Done EB z a ELCT 5: Digital System Winter 2 9

10 VHDL for the bitcounting circuit Part ELCT 5: Digital System Winter 2

11 VHDL for the bitcounting circuit Part 2 ELCT 5: Digital System Winter 2

12 VHDL for the bitcounting circuit Part 3 ELCT 5: Digital System Winter 2 2

13 VHDL for the bitcounting circuit Part 4 ELCT 5: Digital System Winter 2 3

14 ASM chart for the multiplier Reset Binary x Load A Load B P<-P+A S P <- s S2 Shift left A, Shift right B B=? b s S3 Done ELCT 5: Digital System Winter 2 6

15 Datapath circuit for the multiplier Data A n n Data B n Clock LA EA L E Shift- left register LB EB L E Shift-right register A 2n + B n sum 2n 2n P sel EP DataP 2n E register z b 2n P ELCT 5: Digital System Winter 2 7

16 ASM chart for the multiplier control circuit Reset S P sel =, EP EP s S2 P sel =, EA, EB z s S3 Done b ELCT 5: Digital System Winter 2 8

17 VHDL for the multiplier circuit Part ELCT 5: Digital System Winter 2 9

18 VHDL for the multiplier circuit Part 2 ELCT 5: Digital System Winter 2 2

19 VHDL for the multiplier circuit Part 3 ELCT 5: Digital System Winter 2 2

20 VHDL for the multiplier circuit Part 4 ELCT 5: Digital System Winter 2 22

21 Clock Synchronization Clock Skew: If the circuit of clock enable is used, then the flip-flops without the enable input will observe changes in the clock signal slightly earlier than the flip-flops that have the enable input. This situation, in which the clock signal arrives at different times at different flip-flops, is known as clock skew. Similar problems arise in a chip in which the clock signal is distributed to different flip-flops by wires whose lengths vary appreciably. clock E Dat a D Q Q Clock enable circuit ELCT 5: Digital System Winter 2 23

22 Clock Synchronization Clock Skew: For proper operation of synchronous sequential circuits, it is essential to minimize the clock skew as much as possible. The clock signal is distributed to the flip-flops such that the length of wire between each flip-flop and clock source is the same. An H tree clock distribution network ELCT 5: Digital System Winter 2 24