ENGG 1203 Tutorial. D Flip Flop. D Flip Flop. Q changes when CLK is in Rising edge PGT NGT
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1 ENGG 1203 Tutorial D Flip Flop Sequential Logic 14/21 Feb Learning Objectives Design circuits with Flip Flop Design a finite state machine News Feb 27, 2014, 11:55pm Ack.: HKU ELEC1008, ISU CprE 281x, PSU CMPEN270, Wikipedia Q changes when CLK is in Rising edge PGT CLK D Flip Flop Q1 NGT CLK 1 0 Remember to consider whether the FF is PGT or NGT Design a synchronous, recycling MOD-8 binary down counter with D FFs. Down counter: Counting in descending order MOD-8: Count from
2 Q2 K-map Fig. (a): A complete 4bit parallel adder with registers Fig. (b): Signals for addition For 1001 add 0101, describe what happen at t1, t2, t3, t4 and t5. Assume Co=0 5 6 At time t1, ݎ is active low FF at the bottom will be cleared 7 At time t2, load is active high Set A numbers will be loaded into the upper register 8
3 At time t 4, the load is active high, the set B numbers will be loaded into register B on PGT of LOAD pulse B 3 B 2 B 1 B 0 = 0101 At time t 3, transfer is active high Adder process between A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0 The sum S 3 S 2 S 1 S 0 = 1001 are transferred to register A on PGT due to this transfer pulse at t At time t 5, A 3 A 2 A 1 A 0 = 1001 and B 3 B 2 B 1 B 0 = 0101, the adder produces S 3 S 2 S 1 S 0 = This sum is transferred into register A when TRANSFER pulse occur at t 5. Finite State Machine (FSM) State transition diagram Truth table K-Map Circuit FPGA State Present state: before the register Next state: after the register State transition: during clock 2 n states: n FFs 11 12
4 Q3 Mealy From state transition diagram to truth table Four states Two-bit state q/q*: Present/Next state z: Output Moore Condition/Output From truth table to K-map From K-map to circuit State register Logic for state transition Logic for output A B D A D B D A D B 15 16
5 Q4 Design a 2-bit counter with input x that can be A down counter when x = 0 ( ) A Johnson counter when x = 1 ( ) Q5 When interfacing an external signal into the FPGA, it is possible that the internal digital signal may bounce between 1 and 0 when the external voltage is very close to the threshold voltage. To solve this problem, a digital debounce circuit can be used. A simple debounce circuit operates as follows: If the output is 0", it is changed to 1" only after two consecutive 1"s have been present in the input. If the output is 1", it is changed to 0 only after two consecutive 0 s have been present in the input. The debounce logic is implemented as a state machine with the following states: Draw a state transition diagram. Input is din; Output is dout. Output of the state machine (dout) should be specified within the state as it is a Moore machine. Express the output dout in terms of s1 and s
6 Q6 Next state of OUT 0 din=0 OUT0 din=1 SEEN1 First 1 Next state of SEEN1 din=0 OUT0 din=1 OUT1 Two consecutive 1"s dout = s0 s1 Design a FSM for the dimmer control The controller starts with display being turned off. The display turns on when the user has pressed the power button once. If the power button is pressed again, regardless of whether is in full or half brightness, the screen turns off When the screen is on, if a user has not touched the screen for more than 3 cycles, the screen should be dimmed to half the normal brightness. If it is idled for another 3 cycles, it should turn off automatically. However, if the user touch the screen at any time when it is dimmed, it should go back to full brightness immediately
7 The controller starts with display being turned off. The display turns on when the user has pressed the power button once. If the power button is pressed again, regardless of whether is in full or half brightness, the screen turns off. --- When the screen is on, if a user has not touched the screen for more than 3 cycles, the screen should be dimmed to half the normal brightness. --- If it is idled for another 3 cycles, it should turn off automatically However, if the user touch the screen at any time when it is dimmed, it should go back to full brightness immediately. Q7 Design a FSM for a vending machine Collect money, deliver product and change Vending machine may get three inputs Inputs are nickel (5c), dime (10c), and quarter (25c) Only one coin input at a time Product cost is 40c Does not accept more than 50c Returns 5c or 10c back Exact change appreciated 27 28
8 We are designing a state machine which output depends on both current state and inputs. Suppose we ask the machine to directly return the coin if it cannot accept an input coin. Input specification: I 1 I 2 Represent the coin inserted Input: We can insert 0 cents (00), 5 cents (01), 10 cents (10), 25 cents (11) Output specification: C 1 C 2 P C 1 C 2 represent the coin returned 00, 01, 10, 11 P indicates whether to deliver product 0, 1 States: S 1 S 2 S 3 Represent the money inside the machine now 3 bits are enough to encode the states S00 (0 cents) 000 S05 (5 cents) 001 S10 010; ; S Consider all situations (S00, S05,, S35) SS machine Truth table K-Map Circuit FPGA After considering all states S35: Currently the machine stores 35 cents If we insert 0 cents 00/000 Next state is S35 (The state repeats itself) If we insert 25 cents 11/110 Next state is S35 + Return 1 quarter + Return 0 product 35c (35 cents inside the machine) + 25c (Insert 25 cents) = 35c (35 cents inside the machine) + 25c (return 25 cents) + 0c (return no product) S35 00/000 11/
9 If we insert 10 cents 10/011 Next state is S0 + Return 1 nickel + Return 1 product 35c (35 cents inside the machine) + 10c (Insert 10 cents) = 0c (0 cents inside the machine) + 5c (return 5 cents) + 40c (return 1 product) If we insert 5 cents 01/001 Next state is S0 + Return 0 nickel + Return 1 product 35c (35 cents inside the machine) + 5c (Insert 5 cents) = 0c (0 cents inside the machine) + 0c (return 0 cents) + 40c (return 1 product) S35 10/011 01/001 (Appendix) Q8 The card reader tells the controller whether the car is a member or a guest car. Only one guest car is allowed per member at a discount rate Only when the guest follows out the member at the exit (within the allotted time) The second guest must pay the regular parking fees Design a FSM for the card reader Specifications Signals from the card reader: MEMBER, GUEST Signals from the toll booth TOKEN ( One toke received ) EXP ( Time for discounted guest payment has expired ) Signal to the gate: OPEN Fee Members: Free Guest with a Member: 1 Token Regular Guest: 2 Tokens. List out all situations through a truth table e.g. Idle Idle / Guest enters / Member enters X : Illegal/Not considered 35 36
10 Then, Truth Table K-map Circuit (Appendix) A typical FSM FSM Truth table Circuit State register (Appendix) Steps in designing a state machine Draw a state transition diagram An initial state Other states to keep track of various activities Transitions Generate a state transition table and a output table Write state transition table and output table in binary State assignment, i.e., the code used for each state Derive canonical sum-of-product expressions Draw the circuit Logic for state transition Logic for 39 output 40
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