Chapter 8 Registers & Counters

Transcription

1 Chapter 8 Registers & Counters 8.1 Introduction Register is a type of sequential circuit used to store binary information or to manipulate the binary information which consists of flip-flops and combinational circuit (optional). If there is n flip-flop in a register it can store n bits. The combinational circuit determines some data processing tasks (how the data is transferred in registers). The main function of the register is to store binary numbers. The data in one flipflop is required for another flip-flop (ie the output of one flip flop is input to other flip flop).in such cases the shift register is used. Shift register is also used in arithmetic operations. In shift register moving a binary number one bit to the left is equivalent to multiplying the number by 2 and moving the binary number one bit to the right is equivalent to dividing the number by Shift Register (1) Left shift Register In left shift register the data is shifted from right to left direction. It consists of serial input and serial output. Let assume at initial stage the data in all flip flop is 0. If the data 1111 is given to left shift register, after four clock pulse the data is stored in the flip flop. At fifth clock pulse the output is 1. Serial out Serial in 1111 FIG 8.1 Left shift register after four clock pulse (2) Right shift Register In Right shift register the data is shifted from left to right direction. It consist of serial input and serial output. Let assume at initial stage the data in all flip flop is 0. If the data 1010 is given to left shift register, after four clock pulse the 4 bit input data is stored in the flip flop. At fifth clock pulse the output is 0.At sixth clock pulse the output is 1. Serial in Serial out Fig 8.2 Right shift register after four clock pulse

2 8.2.1 Modes of operation There are four modes of operation in a shift register. They are 1. Serial in serial out 2. Serial in parallel out. 3. Parallel in parallel out 4. Parallel in serial out. Serial input data n- bit Serial output data Serial input data n- bit Parallel output data FIG.8.3 Serial in serial out Fig.8.4 Serial in Parallel out Parallel input data n- bit Parallel output data Parallel input data n- bit Serial input data Fig 8.5 Parallel in Parallel out FIG.8.6 Parallel in serial out Serial in serial out shift register. In serial in serial out shift register the data is applied in serial manner and the clock pulses are given to each flip flop. After each clock pulse the data move from one position to another and the output is obtained in serial form. A four bit shift register is constructed using D flip flop. The register is cleared, ie forcing all four output to 0. The input is applied sequentially to the D input of the first flip flop. The most significant bit is stored in FF0 and the least significant bit is stored in FF3. The four bit data is stored in the register after four clock pulse. Input Data FF0 FF1 FF2 FF3 D Q D Q D Q D Q CLK CLR Q CLK CLR Q CLK CLR Q FIG :8.7 serial in serial out shift Register CLK CLR Q Serial output data Clock Clear

3 8.2.3 Serial in parallel out shift Register In serial in parallel out shift register the input data is applied in serial manner and the output is obtained in parallel. The four D flip flops are used to construct the bit shift register is shown in fig 8.8. Here the output is taken at each flip flop. Once the data is stored, each bit appears on its respective output line, and all bits are available simultaneously. FIG :8.8 Serial in parallel out shift Register 8.2.4Parallel in serial out shift register A four bit parallel in serial out shift register is constructed with the help of D flip flop and NAND gates. The input is applied through NAND gate. The data bits are D0 to D3, where D0 is the most significant bit and D0 is the least significant bit. First the data is written in the NAND gate by making the shifted by making the WRITE / SHIFT as HIGH. WRITE / SHIFT LOW. Then the data can be FIG: 8.9 Parallel in serial out shift Register

4 8.2.5 Parallel in parallel out Shift Register In parallel in parallel out shift register all data bits appears on the parallel output. When ever the clock pulse is applied all the four bit input data is appeared at the output.d0, D1,D2, D3 are the parallel inputs. Q0, Q1, Q2, Q3 are the parallel output. The parallel in parallel out shift register is shown in fig. Q0 Q1 Q2 Q3 FF0 FF1 FF2 FF3 D0 Q D1 Q D2 Q D3 Q CLK CLK CLK CLK CLR Q CLR Q CLR Q CLR Q Clock FIG : 8.10 Parallel in parallel out shift Register Clear 8.3 Counters Counter is sequential circuit which count the binary values either in increment or decrement order. After a maximum count, the value resets once again to its initial value. Counters are fundamental components of digital system. It has wide applications like pulse counting, frequency division, time measurement and control and timing operations Classification of counters The counters is classified into three categories (i) Asynchronous and synchronous counters. (ii) Single and multi mode counters. (iii) Modulus counters. Asynchronous and synchronous counter: In asynchronous counter, each flip flop is triggered by the output from the previous flip flop. The settling time of asynchronous counter is the cumulative sum of individual flip flops In synchronous counter, the clock pulse is applied simultaneously to all flip flops. The settling time is equal to the propagation delay of individual flip flop.

5 Single and multi mode counters The single mode counter, the counter operates in single mode, i.e it counts either in UP or DOWN mode. Counter counts from zero to a maximum count is called UP count. Counter counts from a maximum count down to zero is called DOWN counter. In Multi mode counter it counts in both UP and DOWN mode. Modulus counter The number of state through which the counter passes is called as modulo, for instance n flip flops will have 2 n states and hence this type arrangement is called as 2 n modulo. 8.4 SYNCHRONOUS COUNTERS In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0 are connected to HIGH. The JK flip flop toggles when both input are high. FF1 has its J and K Fig : bit Synchronous counter inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the Table: 8.1 States of Flip flop output of an AND gate that is fed by the outputs of FF0 and FF1.Pay attention to what happens after the 3 rd clock pulse. Both outputs of FF0 and FF1 are HIGH. The positive edge of the 4 th clock pulse will cause FF2 to change its state due to the AND gate. The count sequence for the 3-bit counter is shown. The most important advantage of synchronous counters is that there is no cumulative time delay because all flip-flops are triggered in parallel. Thus, the maximum operating frequency for this counter will be significantly higher than for the corresponding ripple counter.

6 8.5 SYNCHRONOUS - DECADE COUNTERS A synchronous decade counter counts from 0 to 9 and then recycles to 0 again. This is done by forcing the 1010 state back to the Table: 8.2 State table 0000 state. This so called truncated sequence can be constructed by the following circuit. Fig :8.12 Synchronous Decade counter From the sequence on the left, we notice that: Q0 toggles on each clock pulse. Q1 changes on the next clock pulse each time Q0=1 and Q3=0. Q2 changes on the next clock pulse each time Q0=Q1=1. Q3 changes on the next clock pulse each time Q0=1, Q1=1 and Q2=1 (count 7), or when Q0=1 and Q3=1 (count 9). These characteristics are implemented with the AND/OR logic connected as shown in the logic diagram SYNCHRONOUS - UP-DOWN COUNTER FIG : 8.13 Synchronous UP/DOWN counter

7 A circuit of a 3-bit synchronous up-down counter and a table of its sequence are shown below. A synchronous up-down counter also has an up-down control input. It is used to control the direction of the counter through a certain sequence. Table: 8.3 State Table For both UP and DOWN sequences, Q0 toggles on each clock pulse. For the UP sequence, Q1 changes state on the next clock pulse when Q0=1. For the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0. For the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1. For the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0.These characteristics are implemented with the AND, OR & NOT logic connected as shown in the logic diagram above Design of synchronous counter Example :1 Design of MOD -3 Counters The MOD-3 counter consists of three states. It counts from 000 to 010. To design a counter with three state, the number flip flop required is 2 n 1 m 2 n. Here n is number of flip flop and m is the number of flip flop. If n=2 then we can get four states. Assume MOD-3 counter has three states a,b,c and its sequence is given by Step:1 Draw the state transition diagram a c b Fig 8.14 State diagram for MOD-3 counter

8 Step 2: Draw the state transition table Table: 8.4 State Transition table Present state Next state a b b c c a Step 3: State assignment Assign the binary values to the three states a= 00,b =01,c=10. Table :8.5 state assignment table Present state q1 q0 Next state Q1 Q Step 4: Excitation table JK flip flop is used for synchronous design for simplified circuit. Table : 8.6 Excitation Table Present state Next state Excitation inputs q1 q0 Q1 Q0 J1 K1 J0 K x 1 x x x x 1 0 x In first row present state q1 to next state Q1 has 0 0 transition which requires J1=0 and K1=x, q0 to Q0 has 0 1 transition which requires J0=1 and K0=x.

9 Step 5: Excitation map. Draw the excitation map for J1,K1,J0,K0 q0 q x x (a) J1 q0 q x x 1 x (b) K1 q0 q1 0 1 q0 q x 0 x x 1 x x (c) J0 (d) K0 Fig Excitation map for J1,K1,J0,K0 The simplified excitation functions are J1=q0 K1=1 J0= q 1 K0=1 Step 6: schematic diagram Q0(LSB) Q1(MSB) +5V +5V clock FIG.15 Circuit diagram for MOD-3 synchronous counter

10 Example 2: Design of BCD or MOD-10 counter. To design a BCD counter with 10 states four flip flops are required. The four flip flop has 16 states, the remaining states are consider as don t care.assume the 10 states for MOD -10 counter are a,b,c,d,e,f,g,h,i,j. Step:1 Draw the state transition diagram Fig 8.16 state diagram for MOD-10 Counter Step 2: Draw the state transition table Table : 8.7 State transition table Present state Next state a b b c c d d e e f f g g h h i i j j a

11 Step 3: State assignment Assign the binary values to the three states a= 0000,b =0001,c=0010,d=0011,e=0100,f=.0101,g=0110,h=0111,i=1000,j=1001 Table : 8.8 State assignment table Present state q3 q2 q1 q0 Next state Q3 Q2 Q1Q Step 4: Excitation table JK flip flop is used for synchronous design for simplified circuit. Table :8.9 Excitation table Present state q3 q2 q1 q0 Next state Q3 Q2 Q1Q0 Excitation inputs J3 K3 J2 K2 J1 K1 J0 K x 0 x 0 x 1 x x 0 x 1 x x x 0 x x 0 1 x x 1 x x 1 x x x 0 0 x 1 x x x 0 1 x x x x 0 x 0 1 x x x 1 x 1 x x 0 0 x 0 x 1 x x 1 0 x 0 x x x Step 5: Excitation map. Draw the excitation map for J1,K1,J0,K0

12 q1q0 q3q x x q3q2 q1q x x x x x 01 x x x x x 11 x x x x x x 10 x x x x (a) J3=q2q1q0 (b) k3=q0 q3q2 q1q x x 0 q3q2 q1q x 0 x x 01 0 x x 0 01 x 0 x x 11 1 x x x 11 x 1 x x 10 0 x x x 10 x 0 x x (c) J2=q1q0 (d) k2=q1q0 q3q2 q1q x 0 q3q2 q1q x x x x x 0 01 x x x x 11 x x x x x x 10 x x x x x x (e) J1= q 3q0 (f) k1=q0

13 q3q2 q1q x 1 01 x x x x 11 x x x x x x (g) J0=1 q3q2 q1q x x x x x x x 10 x x x x (h) K0=1 Step 6: schematic diagram for the Excitation map +5V Clock J0 Q0 J1 Q1 J2 Q2 J3 Q3 k0 Q 0 K1 Q1 K2 Q2 Q3 K3 J0 0 J0 J0 Q0(LSB) Q1 Q2 Q3(MSB) FIG 8.17 Circuit diagram for MOD-10 counter

14 8.6 HDL FOR SEQUENTIAL CIRCUIT. VHDL is an acronym which stands for VHSIC Hardware Description Language and VHSIC stands for Very High Speed Integrated Circuits. The acronym itself captures the entire theme of language and it describes the hardware in the same manner as does the schematic. VHDL is being used for documentation, verification, and synthesis of large digital designs. This key feature of the VHDL of the VHDL saves a lot design effort. Since the same VHDL code can theoretically achieve all three of these goals. In addition to being used for each of these purposes, VHDL can be used in three different approaches for describing the hardware. These three different approaches are the data flow, structural and behavioral methods of hardware description. A mixture of these three methods can also be employed to arrive at an efficient design. VHDL LIBRARIES The libraries can be declared in VHDL using two lines of code, one containing the name of the library and the other line containing a use clause as follows. library library_name; use library _name. package_name.all; At least three packages are usually needed in a design from three different libraries. They are (i) ieee.std_logic_1164 from the ieee library, (ii) standard from the std library and (iii) work from work library. The library declarations for the above three different packages are given as follows. use ieee.std_logic_1164.all; library std; use std.standard.all; library work; use work.all; The libraries std and work shown above are made visible by default, so there is no need to declare them; only the ieee library must be explicitly written. However, the latter is only necessary, when the std_logic(or std_ulogic) data type is employed in the design. The purpose of three packages/libraries mentioned above is the following: the std_logic_1164 package of the ieee library specifies a multi-level logic system; std is a resource library(data types, text i/o,etc) for the VHDL design environment; and the work

15 library is where the user designed programs are saved(the.vhd file, plus all files created by the compiler, simulator, etc.). The ieee library contains several packages, including the following; std_logic_1164: specifies the std_logic (8 levels) and std ulogic (9 levels) multi-valued logic systems. The 8 levels of std_logic are: X, - Forcing Unknown, 0, - Forcing 0, 1, - Forcing 1, Z, - High Impedance, W, - Weak Unknown, L, - Weak 0, H, - Weak 1 and - - Don t care. The 9 levels of std_ulogic are: U, - Uninitialized plus the 8 of std_logic. Std_logic_arith: specifies the SIGNED and UNSIGNED data types and related arithmetic and comparison operations. It also contains several data conversion functions, which allow one type to be converted into another: conv_integer(p), conv_unsigned(p,b), conv_signed (p,b), conv_std_logic_vector(p,b). Std_logic_signed: contains functions that allow operations with std_logic_vector data to be performed as if the data were of type SIGNED. Std_logic_unsigned : contains functions that allow operations with std_logic_vector data to be performed as is the data were of type UNSIGNED. HDL FOR SEQUENTIAL LOGIC CIRCUITS Realization of flip-flops SR- Flip-Flop: The VHDL program for the SR-Flip-Flop can be written as follows. This program follows data flow approach. use ieee.std_logic_1164.all; entity srff1 is - Declaration of entity port(s,r: in std_logic;q,nq:inout std_logic) Set of i/p & o/p in declaration end srff1; - End of entity declaration architecture srff_arch of srff1 is Q<=R nor NQ; NQ<= S nor Q; Clocked SR Flip-Flop: The VHDL program for the clocked SR flip-flop cab be written as follows. This program follows structural approach. use ieee.std_logic_1164.all;

16 entity clksr is port(s,r,clk:in std_logic; M,N:inout std_logic; Q,NQ:inout std_logic); end clksr; architechture clksr_arch of clksr is component srff1 is port(s,r:in std_logic; Q,NQ:inout std_logic); end component; M<=S and Clk; - AND logic operation S with CLK N<=R and Clk; - AND logic operation R with CLK al:srff1 port map(m,n,q,nq) - SR FF component is used at - instance al D- Flip-Flop: The VHDL program for the D- Flip-Flop can be written as follows. This program follows behavioral approach. use ieee.std_logic_1164.all; entity dfff1 is port(d, CLK, reset:in std_logic; Q:out std_logic); end dfff1; architechture arch_dflipflop of dfff1 is process(clk) if(clk event cnd CLK= 1 )then - CLK =1: if reset = 0 then - Reset=0 implies q=0 Q<= 0 ; - Reset=1 implies q=d Else Q<=D; endif; endif; end process;

17 JK- Flip-Flop: The VHDL program for the JK- flip flop can be written as follows. This program follows behavioral approach. use ieee.std_logic_1164.all; entity jkff1 is port(j,k, CLK:in std_logic;; Q,NQ:inout std_logic); end jkff1; architechture jkff_arch of jkff1 is process(clk,j,k) if(clk= 1 and CLK event) then if(j= 0 and K= 0 )then Q<=Q; NQ<=NQ; elsif(j= 1 and K= 0 )then Q<= 1 ; NQ<= 0 ; elsif(j= 0 and K= 1 )then Q<= 0 ; NQ<= 1 ; elsif(j= 1 and K= 1 )then Q<=not Q; NQ<=not NQ; end if; end if; end process; T- Flip-Flop: The VHDL program for the T- flip flop can be written as follows. This program follows behavioral approach. use ieee.std_logic_1164.all; entity tff1 is port(t, CLK:in std_logic;; Q,NQ:inout std_logic);

18 end tff1; architechture arch_tff of tff1 is process(clk,t) if(clk= 1 and CLK event) then if(t= 1 )then Q<=not Q; NQ<=not(Q)after 0.5 ns; else Q<=Q; NQ<=not(Q)after 0.5 ns; end if; end if; end process; 4-bit Serial in Serial out Shift Register: The VHDL program for the 4-bit Serial in Serial out Shift Register can be written as follows. This program follows structural approach. When a clock pulse is applied, output of one flip-flop is given as input of the next flip-flop. The serial output is taken from the last flip-flop. use ieee.std_logic_1164.all; entity siso is port(d:instd_logic: reset, CLK:in std_logic; Q:out std_logic); end siso; Architechture arch_siso of siso is signal QA,QB,QC,QD: std_logic; component dff1 is port(d,clk,reset: in std_logic; Q: out std_logic); end component; a1: dff port map(d,clk,reset,qa); a2: dff port map(qa,clk,reset,qb); a3: dff port map(qb,clk,reset,qc); a4: dff port map(qc,clk,reset,qd); - D flip-flop program is used as component

19 4-bit Serial in Parallel out Shift Register: The VHDL program for the 4-bit Serial in Parallel out Shift Register can be written as follows. This program follows behavioral approach. When the clock pulse is applied, output of one flip-flop is given as input of the next one and the output is obtained from all the flip-flops. use ieee.std_logic_1164.all; use ieee.std_logic _unsigned.all; entity shiftreg is port(clk,reset,enable:instd_logic;shiftedop:out std_logic_vector(3 downto 0)); end shiftreg; Architecture arch_shiftreg of shiftreg is signal a:std_logic_vector(3 down to 0); process(clk,reset) if reset= 0 then a<=(others=> 0 ); - signal a is cleared, i.e, a=0000 elsifclk event and CLK= 1 then if enable= 1 then a<=sh1(a, 1 ); - shift left a by one bit a(0)<=d; endif; endif; end process; shiftedop<=a; 4-bit Parallel in Serial out Shift Register: The VHDL program for the 4-bit Parallel in Serial out Shift Register using behavioral approach can be written as follows. use ieee.std_logic_1164.all; use ieee.std_logic _unsigned.all; entity dpiso is port(clk,load:instd_logic;d:in std_logic_vector(3 downto 0)); dout:out std_logic; end dpiso; Architecture arch_dpiso of dpiso is signal reg:std_logic_vector(3 down to 0);

20 process(clk) if(clk event and CLK= 1 ) then if(load= 1 )then reg<=d; else reg<=reg(2 downto 0) & 0 ; endif; endif; end process; dout<=reg(3); 4-bit Parallel in Parallel out Shift Register: The VHDL program for the 4-bit Parallel in Parallel out Shift Register can be written as follows. This program follows structural approach. use ieee.std_logic_1164.all; entity pipo is port(d:instd_logic_vector(0 to 3); reset,clk:in std_logic; Q:out std_logic_vector(0 to 3)); end pipo; Architechture arch_pipo of pipo is component dff1 is port(d,clk,reset: in std_logic; Q: out std_logic); end component; a1: dff1 port map(d(0),clk,reset,q(0)); - Delay FF component is used at a2: dff1 port map(d(1),clk,reset,q(1)); a3: dff1 port map(d(2),clk,reset,q(2)); a4: dff1 port map(d(3),clk,reset,q(3)); 4-bit Synchronous Binary Counter: The VHDL program for the 4-bit Synchronous Binary Counter can be written as follows. This program follows structural approach. use ieee.std_logic_164.all; entity binarycounter is

21 port(vcc,clk:in std_logic_vector(0 to 3)); end binary counter; architecture arch_binarycounter of binarycounter is signal X1,Y1:std_logic; component jkff1 is port(j,k,clk: in std_logic;q,nq:inout std_logic); end component; component andgate is port(a,b:in std_logic;y:out std_logic); end component; component andgates is port(a,b,c:in std_logic;y:out std_logic); end component; a: jkff1 port map(vcc,vcc,clk,q(0),nq(0)); b: jkff1 port map(q(0),q(0),clk,q(1),nq(1)); c: abdgate port map(q(1),q(0),x1); d: jkff1 port map(x1,x1,clk,q(2),nq(2)); f: andgates port map(q(0),q(1),q(2),y1); e: jkff1 port map(y1,y!,clk,q(3),nq(3)); 3-bit Synchronous Up/Down Counter: The VHDL program for the 3-bit Synchronous Up/Down counter can be written as follows. This program follows structural approach. use ieee.std_logic_164.all; entity updowncounter is port(vcc,up,clk:in std_logic; Q,NQ:inout std_logic_vector(0 to 2)); end updowncounter; architecture arch_updowncounter of updowncounter is signal X1,Y1,Z1,A1,B1,C1,D1:std_logic; component jkff1 is port(j,k,clk: in std_logic;q,nq:inout std_logic); end component;

22 component andgate is port(a,b:in std_logic;y:out std_logic); end component; component notgate is port(a:in std_logic;y:out std_logic); end component; component orgate is port(a,b:in std_logic;y:out std_logic); end component; ff1: jkff1 port map(vcc,vcc,clk,q(0),nq(0)); ag1: andgate port map(q(0),up,x1); ng1: notgate port map(up,y1); - Up control i/p is inverted to get ag2: andgate port map(nq(0),y1,z1); - Down (active low) og1: orgate port map(x1,z1,a1); ff2: jkff1 port map(a1,a1,clk,q(1),nq(1)); ag3: andgate port map(q(1),x1,b1); ag4: andgate port map(z1,nq(1),c1); og2: orgate port map(b1,c1,d1); 4-bit Ring Counter: The VHDL program for the 4-bit ring counter can be written using the behavioral approach. use ieee.std_logic_164.all; entity ringcount is port(clk,clr:in std_logic; Q:inout std_logic_vector(0 to 3)); end ringcount; architecture rincountarch of ringcount is process(clk,clr) if (CLR= 0 )then Q<= 1000 ;

23 elsif(clr= 1 ) then if(clk= 1 )and CLK event then Q(0)<=Q(3); for I in 0 to 2 loop Q(i+1)<=Q(i); end loop; endif; endif; end process; end ringcountarch; 4-bit Johnson Counter: The following is D-flip-flop program that follows behavioral approach and is used as component in Johnson Counter. use ieee.std_logic_1164.all; entity dff2 is port(d, CLK, reset:in std_logic; Q,NQ:out std_logic); end dff2; architechture arch_dflipflop of dff2 is process(clk) if(clk event cnd CLK= 1 )then - CLK =1: if reset = 0 then - Reset=0 implies q=0 Q<= 0 ; - Reset=1 implies q=d else Q<=D; NQ<=not(Q); endif; endif; end process; The VHDL program for the 4-bit Johnson Counter can be written as follows that uses the above D-flip-flop program as component. entity Johnson is port(clk,reset:in std_logic;

24 Q,NQ:inout std_logic_vector(0 to 3)); end Johnson; architecture arch_johnson of Johnson is component dff2 is port(d,clk,reset:in std_logic; Q,NQ:inout std_logic); end component; a: dff2 port map(nq(3),clk,reset,q(0),nq(0)); b: dff2 port map(q(0),clk,reset,q(1),nq(1)); c: dff2 port map(q(1),clk,reset,q(2),nq(2)); d: dff2 port map(q(2),clk,reset,q(3),nq(3)); Summary A register is group of flip flop can store one bit information. Shift registers are used in parallel to serial and serial to parallel conversion, Successive approximation type A/D converters, Sequence generators. In n bit shift register n flop flops are required. The primary function of counter is to count binary bits in a pre defined sequence using any types of flip flop. Counter is a sequential circuit and it can be developed by flip flops. Generally counter has 2 n counter states. Where n is the number of flip flops used in the counter. Counter of any value can be designed by skipping some states from the natural value. For this feedback signals are taken from some flip flops and then reset or clear all flip flops. Counters are classified into synchronous and asynchronous counters Review questions 1. What is shift register? What are the types of shift register? 2. Write the applications of shift register. 3. Design a synchronous binary counter using T flip flop. 4. Discuss a decade counter and its working principle. 5. Design a counter with the following repeated binary sequence 0,1,2,3,4,5,6. Use JK flip flop. 6. Write a HDL program for synchronous counter