Class 19 Sequential Logic: Flip-Flop
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1 Class 9 Sequential Logic: Flip-Flop June 2, 22 2 Differences between Latch and Flip-Flop D latch Level trigger D flip-flop Edge trigger
2 June 2, 22 3 Function Table of D Flip-Flop DFF CLK D D flip-flop Edge trigger + + Function Reset Set Function table of D flip-flop June 2, 22 4 JK Flip-Flop JKFF SR NAND Latch Gated SR NAND Latch JK flip-flop CLK J K + + Function No Change Reset Set Toggle Function table of JK flip-flop 2
3 June 2, 22 5 Frequency Divider or Counter Clock Pulse Q 2 Q Q June 2, 22 6 JK Flip-Flop with Asynchronous Inputs Second priority First priority Sync Async npre nclr CLK J K + + Function No Change Reset Set Toggle Preset Clear Forbidden 3
4 June 2, 22 T Flip-Flop D flip-flop with an OR at the input T flip-flop: the output oggles on each clock pulse when T is high CLK T + Function No change Toggle Function table of T flip-flop June 2, 22 8 Integer vs. Unsigned STD_LOGIC USE ieee.std_logic_64.all; ENTITY compare4 IS PORT( a, b : IN INTEGER RANGE TO 5; agtb, aeqb, altb : OUT STD_LOGIC); END compare4; ARCHITECTURE a OF compare4 IS SIGNAL compare : STD_LOGIC_VECTOR(2 downto ); PROCESS (a,b) IF a<b THEN compare <= ""; ELSIF a=b THEN compare <= ""; ELSIF a>b THEN compare <= ""; ELSE compare <= ""; agtb <= compare(2); aeqb <= compare(); altb <= compare(); END PROCESS; END a; USE ieee.std_logic_64.all; USE ieee.std_logic_unsigned.all; ENTITY compare4 IS PORT( a, b : IN STD_LOGIC_VECTOR (3 downto ); agtb, aeqb, altb : OUT STD_LOGIC); END compare4; ARCHITECTURE a OF compare4 IS SIGNAL compare : STD_LOGIC_VECTOR(2 downto ); PROCESS (a,b) IF a<b THEN compare <= ""; ELSIF a=b THEN compare <= ""; ELSIF a>b THEN compare <= ""; ELSE compare <= ""; agtb <= compare(2); aeqb <= compare(); altb <= compare(); END PROCESS; END a; 4
5 June 2, 22 9 Signal Attributes and Edges Attribues of Signal p[..] Description Upper bound of p Lower bound of p Left bound of p Right bound of p Attribute p HIGH p LOW p LEFT p RIGHT p LENGTH Length of p Value 8 Q EVENT and Q= ) FALLING_EDGE(Q) Q Q Q EVENT and Q= ) RISING_EDGE(Q) June 2, 22 Signal Attributes and Constant with Default Value USE ieee.std_logic_64.all; ENTITY parity_genx IS PORT( pe: OUT STD_LOGIC); END parity_genx; ARCHITECTURE parity OF parity_genx IS CONSTANT width: INTEGER := 8; SIGNAL d: STD_LOGIC_VECTOR( to width-); SIGNAL p : STD_LOGIC_VECTOR(d'LOW+ to d'high); p() <= d() xor d(); parity_generate: FOR i IN d'left+2 to d'right GENERATE p(i) <= p(i-) xor d(i); END GENERATE; pe <= p(d LENGTH-); END parity; Constant value +2=2 8-= Default value 8-= 5
6 June 2, 22 Frequency Divider USE ieee.std_logic_64.all; ENTITY FrequencyDivider IS Map to external 5MHz clock PORT ( CLK: IN STD_LOGIC; LED: OUT STD_LOGIC); END FrequencyDivider; ARCHITECTURE a OF FrequencyDivider IS Imported from COMPONENT jkff_primitive jkff_primitive.bdf PORT ( of the same project CLK: IN STD_LOGIC; Q: OUT STD_LOGIC); END COMPONENT; SIGNAL Q: STD_LOGIC_VECTOR(25 downto ); JKFF PRN J INPUT OUTPUT VCC J Q Q CLK INPUT VCC K INPUT VCC K CLRN inst The procedure to import a.bdf design into a VHDL file:. Create a jkff_primitive.bdf file, and add a JKFF component into this file. 2. Create input and output pins for this JKFF component. 3. In the VHDL file, declare the jkff_primitive as its component with only the in/out pins that it wants to use. 4. Generate this component in this VHDL file. -- Frequency Divider Q(Q'LOW) <= CLK; 25 divider: FOR i IN Q'LOW+ to Q'HIGH GENERATE divider_unit: jkff_primitive PORT MAP(CLK=>Q(i-), Q=>Q(i)); END GENERATE; LED <= not Q(Q'HIGH); END a; Turn the LED on/off every.32s s / (5MHz / 2 24 ) Generate 25 JK flip-flops June 2, 22 2 FOR Loop and Array USE ieee.std_logic_64.all; ENTITY FrequencyDivider IS PORT (Hex, Hex, Hex2, Hex3: OUT STD_LOGIC_VECTOR( to )); END FrequencyDivider; ARCHITECTURE a OF FrequencyDivider IS CONSTANT DigitValue: INTEGER := 6; TYPE MMSS is array ( to 3) of INTEGER RANGE to DigitValue; SIGNAL digits: MMSS; TYPE SEVENSEGMENT is array ( to 3) of STD_LOGIC_VECTOR( to ); SIGNAL segments: SEVENSEGMENT; -- show -segment Hex <= segments(); Hex <= segments(); Hex2 <= segments(2); Hex3 <= segments(3); Define an STD_LOGIC_VECTOR array Map signal to port Constant with default value 6 Define an integer array Light on dot of HE2 hexadecimal Note: = x A8 = o 53 = b binary octal PROCESS(all) FOR i IN to 3 LOOP CASE digits(i) IS WHEN => segments(i)<=""; -- WHEN => segments(i)<=""; -- WHEN 2=> segments(i)<=" ; -- 2 WHEN 3=> segments(i)<=""; -- 3 WHEN 4=> segments(i)<=""; -- 4 WHEN 5=> segments(i)<=""; -- 5 WHEN 6=> segments(i)<=""; -- 6 WHEN => segments(i)<=""; -- WHEN 8=> segments(i)<=""; -- 8 WHEN 9=> segments(i)<=""; -- 9 WHEN others =>segments(i)<=""; END CASE; END LOOP; segments(2)() <= ''; -- display "dot" END PROCESS; END a; 6
7 Hint: digits() <= digit mod ; digits() <= (digit/) mod ; digits(2) <= (digit/) mod ; digits(3) <= (digit/) mod ; PROCESS(CLK) IF(RISING_EDGE(CLK)) THEN Ticks <= Ticks + ; Function IF(Ticks >= TenMiniSecondTicks-) THEN Ticks <= ; digit <= digit + ; USE ieee.std_logic_64.all; END PROCESS; ENTITY FrequencyDivider IS PORT (CLK: IN STD_LOGIC; Hex, Hex, Hex2, Hex3: OUT STD_LOGIC_VECTOR( to )); END FrequencyDivider; ARCHITECTURE a OF FrequencyDivider IS SIGNAL Ticks : INTEGER; TYPE MMSS is array ( to 3) of INTEGER RANGE to 6; SIGNAL TenMiniSecondTicks: INTEGER := 5; SIGNAL digits: MMSS; SIGNAL digit; Function name FUNCTION PlusOne (a:integer RANGE to 6) RETURN INTEGER IS VARIABLE result : INTEGER RANGE to 6; result := a + ; RETURN (result); END; Return value Parameters (separated by ;) Variable (SIGNAL is not allowed in functions) Value assignment to variable should use := Return value type -- Stopwatch PROCESS(CLK) IF(RISING_EDGE(CLK)) THEN Ticks <= Ticks + ; IF(Ticks >= TenMiniSecondTicks-) THEN Ticks <= ; digits() <= PlusOne(digits()); IF(digits()>=9) THEN digits() <= PlusOne(digits()); digits() <= ; IF(digits()>=9) THEN digits(2) <= PlusOne(digits(2)); digits() <= ; IF(digits(2)>=9) THEN digits(3) <= PlusOne(digits(3)); digits(2) <= ; IF(digits(3)>=9) THEN digits(3) <= ; Function call END PROCESS; END a; June 2, 22 3 Remember to USE ieee_std_logic_arith.all; Exercise: Try to use one integer instead of an integer array (i.e., 4 intergers). June 2, 22 4 DE External Clock
8 June 2, 22 5 Lab 9 Part : Frequency Divider with JK flip-flops or T flipflops Design a flashing light array with the 5MHz clock - LEDG[..9] is toggled every 2 [25..34] clock ticks, respectively. - E.g., LEDG is toggled with.49hz, LEDG is toggled with.45hz, and so on. Part 2: Design a clock Design a clock with four digits. - HE[32] represents MM.SS (MM: minutes, SS: seconds), where the dot between MM and SS should be always on. - Set the initial time to June 2, 22 6 DE External Clock 8
9 June 2, 22 Pushbutton and Slide Switches Pin number Pin number 3 Pushbutton switches: Not pressed Logic High Pressed Logic Low Slide switches (Sliders): Up Logic High Down Logic June 2, 22 8 LEDs Pin number LEDs Opuput high LED on Output low LED off 9
10 June 2, Segment Displays Pin number (active-low)
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