D U I S B U R G E S S E N

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1 Notes on the lecture Fundamentals of Computer Engineering (Prof. Dr.-Ing. xel Hunger) UNIVERSITÄT D U I S U R G E S S E N Institute for Multimedia & Software Engineering, Dipl.-Ing. Sascha Mertens, October 23

2 Contents Contents Contents... Switching lgebra... 5 Introduction... 5 Definition... 5 asic Set... 6 Logical Expressions... 7 oolean Operators... 7 Conjunction (ND operation)... 7 Disjunction (OR operation)... 7 xioms... 7 Commutativity (xiom )... 7 ssociative Law (xiom 2)... 8 Distributive Law (xiom 3)... 8 Identity (xiom 4)... 8 Complementation (xiom 5)... 9 Theorems... 9 Null Law (Theorem )... 9 Involution (Theorem 2)... Idempotency (Theorem 3)... bsorption (Theorem 4)... Simplifications (Theorems 5-8)... De Morgan's law (Theorem 9)... Shannon's law (Theorem )...2 Logical Functions...3 Canonical forms...3 Literals...3 Minterm...3 Maxterm...3 Sum-of-products (SOP)...3 Product-of-sums (POS)...3 Disjunctive Normal Form (DNF)...4 Conjunctive Normal Form (CNF)...4 Logical Functions...4 Notes on Fundamentals of Computer Engineering

3 Contents Truth Tables...4 Don t care states...5 Truth tables and DNF/CNF...5 Fundamental logical functions...7 Signs for logical functions...8 Gates...8 Complete logic gate sets...9 Complete logic gate set with NND gates...2 Complete logic sets with NOR gates...2 Realizing circuits with complete gate sets...2 Logical Levels, Timing & Delays Logical levels...23 Different interpretations...23 Positive and negative logic...23 Ranges for logical values...24 Timing diagrams (Impulse diagrams)...25 Propagation delay...26 Propagation delays of combinational circuits...27 Hazards...29 Using hazards...3 Karnaugh-Veitch-Maps Simplification of logical functions...32 Structure of KV-Maps...33 How to draw a KV-Map...33 Logical functions in a KV-Map...35 Minimisation with KV Maps...38 Minimising across the borders...4 KV-Maps and Don t cares...4 Product-of-Sums and KV-Maps...42 Number Representation Introduction...44 Positional Number Systems...44 Conversion from decimal to any system: Horner lgorithm...48 inary Representation of signed numbers...5 Word Length & Ranges...5 Notes on Fundamentals of Computer Engineering 2

4 Contents Sign-Magnitude Representation...5 Two s Complement...52 Misinterpretation of inary Numbers...54 Fixed-length format for Decimal Fractions...54 Floating Point Numbers...55 IEEE Floating Point Numbers...56 inary rithmetic... 6 inary ddition of unsigned numbers...6 Overflow...6 inary Subtraction of unsigned numbers...6 ddition and Subtraction of signed numbers...6 Examples...62 inary Multiplication...64 inary Multiplication of Signed Numbers...65 Combinational Circuit Design Introduction...66 Design of combinational circuits in 3 steps...66 Design examples asic combinational circuits...68 Code Converter...68 Multiplexer...7 Demulitplexer...7 Half dder...72 Full dder...73 Parallel dder...74 Flip-Flops Sequential Circuits vs. Combinational Circuits...75 Sequential Circuits and Flip-Flops...75 The roots: Set-Reset Flip-Flop (SR flip-flop)...76 Clocked Flip-Flops...77 Different Types Of Clock Inputs...78 Jump-and-Kill Flip-Flop (JK Flip-Flop)...79 Delay Flip-Flop (D flip-flop)...8 Trigger Flip-Flops (T Flip-Flops)...8 synchronous Set and Reset...8 Notes on Fundamentals of Computer Engineering 3

5 Contents asic Sequential Circuits Introduction...83 Counters...83 synchronous Counter...83 Synchronous Counters...85 Counting any Sequence - Counter Design...85 Registers...87 Shift Registers...87 Cyclic Registers...88 Parallel In Serial Out...88 Serial dder...89 Finite State Machines (utomata)...9 Introduction What is a Finite State Machine?...9 Mealy and Moore Machines...9 The Moore Machine...9 The Mealy Machine...92 State Graphs...92 Transitions in State Graphs...93 State Graphs for Moore Machines...93 State Graphs for Mealy Machines...94 State Tables...95 Machines and Flip-Flops...96 Synthesizing a Finite State Machine...97 Notes on Fundamentals of Computer Engineering 4

6 Switching lgebra Definition Switching lgebra Introduction s modern as computers seem to be as old is the theory we use to built them logic was invented more than 2 years ago. In this time the famous greek philosopher ristotle was not only looking for truth but was trying to develop a method of finding it. He introduced the categorical logic as formal rules for the correct reasoning. The core idea is that every statement (predicate) is either true or false 2. ristotle than put up a formalism for defining rules to deduct the truth of a statement out of the truth of some premises,c,d. This formalism is still in use in the philosophic world as well as in artificial intelligence research (e.g. Prolog). In the 9 th century the british mathematician George oole (inspired by works of Lull, Hobbes, Leibniz and other thinkers) found a way to express ristotle s formalism as an algebra that is in the form of mathematical equations. oole introduced the two basic logic operators ND and OR to built complex logical statements out of simple statements. Even though, the mathematical concepts for oolean lgebra is not the direct result of oole s work but a consecutive development by mathematicians like E. Huntington. Nevertheless, nowadays most people say oolean lgebra when they refer to oole s concepts. The turn to engineering was made in 938, when Claude Shannon was working on the switched networks of the ell telephone company (and we are talking of real switches here). Shannon demonstrated that oole s way to handle complex statements that are either true or false can perfectly be used to describe the functionality of networks of switches that are either open or closed. Since than, switches have become much smaller, but Shannon s Switching lgebra is still the major language to describe the behaviour of digital systems i.e. electrical networks where (current or voltage ) is switched between two definite levels. Definition ny lgebra in general consists of a set of elements operations that can be used on the elements a neutral element for every operation Truth finding for greek philosophers quite often meant, that true was what the most eloquent of them could convice the others to believ, i.e. the border between philosophers and sophists were very thin 2 Sounding simple there were raging battles on this matter. The idea of declaring statements as nearly true or somehow false led to the development of fuzzy logic. Notes on Fundamentals of Computer Engineering 5

7 Switching lgebra asic Set a number of axioms the set and the operations have to satisfy Moreover for every lgebra there is a set of fundamental theorems, that can be derived from the axioms. The Switching lgebra consists of the basic set = {, } the disjunction + (OR) the conjunction (ND) the neutral elements and and satisfies the axioms of commutativity associativity distributivity identity complementation From this definition can be derived the following theorems: null law involution idempotency absorption simplification Now let's have a closer look at this definition. asic Set To clarify the idea of the Switching lgebra we go back to its roots - switches. If is a variable of a Switching lgebra, it can be or. Let therefore be represented by a switch. = might equal to a closed switch so a current can flow through it and = is an open switch that cuts the circuit. This assignment is a possibility, it can equally be chosen the other way round. Important is, that for a closed system, the interpretation must always be the same. =: I =: Notes on Fundamentals of Computer Engineering 6

8 Switching lgebra xioms Logical Expressions logical expression is a combination of one or more elements. To combine them, the operators + (OR) or (ND) are used. s the lgebra is closed, the operators used on two elements and of the basic set will yield a result C that is member of the basic set again. Clearly spoken: we will get either one or zero, a network of switches will at any time either act like an open or like a closed switch and a composed logical statement is either true or false. Sounds logical, does it? Logical expressions are also called oolean or switching expressions. oolean Operators Conjunction (ND operation) The conjunction is also called ND operator. Thus the operation yields only if is ND is. network described by is a series of two switches, where a current only can flow if both are closed. Usually the sign is omitted when writing down expressions: = : Disjunction (OR operation) The disjunction + is called OR operator. It yields as soon as is OR is. Thus it is equivalent to two parallel switches where a current can flow if one of them (or both) are closed. + : xioms Commutativity (xiom ) oth operators of Switching lgebra are commutative: + = + = Notes on Fundamentals of Computer Engineering 7

9 Switching lgebra xioms = ssociative Law (xiom 2) = oth operators of Switching lgebra are associative: + + C = ( + ) + C = + ( + C) = C = C C C = (C) = ()C Distributive Law (xiom 3) C If the operators are combined in one expression they satisfy the axiom of distributivity: ( + C ) = + C = C C +C = (+)(+C) C = C Identity (xiom 4) Each operator has an identity element also called neutral element. With a basic set of only two elements we do not have much of a choice, so: Notes on Fundamentals of Computer Engineering 8

10 Switching lgebra Theorems + = = = I = Complementation (xiom 5) For every element of the basic set there exists its complement also called its inverse element or its negation. s must be different from we end up with the smart statement, that is the complement of. n element combined with its complement yields a neutral element: + = I = = Even though it is not correct in the strictly mathematical sense, the complement can be understood as the result of an operation called NOT : NOT ()= Theorems Even though some of the theorems look like very basic rules, all of them can be concluded from the axioms. Null Law (Theorem ) ny neutral element used with the "other" operator (to which it is not the neutral element) cancels out the variable (compare with xiom 4 and see the difference): Notes on Fundamentals of Computer Engineering 9

11 Switching lgebra Theorems + = = I I = = Involution (Theorem 2) The complement of an element's complement is the original element again: Idempotency (Theorem 3) = n element combined with itself yields itself (mark the difference to e.g. the algebra of natural numbers where + = 2. In logic it s different) : + = = = bsorption (Theorem 4) = ( + ) = = Notes on Fundamentals of Computer Engineering

12 Switching lgebra Theorems + = = Simplifications (Theorems 5-8) + = = ( + )( + ) = = ( + ) = = + = + = De Morgan's law (Theorem 9) The negation of a term only containing one kind of operators can be transformed as follows: ( C D...) = + + C + D +... ( + + C+ D+...) = C D... Notes on Fundamentals of Computer Engineering

13 Switching lgebra Theorems Shannon's law (Theorem ) Shannon found a more general version of De Morgan's law that is valid for whole expressions containing both operators: (,,,...,,,,..., +, ) = (,,,...,,,,..., +, ) = (,,,...,,,,..., +, ) f C C f C C f C C The negation of an expression can be built by inverting every single variable changing every + to and every to + changing every to and every to Example: ( + ) C+ = (( + ) C) + = (( ) + C) = ( + C) = C Keep a good eye on the terms order. Use brackets!!!! C + = ( C) + = ( + C) + C Notes on Fundamentals of Computer Engineering 2

14 Logical Functions Canonical forms Logical Functions Canonical forms Every switching expression can be written down in a canonical form. This is often useful during development. There are the two canonical forms: the disjunctive normal form (DNF) and conjunctive normal form (CNF). To understand these forms, we have to explain literals, Minterms and Maxterms first. Literals literal is either a variable or the complement of a variable. Minterm Minterm over n variables is a logical sum (disjunction) of exactly n literals with no repeated variables. With n variables we thus have 2 n possible Minterms. Example (n=3): C C C C C C C C Maxterm Maxterm over n variables is a logical product (conjunction) of exactly n literals with no repeated variables. With n variables we thus have 2 n possible Maxterms. Example (n=2): Sum-of-products (SOP) The sum-of-products is a regular form consisting of a sum of m terms, where every term is a product: f SOP = + C + C Product-of-sums (POS) The product-of-sums is a regular form consisting of a product of m terms, where every term is a sum: ( + C ) ( + + C) ( C ) f POS = + Notes on Fundamentals of Computer Engineering 3

15 Logical Functions Logical Functions Disjunctive Normal Form (DNF) The DNF is a sum of products (SOP) consisting only of Minterms. Therefore every variable must appear exactly once in each product. f DNF = C + C + C + C + C Conjunctive Normal Form (CNF) The CNF is the product of sums (POS) only containing Maxterms. Therefore every variable must appear exactly once in each sum. CNF ( ) ( ) ( ) f = + + C + + C + + C Logical Functions The most common way to work with logical expressions is to use them as functions. So they are nothing else than rules for getting one output value out of n input variables. In this way, the disjunction of two variables would be written f (, ) = +. part from logical expressions, functions can be expressed by truth tables. Truth Tables truth table lists the values of a logical function for all possible permutations of the input variables values. Therefore a truth table for a function with n variables has 2 n rows. Example: The truth table for the function f(,,c) = + C is C f(,,c) Table : Example for a truth table Notes on Fundamentals of Computer Engineering 4

16 Logical Functions Logical Functions Don t care states When designing logical circuits we will sometimes have the situation, that the output value is only specified for some of the possible input values. This case can happen in two basic cases: for some reason it is sure, that certain input combinations will not occur, so there is no need to specify the output all input combinations can happen but for some reason some of them can be disregarded Now, speaking of reality, no output is fine in mathematics, but a real circuit always has some output. The point is that for the two cases mentioned above we don t care about the value of these outputs. In a truth table, such input combinations are marked with an X. During the design process, it is possible to replace those Xs with s or s, just as it suits best (The handling of Don t cares will be explained more detailed in the section on KV-Maps). The function in Table 2 has Don t cares for (,) = (,) and (,)=(,). f(e,,) X Truth tables and DNF/CNF X Table 2: Logical Function with Don t Cares Every row in a truth table corresponds to a Minterm and to a Maxterm. In a Minterm mk, a truth table s zero corresponds to the variable s complement a truth table s one corresponds to the variable C C In a Maxterm Mk: a truth table s one corresponds to the variable s complement a truth table s zero corresponds to the variable Notes on Fundamentals of Computer Engineering 5

17 Logical Functions Logical Functions C + + C s you probably already recognized C = + + C, thus the Minterm for a certain row is the negation of the row s Maxterm (and vice versa) So where is the use in all this? Using Minterms or Maxterms is the fastest way to read a logical expression from a truth table! Consider the following table: C Minterms Maxterms f(,,c) Truth table DNF : C C C C C C C C + + C + + C + + C + + C + + C + + C + + C + + C Table 3: Truth table with min- and Maxterms Using Minterms, we can read the function s DNF directly from the table by building the Minterm for every row where the function is one summing up the Minterms The function for the example is therefore f (,, C) = C + C + C Truth table CNF: Using Maxterms, we can read the function s CNF directly from the table by building the Maxterm for every row where the function is zero multiplying the Maxterms The function for the example is therefore f (,, C ) = ( + + C )( + + C )( + + C )( + + C )( + + C ) Notes on Fundamentals of Computer Engineering 6

18 Logical Functions Logical Functions Fundamental logical functions When designing logic circuits everything can be broken down to functions of two variables. The following truth table lists all possible functions for two variables: f f2 f3 f4 f5 f6 f7 f8 f9 f f f2 f3 f4 f5 f6 Table 4: Truth table with all possible results of the logical combination of two variables These fundamental logical functions are: f = inary Zero f 2 = = + = NOT OR or NOR f f 3 5 = = Inhibition f = 4, f = 6 Negation, Inversion, Complement, NOT f 7 = + = Exclusive OR, XOR f8 = + = = NOT ND or NND f 9 = = ND, Conjunction f = + = Equivalence, Inclusive-OR, XNOR f =, f 3 = Identity, Tautology f = + 2, = f4 = + Implication, IF - THEN = f 5 = + OR, Disjunction f = 6 inary One Notes on Fundamentals of Computer Engineering 7

19 Logical Functions Gates Signs for logical functions There exist a lot of different signs to denote the same logical function. The most common are listed here: Function lgebra of sets lgebra of sentences Switching algebra DIN 66 Conjunction or & Disjunction + Negation, or Neutral Elements 3, Ø 4 w, f, Table 5: Signs for logical functions Gates more technically oriented representation of logical functions are symbols. s a function can be seen as a black box with several inputs and one or more outputs we can use boxes to describe the fundamental logical functions. If these boxes are built as electrical devices they are called gates (think of a system with running water and gates to block the water). The logical expressions built out of the basic functions are realized by connecting several gates to a logic circuit. The gates are represented by symbols. The most used symbols are those defined by the Deutsche Industrie Norm / International Electrotechnical Commission and those of the merican National Standards Institute /IEEE. 3 The whole asic Set, all possible elements (in oole s lgebra: the universe ) 4 The Empty set Notes on Fundamentals of Computer Engineering 8

20 Logical Functions Complete logic gate sets DIN / IEC NSI / IEEE Function ND & X = OR > X = + NOT X = NND & X = = NOR > X = + = ntivalence XOR Equivalence XNOR = X = + = = X = + = Table 6: The basic logical functions as Gates Usually the symbol for NOT is omitted if it is directly connected to the input or output of another gate. The inverted input/output is marked with a circle instead (Compare ND and NND in the preceding table). Example for a logic circuit: Figure :Example for a logical circuit Complete logic gate sets complete logic gate set is a set of logical functions that is sufficient to build any logic expression. The simplest complete set we already know is {ND, OR, NOT} as it originates in the definition on oolean algebra itself. s we will see later, these gates are easy to work with but there are other types which are easier and cheaper to Notes on Fundamentals of Computer Engineering 9

21 Logical Functions Complete logic gate sets build. Moreover, wouldn t it be nice if we could do with just one type of gate? ll we have to do is to examine, if we can create ND, OR or NOT with our champion. Complete logic gate set with NND gates We can create a complete logic set only using NND gates: NOT with NND Gates = = & ND with NND Gates = = = ( ) ( ) & & OR with NND Gates + = & = = ( ) ( ) & & + Complete logic sets with NOR gates Equally, NOR gates are sufficient for a complete logic set: NOT with NOR Gates = + = > ND with NND Gates = = + = = ( ) ( ) > > > Notes on Fundamentals of Computer Engineering 2

22 Logical Functions Complete logic gate sets OR with NND Gates ( ) + = + ( ) ( ) = = ( ) ( ) > > + Realizing circuits with complete gate sets The preceding section showed that any circuit can be generated using only one type of gate. On the other hand up to three gates are used to employ one single operation which is not very economic. The approach for whole circuits is more straightforward and makes use of the canonical forms: NND circuits can be derived directly from a SOP (sum-of-products) NOR circuits can be derived directly from a POS (product-of-sums) fter converting a logical function into the required normal form it is double inverted and DeMorgan s law is employed once: NND f = ab ( + cd) = ab + acd = ab + acd = ab acd = ab acdd NOR f = a( b+ c) + d( b+ c) = ( a+ d)( b+ c) = ( a+ d)( b+ c) = ( a+ d) + ( b+ c) = ( a+ d + d) + ( b+ c) = ( a ( d d)) ( b c) a b a b c d c d NND based circuit for f = ab ( + cd) NOR based circuit for f = ab ( + c) + d( b+ c) Please note that the logical functions NND and NOR are not associative. Notes on Fundamentals of Computer Engineering 2

23 Logical Functions Complete logic gate sets ( a b) c= a+ b+ c= ( a+ b) c a( b+ c) = a+ b+ c= a ( b c) Therefore it is important to use brackets when using the sign for NOR or sign for NND. Even though there exist multiple input gates that implement a NND or NOR function for more than 2 input variables. Thus it is sensible to have more then two variables in one NOR/NND expression but it is not sensible to write down this expression with and unless the only gates available are two-input gates. In this case the expression needs to be converted carefully: abc = abc = ( ab)( ab) c = (( a b) ( a b)) c The example shows that to replace one 3-input NND gate we would need 4 NND gates with two inputs! Notes on Fundamentals of Computer Engineering 22

24 Logical Levels, Timing & Delays Logical levels Logical Levels, Timing & Delays Logical levels efore we can think on how to build gates we have to decide on how to represent our logical values and. Even though switches and lamps were basically introduced to demonstrate the principle they are only halfway the real thing. t first, for a logical circuit we need something that supports two stable states. This could be a mechanical lever (2 positions), water in a bucket (empty full), a torch (burning or not burning) or anything comparable (in the 9 th century somebody really did build some logical gates using water!). Today we use electrical circuits to model logical functions. This gives us two simple choices on how to represent the logical values: current or voltage. With our switches the was a closed switch. Therefore the was represented by a current i (mpere) passing the switch. n open switch cuts of the current, so the was represented by a current of. Current=i logical Current= logical Different interpretations s much as the assignment described above sounds logical it is important to understand that it is only one possible assignment. Of course we could have had it exactly the other way round: closed switch is and open switch is! Even though this is much less descriptive it would lead to a consistent system. dditionally there are two simple ways of expressing logical values with electricity: currents and voltages. In both cases we pick two distinct values and assign one to logical and one to logical. Usually one of these values is but this is pure choice and not a necessary part of the game. Thus with current or voltages there are four possible ways to express logic: Current (I <I2) Voltage (U < U2) Logical I I2 U U2 Logical I2 I U2 U Table 7:Possible electrical representations for logical values Positive and negative logic Let us come from what we might choose to what all the others really do. Today s electronic logic circuits use voltage levels to express logic and one of these levels is (nearly) always V. In positive logic the logical is assigned the voltage V and Notes on Fundamentals of Computer Engineering 23

25 Logical Levels, Timing & Delays Logical levels the logical is represented by a voltage Umax. In negative logic the assignment is just the other way round: Positive Logic Negative Logic Logical V Umax Logical Umax V Table 8: Positive and negative logic (with voltages) Ranges for logical values uilding devices that have exact voltage levels are complicated and expensive (especially if the output is consumed by a variable number of other circuits). dding the fact that the output of one circuit might be transferred by whatever channel (cable, radio waves, optical cable) to the input of another circuit it gets clear, that a logical circuit has to keep up with inputs that are nearly Umax or almost as well. Thus the exact logical levels L and H are a nice idea to work with in theory but in hardware reality they are represented by whole voltage ranges: UL,min <Usignal<UL,max Logical Low UH,min <Usignal<UH,max Logical High Thus in positive logic a signal must be smaller then the upper bound of the Low range to be interpreted as a logical. ccordingly it must be at least equal to the lower border of the high range to be interpreted as a logical. It is common to have the two areas separated by a third area (thus UL,max UH,min) so that a corrupted logical signal might be recognized: U U H,max U H,min U L,max U L,min Range for logical Logic value undefined Range for logical Figure 2: Ranges for logical values (in positive logic) Notes on Fundamentals of Computer Engineering 24

26 Logical Levels, Timing & Delays Timing diagrams (Impulse diagrams) Just to give an impression, some typical ranges are Logical Low Logical High TTL circuits.7 V V CMOS circuits -.5 V 3 5 V Table 9: Typical voltages for logic gates Of course there is still the difference between positive and negative logic in negative logic the higher voltage range represents the logical low: Positive logic Negative logic U U Umax U max Umin logical logical t U min logical logical t Figure 3: Voltage diagram for a change from logical to in positive and negative logic Timing diagrams (Impulse diagrams) The last example in the preceding chapter already introduced a widely used means of describing the behaviour of logical circuits: the timing or impulse diagram. s logical values are assigned to levels it is straightforward to sketch these levels against time. Thereby we can sketch the real voltage levels or just abstract logical levels (also called logical L (Low)) and (called logical H (High)). y sketching the inputs and the outputs of a logical circuits we can characterise the circuit s behaviour even more completely as with a truth table as the truth table only explains what happens. The timing diagram adds the information about the when, which will be most important in the next section. X = X = + Figure 4: Timing diagrams for the conjunction and the disjunction Notes on Fundamentals of Computer Engineering 25

27 Logical Levels, Timing & Delays Propagation delay Propagation delay So why is it so important to bother about time? Well, as everything in the world needs time, real logical circuits do not react immediately to input changes but need time they delay the input signal. The delay that occurs when feeding an input signal to a logical circuit several origins: Switching delay: whatever kind of electronics were used to realize the gates they need time to switch from one logical state to another Transmission delay: the time the electrical impulse need to travel between the circuit s components The addition of these times is called the propagation delay or transition time, it is the time between the moment when the inputs of the circuit are changed until the effects of this change occur at the output. These times can be different for the output changing from Low to High or changing from High to Low, so there are actually two propagation delays for a logical circuit: t PLH t PHL Propagation Delay for a output s change from logical Low to logical High Propagation Delay for a output s change from logical High to logical Low The delays are illustrated for an inverter in the following figure. The Low to High delay is found as the time difference between the input voltage going from High to Low and the output voltage going from Low to High do not mix up the namings, it is the output that rules. U e High Low t U a High Low t PLH t PHL Figure 5: Propagation delay for an inverter t Notes on Fundamentals of Computer Engineering 26

28 Logical Levels, Timing & Delays Propagation delay Though this does not seem hard to measure there is still need for further thinking. The input signals as used until yet all had vertical flanks of course this is quite hard to achieve as it means the voltage is and UHigh at the same time! Figure 6 shows a more (not yet totally) realistic input signal. We define as rise time tr the time a signal needs to go from Low to High. ccordingly the fall time tf is the time the signal needs to go from High to Low. To calculate rise and fall we measure the actual times for the signal having % and 9 % of the maximum voltage: tr=t(u=.9 Umax) t(u=. Umax) tf=t(u=. Umax) t(u=.9 Umax) Figure 6 shows the propagation delays for a buffer (thus the logical function =). ssuming that the signals flanks are not vertical there are obviously several possibilities to measure delays (Input starts changing to output starts changing, input starts changing to output ends changing etc). It is convention that propagation delays are measured as the time between the input signal being 5 % of the maximum voltage and the output voltage being 5 % of the maximum voltage: tp=t(uo=.5 Umax) t(ui=.5 Umax) U i t 9% 5% % U o t P L H t P H L t 9% 5% % t R t F Figure 6: More realistic signals and propagation delays of a buffer The existence of propagation delay makes the design of digital circuits more complicated. Sometimes a very smart solution on the pure logical side turns out to be worse working than a more complex solution just due to the timing behaviour. For the following discussion on that behaviour we want to idealise impulses to have vertical flanks. Propagation delays of combinational circuits In circuits containing more than one the propagation delays add up and sometimes create unwanted effects. To find out the timing behaviour of such a circuit we have Notes on Fundamentals of Computer Engineering 27

29 Logical Levels, Timing & Delays Propagation delay to consecutively draw the timing diagrams for all the gates of a circuit, starting on the input side. The following example shows the function f = ( + + C) D for the four input states (,,C,D) = (,,,), (,,,), (,,,), (,,,): C D X Table : Outputs for the four given inputs ll gates have the same propagation delays tplh= tphl = tpl = ns. For an analysis of the timing behaviour, the output of every gate is sketched beginning with the gates that are connected to the inputs and therefore form the st layer of the circuit. The gates that are connected to the outputs of the first layer form the second layer, their outputs are sketched next in the diagram D D C X ++C Figure 7: Implementation of f = ( + + C) D C D E ++C X Figure 8: Timing diagram for the circuit nearby The circuit shown in Figure 7 could be called a regular two layer circuit, as any input signal has to pass exactly two elements. The timing diagram is done by first sketching the output of the OR-gate as K = + + C and the inverter s output E = D. The output can then be found as X=K E. Due to the regular structure of the circuit there is a fixed transition time for all possible input combinations: tt=2 tp. Thus the input combination = and D=, which is present at t= ns produces a at the output at t=3 ns. The influence of the propagation delay can be seen in Notes on Fundamentals of Computer Engineering 28

30 Logical Levels, Timing & Delays Hazards C D Z ++C X Figure, where a different implementation of the same function yields a greater delay of the output signal. D C W Z Y X Figure 9: Different Implementation of f = ( + + C) D C D Z ++C X Figure : Timing diagram for a different implementation In the second example a NND gate was used to implement the function f = ( + + C) D = C D. ecause the information of the input changing to one has now to pass three gates, the total propagation delay for this input state is tp=3 ns. Hazards The total delay of the output signal is surely annoying, but still the output is as expected, so why bother so much on it? The answer is that even in simple circuits the delayed signal can change the whole logical behaviour of the signal. Consider a functions as simple as X=(+)C with the input sequence (,,C) = (,,),(,,),(,,),(,,) C X Notes on Fundamentals of Computer Engineering 29

31 Logical Levels, Timing & Delays Hazards Obviously the output of a circuit implementing this function should remain for an input sequence like that. Figure 2 shows that there is a peak instead. ns ns C Figure : Circuit for f=(+)c Y X C Y X Figure 2: Timing diagram for the circuit nearby This kind of peaks are called glitches and are a consequence of signal races, as their origin are differently delayed input signals: in this example the information about C going up reaches the last gate by tp earlier than the information about going down. Thus the ND gate reacts like there was an input of (,,C)=(,,) which yields the that we see in the diagram. The componenet organization which causes such glitches is called a hazard. It is obvious that hazards and the resulting glitches might trigger unwanted states in the circuit somewhere else, so they must not be ignored. Using hazards If the preceeding chapter left you with the impression that hazards are the developer s greatest enemy you are partly wrong. ctually we even can make use of the glitches. Consider the circuit in Figure 3 which seems to a completely stupid method of generating a logical and it is quite obviously a hazard. Now let jump from to which makes the circuit generate a glitch which is a pulse with the pulse width of tpulswidth=tp. Thus the circuit as shown below is a pulse generator that generates a pulse whenever a raising flank occurs at it inputs. Therefore it could also be called a raising-flank-to-pulse converter. Using an (odd) number of n inverters it is possible to generate pulses of tpulswidth=n tp with this technique. ns Y X Y X Figure 3: Flank to pulse converter t p Figure 4: Timing diagram for the flank-topulse-converter Notes on Fundamentals of Computer Engineering 3

32 Logical Levels, Timing & Delays Hazards Y X Y X Figure 5: Flank-to-pulse converter with triple pulse width Figure 6: Timing diagram for the flank-topulse converter with triple pulse width 3t p Notes on Fundamentals of Computer Engineering 3

33 Karnaugh-Veitch-Maps Simplification of logical functions Karnaugh-Veitch-Maps Simplification of logical functions Up to now we used truth tables and oolean expressions in one of the normal forms to represent logical circuits. oth of them are extended descriptions for a logical function, containing a lot of redundant information. For economical and reliability reasons, it is necessary to examine each function and eliminate irrelevant terms using suitable methods before their technical realisation. The following illustration represents the technical circuit realisation of one logical function. The left circuit is derived from the disjunctive normal form, the right one from a simplified expression. s every Minterm needs on gate, the latter would be much cheaper and easier to realize, even though it provides the same functionality. CD + CD + CD + CD + CD + CD = C + C Figure 7: Circuit for a logical function, derived from the expanded and from the simplified expression Even though the two circuits yield the same results the second circuit is easier and cheaper to realise. Manual simplification is usually very time consuming and too error prone. The quality of simplification depends strongly on the experience and intuition of the person, especially when dealing with a large number of variables. Notes on Fundamentals of Computer Engineering 32

34 Karnaugh-Veitch-Maps Structure of KV-Maps Therefore, a systematic minimisation method was introduced, which would produce minimum solution, bearing in mind that there could be more than one minimum solution for the same function. asically there are two types of systematic minimisation methods: Graphical minimisation methods + are fast + are not complicated - can only be used for a limited number of variables - are experience needed Tabular minimisation methods + can handle any number of variables + can be implemented as a computer program - are slow - are complicated Two popular methods of minimisation of oolean function are: Karnaugh -Veitch Maps (Graphical) Quine-McCluskey lgorithm (Tabular) Structure of KV-Maps The Karnaugh-Veitch-Map is a graphical method of minimisation that was developed in early 5 s. It is named after the mathematicians Karnaugh and Veitch, and is also known as KV-Diagram or K-Map. KV-Maps are used to minimise oolean equations with up to 4 variables. The method was derived from the Euler- Venn-Diagram set theory. How to draw a KV-Map The KV-Map is the graphical presentation of a truth table in matrix form. Each field of the matrix corresponds to a Minterm. For n input variables, the KV-Map has therefore 2 n fields. The fields are arranged in such a way, that the adjacent fields differ only in one input variable. The nearby illustration shows a KV-Map with one variable. The KV-Map is divided into 2 parts, one part for the variable (a = ) and the other part for the negated variable (a = ). bar at the side of the KV-Map marks the region where the variable is. a a a= a= Figure 8 KV-Map for one variable Notes on Fundamentals of Computer Engineering 33

35 Karnaugh-Veitch-Maps Structure of KV-Maps KV-Map with 2 variables has, for each of the two variables, a negated and a not negated region. Thereby a diagram with 4 fields is used. The KV-Map for multiple variables can be obtained by mirroring the basic structure. C D Figure 9 The development KV-Maps for more than variable by mirroring The distribution of the variable s region does not need to be exactly like in Figure 9. Figure 2 shows other possibilities to draw a KV-Map for 4 variables. C a a b c d d c b Figure 2: Two different valid setup for a 4 variable KV Map Neighbours across the borders In 2-dimensional representation, it is not clearly shown that the fields at the map s borders are neighbours to each other. This circumstance becomes clearer when sketching a KV-Map in 3 dimensions. In Figure 2 we can easily see, that C and C are neighbours. Notes on Fundamentals of Computer Engineering 34

36 Karnaugh-Veitch-Maps Logical functions in a KV-Map C C a C C C C b C C C C C C C C c C C Figure 2 KV-Map in 3 dimensions KV Maps for more than 4 variables The assignment of areas in a KV-Map with 5 variables is complicated. Using a KV- Map on more than 4 variables will lead to at least one area that is split up. This is the reason why the utilisation of KV-Map is somehow limited. The example in Figure 22 shows a KV-Map with 5 variables. a a b d c e Figure 22: KV-Map for 5 variables Logical functions in a KV-Map KV-Map can be considered as a 2 dimensional truth table. s every possible input combination is found as one field of the KV-Map, every field corresponds to one row in the truth table. cell map helps to find each row of a truth table in a KV-Map (keep in mind that the position of the rows depends on how the KV-Map was drawn). Notes on Fundamentals of Computer Engineering 35

37 Karnaugh-Veitch-Maps Logical functions in a KV-Map N o a b c f 2 (a,b,c) a b 4 5 c Figure 23 Truth Table and Cell Map To represent a function with the KV-Map we only have to fill the map s fields with the according function values N o a b c f 2 (a,b,c) a b c Figure 24 Truth Table and KV-Map If the function is given as a oolean expression the most easiest way is to use the DNF to fill the KV-Map. The DNF for the example above is f = abc + abc + abc + ab c + abc. Thus there is a in the KV-Map for every Minterm that occurs in the DNF. Writing a function in DNF to a KV Map therefore consists of finding the field for each Minterm and filling it with a. The remaining fields are then filled with a. f = abc + abc + abc + ab c + abc Notes on Fundamentals of Computer Engineering 36

38 Karnaugh-Veitch-Maps Logical functions in a KV-Map a abc abc ab c abc c b abc KV Maps - merican Style Figure 25 From DNF to KV-Map The former section already demonstrated, that the distribution of the fields in a KV Map might differ from case to case. What makes it even more confusing is that there exist two common ways of denoting the variables making KV Maps. Though it seems there are two different philosophies, the look more different than they are. The denotation shown above is widely used e.g. in Germany whereas especially in merican literature engineers use a notation as in Figure 8 (the numeration corresponds to the rows of a truth table). a b ab ab ab ab ab cd Figure 26: merican Style KV Maps for 2 and 4 variables In this notation, the values for the input variables are simply written to the borders of the map. Every field in the first column represents an input combination where a=. ccordingly, the first row contains all fields, where b= (two variables) or where c= and d= (four variables). This style comes quite close to being a 2 dimensional truth table: from every field we can nearly directly read the according truth table entry: Field 7 is in the column where ab = and in the row for cd =. Thus field 7 represents the input combination abcd = which corresponds to the Minterm abcd. In the same way, field 4 would represent ab= and cd=, making abcd=, so it is the field for the Minterm abcd. Notes on Fundamentals of Computer Engineering 37

39 Karnaugh-Veitch-Maps Minimisation with KV Maps e aware, that this is only a different style of drawing a KV Map and not a different concept 5. Figure 27 illustrates that it is even possible to use both styles on the same drawing. Which one you use in the end is a question of personal preference, but you need to know how to handle both (e.g. in case you need to read someone else s maps). ab cd a d c Figure 27: KV Map in both styles b Minimisation with KV Maps The purpose of introducing KV-Maps was to minimise logical functions. possible way for algebraic simplification is by cancelling out two terms, where one term contains one or more negated variables and the other term contains the according non-negated variables: f = abc + abc = ab( c + c) = ab In a KV-Map, such terms would be neighbours. Thus minimisation with KV-Maps means searching for pairs of s: a ab c abc b ab c + abc = ab c 5 Even though they are sometimes distinguished by the two different names Karnaugh Map (merican) and Veitch Diagram (Non merican) Notes on Fundamentals of Computer Engineering 38

40 Karnaugh-Veitch-Maps Minimisation with KV Maps It can be seen that for every pair one variable is cancelled out. This kind of summary can also be done for more than one Minterm by looping together blocks of 4, 8 or 6 fields containing a : a d b f = abcd + abcd + abcd + abcd = bd ( ac + ac + ac + ac ) = bd (( a + a)( c + c)) = bd c The last example also illustrates that for eliminating a variables there has to be a block of 2 a one in the KV Maps. The minimised terms are called Implicants. In most of the cases, some Minterms will be covered by more than one implicants, but the aim is to find for each Minterm a block that is as big as possible the bigger the block the smaller the term for the implicant (the less gates and wires are needed to implement it). ny implicant that is not completely part of a smaller implicant (any loop that is not part of a bigger loop) is a Prime Implicant a term that cannot be minimised further. The minimised function consists of all Prime Implicants that are needed to cover all the original Minterm. ab a b d b d f = a c + b d + ad a c ad c Figure 28 Minimised function with 4 implicants and 3 Prime implicants Figure shows an example where we have four Prime Implicants but only need three of them to completely describe the minimised function. ny Prime Implicant that contains at least one Minterm that is not covered by any other Prime Implicant must be part of the minimised function. These terms are therefore called Essential Prime Implicants. Notes on Fundamentals of Computer Engineering 39

41 Karnaugh-Veitch-Maps Minimisation with KV Maps Minimising across the borders When searching for blocks of ones we have to keep in mind that KV-Maps are circular i.e. that the left neighbours of the cells in the first column are the cells in the last column (see Page 34). Thus it needs a bit of training to find the implicants in the outer regions : a d b f = abcd + abcd + abcd + abcd + abcd + abcd = cd + acd c a Figure 29 Minimise across the borders... d b f = abcd = cd + abcd + abcd + ab cd c Figure 3...and even across corners Notes on Fundamentals of Computer Engineering 4

42 Karnaugh-Veitch-Maps Minimisation with KV Maps KV-Maps and Don t cares If a function contains don t care states KV-Maps really start getting powerful. s a don t care is an input combination that will not occur, the function value for this combination does not matter we can choose it. In a KV-Map we mark don t care with a X and use them as ones if this helps building bigger blocks (=smaller implicants). It is vitally to understand that an X can be used to form an implicant but does not need necessarily to be used we don t care about any not used X, hence the name. s an example we take the conversion of 4 bit binary code numbers to 4 bit iken code numbers. In binary, 4 bit can represent 6 numbers (and therefore 6 states), whereas iken code can (by definition) only form number with 4 bits. Thus there are 6 binary numbers ( input combinations) with no output they are the don t care states. inary Code iken Code C D W X Y Z Input combinations without function value Don t care states Figure 3 Truth table for inary - iken Conversion Notes on Fundamentals of Computer Engineering 4

43 Karnaugh-Veitch-Maps Minimisation with KV Maps s we convert 4 inputs to 4 outputs we find four output functions according to the truth table on page 4. W = CD + CD + CD + CD + CD X = CD + CD + CD + CD + CD Y = CD + CD + CD + CD + CD Z = CD + CD + CD + CD + CD The following truth tables demonstrate the use of don t care states. Especially the KV-Map for Z illustrates how only some of the don t cares are employed to find implicants whereas some of them are ignored. D D X X X X X X C W = + C + D X X X X X X C Y = + C + CD D D X X X X X X X X C X = + D+ C X X X X C Z = D Product-of-Sums and KV-Maps The last chapter always used KV-Maps with functions that were in the sum-ofproduct form. Sometimes it is useful to employ a product-of-sum form instead e.g. when the aim is to design a NOR circuit. Thus we need to know how to write functions in CNF to KV-Maps how to read minimised functions as POS. Notes on Fundamentals of Computer Engineering 42

44 Karnaugh-Veitch-Maps Minimisation with KV Maps Table shows the distribution of Maxterms in a KV-Map: a a + b + c a + b + c a + b + c a + b + c b a + b + c a + b + c a + b + c a + b + c c Table : KV-Map with Maxterms Writing down a CNF into a KV-Map is pretty much like writing it into a truth table everything is just the other way round as with a DNF: when finding the field of a term, a negated variable x corresponds to the x= area in the Map we write a into the fields that correspond to the Maxterms The same rules apply for minimisation: to find a minimised function as POS we first search blocks of zeros! Then we read out the zero blocks with the difference that the basic structure of the simplified function is f = ( + )( + )( + ) the coordinates have to be read in CNF style: x for x= and x for x= f = ( a + b + c )( a + b + c )( a + b + c ) a b c f = ac + bc = ( a + c )( b + c ) Remember that a KV-Map is just one more way to write down oolean functions. Of course it is possible to write a function that was given in DNF to a KV-Map and deduce the simplified function as product-of-sums. Thus a KV-Map is a perfect medium to transform a oolean expression from SOP form to POS form or vice versa. Notes on Fundamentals of Computer Engineering 43

45 Number Representation Positional Number Systems Number Representation Introduction orn with fingers we are used to think of numbers in a decimal system, building our numbers with a basic set of symbols the digits ( digitus is Latin for finger ). When working with digital circuits we have to adopt to their limits: as they have only two fingers (logical one or logical zero), they have to use the binary system with only two digits. s binary (or dual) numbers are quite long it has become common to use octal or hexadecimal numbers to visualize numbers when working with digital circuits they are shorter than the binary ones but easier to transform from/into dual numbers than decimal numbers. Positional Number Systems ll mentioned number systems are positional (polyadic) meaning that the value of a number results from the values and the positions of the digits. ny decimal number is a row of digits where the values left-most value the most (Most Significant Digit, MSD) and the one right-most values the less (Least Significant Digit, LSD). To gain the number s actual value every digit is multiplied with a power of ten starting with = at the right. Thus the bundle of signs 968 means number with a fractional part works exactly the same way, only that the value of the position is ten to the power of a negative number:, 32 = Of course this scheme is just the specialized case of a more general principle. The number of symbols in the basic set of a number system is called the base. The digits can than be interpreted as coefficients xi of the position value n. The base of a certain number is usually indicated by an index after the number. 2 Z = x = n n i i= m n + x i x n n + + x + x + x + x x m m Z: Number of a number system with the base : ase of number system (with 2) xi: Digits (with xi<) i : Value in the i-th position n: Total number of integer digits m: Total number of fraction digits Notes on Fundamentals of Computer Engineering 44

46 Number Representation Positional Number Systems In the dual system, the numbers used are and only. These numbers are also known as it (from binary digit). In the hexadecimal system the base is 6, thus 6 digits are required. Therefore, from onwards, the numbers are expressed with the characters to F. Number system ase Numbers Dual 2 {,} Octal 8 {,,2,3,4,5,6,7} Decimal {,,2,3,4,5,6,7,8,9} Hexadecimal 6 {,,2,3,4,5,6,7,8,9,,,C,D,E,F} Table 2 Number sets of different Number Systems Decimal Dual (inary) Octal Hexadecimal C 3 5 D 4 6 E 5 7 F 6 2 Table 3 Counting to 6 in different Number Systems Thus the decimal number is calculated by multiplying the digit with the value of its position. For small numbers this can be done manually and it is not a bad idea to know the most used position values for binary numbers by heart: Notes on Fundamentals of Computer Engineering 45

47 Number Representation Positional Number Systems Digit s position Position Value Table 4 Position values of binary digits Examples: Dual number : Z= 2 Z = 2 = = = ase 5: Z= 423,325 Z = = 566, = , 6 +, Hexadecimal Z= F3,3C6 Z = = 44859, = , 875 +, Conversion of Dual number to Octal/Hexadecimal systems inary numbers are bulky to work with to express a number in the range of to it already needs 9 digits (bits). On the other hand the conversion to decimal is, though managable, a bit complicated to be done quickly. The conversion from binary to hexadecimal is somewhat easier and has another advantage: in computers, the basic unit of data is the byte which is 8 bit. Therefore numbers in computers basically come along as 8 bit numbers which can be expressed with two digits in hexadecimal. In former times, the octal system was quite popular to visualize binary numbers. The conversion to octal/hexdecimal is simple because we can group the binary numbers into groups of 3 i.e. 4 digits and convert these groups separatly. Thus we only have to convert numbers smaller then 6 remember the table. The other way is as simple: every octal/hexadecimal can by converted digit by digit. Notes on Fundamentals of Computer Engineering 46

48 Number Representation Positional Number Systems Conversion dual octal Conversion of binary number Z=,2 into octal number. Divide the part before comma into 3 parts: Z2=, The outlined s are added to gain groups of 3 digits each. Now each group is converted on its own Dual, Octal 3 5, 5 4,2 =35,548 Conversion dual hexadecimal The conversion of a dual number into hexadecimal number is done in a similar way, only differing in the number of digits. The binary number is divided into groups of four instead of three. Z =.2 Group the binary numbers into 4 digit groups, treating the integer part (before the comma) and the fractional part (after the comma) separately : Dual Hexadecimal 2 4=E.2=2.E6 Conversion of hexadecimal number into binary number Z = 26 Hexadecimal 2 Dual 26= 2 Notes on Fundamentals of Computer Engineering 47

49 Number Representation Positional Number Systems Conversion from decimal to any system: Horner lgorithm s numbers in a number system with the base can be seen as the sum Z = n i= m x i i the conversion from decimal to any other systems means determing the coefficients xi. s usual it is easier to treat the integer and the fractional part separatly. Conversion of integer numbers: The integer part of the sum shown above can be rewritten as Z ((( x + x ) + + x2 ) + x) = 5 = ( 2 + ) 2 + n n + x This term divided by the base will yield Z ((( x + x ) + + x ) + x ) = + n n 2 x 5 2 = ( 2 + ) x with x < < and ((( x + x ) + + x ) + x ) n n 2 > It can be seen clearly, that ((( x + x ) + + x ) + x ) n n 2 > is the integer part of the division whereas x corresponds to its fractional part. Therefore we can receive x as the remainder of an integer division 6 : Z =(Z DIV ) + x 5 = 2 ( 5 DIV 2) + Z DIV = (( xn + xn ) + + x2 ) + x 5 DIV 2 = 2 + Z MOD = x 5 MOD 2 = The first digit that is the coefficient x can therefore be obtained by determining the remainder of an integer division of Z by. Having a close look to the result of the integer division we recognize, that it is of the same form as the term we started with only that now we can lay our hands on the second digit x: x = ((( x + x ) + + x ) + x ) MOD = ( Z n DIV ) MOD n 2 x = ( 2 + ) MOD 2 = ( Z DIV ) MOD 6 Integer division is what we use when dividing manually: Z DIV means dividing Z by and cutting of the fractional part. The remainder is the according error: R=Z MOD =Z (Z DIV ) 7 : 2 = 3.5 = 3 Remainder 7 DIV 2 =3 and 7 MOD 2= Notes on Fundamentals of Computer Engineering 48

50 Number Representation Positional Number Systems It should be a lesser surprise that the third digit/coefficient comes along with just one more division which makes obvious the principle of the Horner scheme: x 2 = ((( x + x ) + + x ) + x ) MOD = (( Z n n DIV ) DIV ) MOD 3 2 This game can be played until we reach the last digit xn and the actual operation is xn = xn MOD. In this case the according division x n DIV is zero which is the end condition for the algorithm. Now we just have to collect our digits by remembering that the first digit we reveiced was the least significant digit x and the last one was the most significant xn. Z The actual digit is the remainder of the division by : x i = Z MOD Divide by and store the result: Z = Z DIV Check if division yielded zero: W=? Yes Stop No Conversion of decimal fractions: The conversion of fractions is similar to the conversion of whole numbers. However, instead of carrying out division, multiplication with base number is performed. Instead of having a remainder, a carry will be obtained. s the fractional part of a number is Z 2 = x m x m... x 2 x the multiplication mentioned above yields Z 2 = x m + x m x + x 2 with x 2 m + x m x < and x-> s we can see the digit x- is the integer part of this multiplication. For the next digit we only have to multiply the fractional part of the result again: Z 2 = x m + x m x + x 3 2 It can be seen, that for the fractional digits we consecutivly multiply the fractional part of our result and take away the integer part as xn. Reaching the last digit X-m we Notes on Fundamentals of Computer Engineering 49

51 Number Representation Positional Number Systems perform x m = x m thus the end condition is a fractional part of zero. The only problem about this is that a number with an ending fraction in the system may be a number with an endless fraction in another number system (the number.37 is 3 = in decimal). If a decimal number corresponds to an 7 endless dual number, it is not possible to represent this number exactly in binary! Instead there will be a conversion error ec=n-n2. In this case we must choose another end condition for the Horner Scheme, e.g. a maximum number of digits (as in computers there are only a limited number of bits) or a minimum conversion error: Z ctual digit is the integer part of the multiplication by xi=int(z*) Continue with the fraction part of the multiplication: Z=FRCT(Z*) Check if fraction is zero or maximum number of digits reached: Z= v n>n max? Yes Stop No Example for the Horner-lgorithm Now let s see the Horner-lgorithm in plain action. s an example we convert the decimal number 37.56: Z = = Z + Z2 = 37 +,56 Z: 37:2= 8 R (least significant digit) 8:2= 9 R 9:2= 4 R 4:2= 2 R 2:2= R :2= R (most significant digit) 37 = 2 In this example we limit the fractional part to 8 bit: Z2:.56 2=.2 C.2 2=.24 C.24 2=.48 C.48 2=.96 C.96 2=.92 C.92 2=.84 C.84 2=.68 C.68 2=.36 C.56.2 Notes on Fundamentals of Computer Engineering 5

52 Number Representation inary Representation of signed numbers With.2 =, we make an conversion error of ec =,5325 by limiting the fraction to 8 bit. The result of the conversion is inary Representation of signed numbers The number of conversions presented above have in common, that they only dealt with positive numbers. Of course there is the possibility of writing a minus before a number in any system to mark a negative number. ut remember that all this trouble is done with the aim of building a machine that uses logical circuits to calculate and these circuits only can do s and s! There exist several systems to represent signed numbers in binary form. The most common are the Sign- Magnitude Representation and the Two s Complement. efore going into these representations we should have a short look at the matter of word lengths and ranges. Word Length & Ranges The binary representation of a number is usually called a data word. Therefore the number of bits that are used per number is called the word length. Logically a given word length determines the range of numbers that can be represented: with a word of n bit there are 2 n possible numbers. The actual range is determined by the word length and the used system. Modern computers usually employ word lengths of one or several byte ( byte = 8 bit): Word length n Number of words 2 n Range if used as unsigned integer [, 2 n -] byte = 8 bit 256 [, 255] 2 byte = 6 bit [, 65535] 4 byte = 32 bit [, ] Table 5: Ranges for unsigned integer numbers Sign-Magnitude Representation The most straightforward way to represent signed numbers is to indicate the sign by an extra bit. This form is called the Sign-Magnitude Representation as sign and magnitude can be cleary distinguished in the binary number. The sign is stored in the MS which is therefore called sign bit. y convention, the sign bit is for positive numbers and for negative numbers. Notes on Fundamentals of Computer Engineering 5

53 Number Representation inary Representation of signed numbers Decimal Sign inary Number Magnitude Table 6: Example for the Sign-Magnitude Representation with 5 bit. Two s Complement The Two s Complement (also 2 s complement) is the system that is commonly used in digital systems. The Two s complement meets the following requirements: The most significant bit indicates the sign of a number ( negative). Decimal zero is represented by only one binary number The binary addition of any numbers yield a correct result without any further conversions Even though the sign of a number is indicated by the MS the Two s Complement does not have a sign bit. Much more it is a mapping of a range of decimal numbers [- 2 n-,2 n- -] to a range of binary numbers [,2 n ]. This mapping can be seen in Figure = + 4 = Figure 32: Two s Complement for 4 bit numbers binary representation of a negative decimal number can be obtained in two ways: Finding the Two s Complement by inversion Transform the magnitude of the decimal number to binary. Notes on Fundamentals of Computer Engineering 52

54 Number Representation inary Representation of signed numbers uild the One s Complement 7 by inverting every single bit of this binary number. dd to the result. Example (Used bits: n=5): -2 Magnitude Decimal: 2 Magnitude inary: One s Complement: Two s Complement: Finding the Two s Complement by subtraction Substract the decimal number from 2 n (n is the data word length). Convert the difference to a binary number Example (n=5) -2 Difference = 32 2 =2 Two s Complement 2 = 2 Decomplementing a negative number Complements work just like the minus sign: complementing a positive number yields the negative number. Complementing a negative number yields ( ) =. Complementing a number means nothing else than negating it! If somebody tells you that a number is in 2s complement it does not mean the number is negative. Instead it means that the number might be negative because it is stored in a representation that allows negative numbers too. So if a binary number is given and it is known that it is in Two s Complement, these are the steps to decimalise it: Find out, if the number is negative (MS=) or positive (MS=) If the number is negative, complement the number as described above. The resulting number is a positive value, the magnitude of the original negative number. Convert the magnitude to decimal. Put a minus if the binary number was negative 7 The One s Complement is another possible system of representing signed numbers. s it has the same disadvantage as the S-M-System ( and ) it is seldom used. Notes on Fundamentals of Computer Engineering 53

55 Number Representation Fixed-length format for Decimal Fractions Example: may be an 8 bit number in Two s Complement: 8 bit MS = Number negative Invert( ) = dd Convert: 2 = 3 2,Two s C. = -3 Misinterpretation of inary Numbers Especially the last example shows clearly, that a binary number can easily be misinterpreted. To reconvert a given dual number we always have to know which kind of representation was used. If only a bit sequence was given, it could be System 2= Unsigned inary Number 38 Signed inary Number (Sign-Magnitude, n=6) Signed inary Number (One s Complement, n=6) Signed inary Number (Two s Complement, n=6) Signed inary Number (ny of these systems, n=8) -6-2 = = -26 = 38 Mind you, it could not even be intended to be a number at all. This example should make clear that for the correct interpretation of a binary number we must know the word length if the number is meant to be a signed or an unsigned number if it is signed: which system for signed numbers was used Fixed-length format for Decimal Fractions Up to now we know how to convert decimal fractions to binary. ut how to actually store this binary? The problem is the same as it is with negative numbers: we use an additional symbol (the point) that is not available in digital circuits. One solution is Notes on Fundamentals of Computer Engineering 54

56 Number Representation Floating Point Numbers to divide a binary number in its integer and its fractional part with fixed lengths. For signed numbers the fixed length format can be used with Sign-Magnitude as well as with Two s Complement. For Sign-Magnitude the MS is reserved for a sign. For a Two s Complement inversion the point can just be ignored: inverse all bits and add a at the LS. MS Integer part (it 7-3) LS Fractional part (it 2-) Example: Figure 33: fixed-length format with 5 integer and 3 fraction bits Fixed-length binary (8 bit word, 3 bit fraction) Decimal Dual Sign-Magnitude 2 s Complement Table 7: Fixed-langth representation of fractions Floating Point Numbers The major disadvantage of the fixed-length format is its inflexibility. s the length of the parts has to be fixed there is always the struggle between range and precision. 32 bit number with an integer part of 3 bit is sufficient for big ranges but a poor choice in precision when numbers get below. On the other hand reserving 2 bits for the fractional part does not grant a big deal of numbers. The floating point format solves this problem of storing very big numbers and numbers with an extensive fractional part in the same format. The floating point format is based on the fact, that every number N can be expressed as a power of : N = ±M E Therefore a number can be stored by splitting it up into the Mantissa M, the Exponent E, the ase and the Sign = is equivalent to Sign: + Mantissa: Exponent: -2 ase: Notes on Fundamentals of Computer Engineering 55

57 Number Representation Floating Point Numbers This information now has to be stored which leaves us with a lot of choices: how to store the sign? Which base to choose (or choose it freely and store it with the number). How to store Mantissa and Exponent etc. It is obvious that there are several possibilities to define a floating point format. IEEE Floating Point Numbers The format commonly used in modern computer is the IEEE floating point format with 32 (Single Precision) or 64 bit (High Precision). y definition the base is always 2 and does not need to be stored: NIEEE floating point = ±M 2 E In the IEEE single precision representation of a real number, one bit is reserved for the sign. representation of the exponent is stored in the followin eight bits, and the remaining twenty-three bits are occupied by the representation of the number s mantissa. In the 64 bit (double precision) representation the exponent (in a special format so that it is called characteristic) gets bits and the mantissa 52: Sign Characteristic Mantissa single precision it 32 its 24-3 its -23 high precision it 64 its it -52 Figure 34 IEEE floating point representation The number is assumed to be a binary number already. The transformation of a decimal value into a IEEE floating point consists of the following steps: Determine the sign bit The easiest part: if the original number is positive, the sign bit is. If the number is negative the sign bit is. Transform decimal to binary The decimal number is converted to binary. If the number is negative only the magnitude is converted as the sign got its own bit (one could say that IEEE floating point is a Sign-Magnitude representation). The integer part is converted first. Than the maximum number of fractional digits is calculated: if ni is the number of bits needed for the integer part there are nf = 24 ni (single precision) nf = 53 ni (double precision) bits for the fractional part. Wait a moment to understand why there is one bit more than the mantissa length would implicate. Notes on Fundamentals of Computer Engineering 56

58 Number Representation Floating Point Numbers Normalizing the number The IEEE standard defines that the exponent of the number has to be chosen so that the mantissa is between and 2. To put it in another way: the normed (binary) number starts with a followed by the point and the rest of the number. To do the normalising you just have to move (to float ) the point. For every digit it is moved to the left the exponent is increased by one. If the point is moved to the right the exponent is decreased by one per digit: Storing the exponent M < 2 NIEEE floating point = ±.Mf 2 E fter the normalisation we receive an integer exponent that could be positive or negative. The IEEE format deals with signed exponents by storing a so-called biased exponent: bias of 27 (single precision) i.e. 23 (double precision) is added to the exponent of the normalised number. The biased exponent is called the characteristic: c = E + 27 (single precision) c = E + 23 (double precision) The IEEE definition reserves the bit combinations all-s and all-s for special use thus the ranges for the exponents are: Single precision: [ -27, ] = [ -26, +27] Double precision: [ -23, ] = [ -22, +23] Storing the Mantissa The normalised number always begins with a. Thus it is not necessary to store this. This suppressed digit at the beginning of the mantissa is called the hidden bit. y storing only the fractional part Mf of the mantissa it is therefore possible to store a n bit mantissa in n- bits this is why we used 24/53 bits for calculating the length of the fractional part. Special Case: Very small numbers and zero In the IEEE system, the all-zero characteristic is used for numbers that are very close to zero -- closer than 2-26 (2-22 for double precision), which is the least of the positive real numbers that can be represented in the part of the system described above. Such numbers are expressed without normalisation. The exponent is held fixed at 26 (-22 for double precision), and the mantissa is a number greater or equal to zero and less than one. So, for instance, the mantissa used for = = is.. Once again, only the part of the mantissa that follows the binary point is stored explicitly, so the (single precision) representation of is Notes on Fundamentals of Computer Engineering 57

59 Number Representation Floating Point Numbers Sign Characteristic Mantissa single precision The least positive real number that can be expressed with 32 in this way is 2-49, which is stored as. Moreover this special convention allows to represent a zero as a floating point number with all bits set to (or a at the MS and all following bits zeros which yields ). Special Case: Infinity and Errors characteristic of all bits set to one is defined to indicate an error. The floating point numbers and are interpreted as positive and negative infinity (for instance as results of a division by zero). ny other number with an exponent of all s means NaN (not a number) and occurs as result of an undefined arithmetic operation (e.g. a division of by ). Reading a IEEE floating point number Converting a floating point number back to decimal means just doing the same steps backwards.. Read the sign from the first bit. positive, negative 2. Read the characteristic from the next 8 (high precision: ) bits and subtract the bias (27 or 23) to receive the exponent E. 3. Read the fractional Mf part of the mantissa from the mantissa bits and add. to receive the Mantissa. 4. Move the point so that you receive a binary number with an exponent of : ±.Mf 2 E = ± N 2 5. Convert the dual number to decimal Examples Represent as a IEEE single precision floating point number: Sign bit Number positive Integer part: 22 = 2 5 bits its available for fractional part: 24 5 = 9 Fractional part:.625 =.2 Normalize binary number:. =. 2 4 Characteristic: 2 4 C = 4+27 = 3 = Mantissa to store (first bit hidden) Mf = Notes on Fundamentals of Computer Engineering 58

60 Number Representation Floating Point Numbers Sign Characteristic Mantissa (with hidden bit) = IEEE floating point = IEEE floating point Which number is stored in the IEEE single precision floating point number N =? N = Sign Negative number Exponent c = 2 = 38 E = = Mantissa Mf = M =.. Notes on Fundamentals of Computer Engineering 59

61 inary rithmetic inary ddition of unsigned numbers inary rithmetic inary ddition of unsigned numbers inary rithmetic is basically the same as the arithmetic in every other number system. The basic operations we learn for decimal arithmetic apply in other radix systems as well.the most basic operation is the addition which is extremely easy in binary. Considering two bits to be added there are only four possible cases: + = + = + = + = s in whole numbers every bit has its position, the case + produces a carry occurring in the next position. In this position could therefore occur a fifth case: + + = With these basic cases the addition of whole numbers is done bitwise from the least significant bit (LS) to the most significant bit (MS): Overflow Even though binary addition is simple in theory, it comes along with one problem in real life. The problem s origin is the fact, that in theory, there exist as many digit as need to represent a number but in real life, there is only a limited number of digits. If two summands are big enough there will occur a carry in the most significant position. Thus the addition of two n-bit numbers produces a result with (n+) bits the result is out of the range that could be represented with the original word length. The occurrence of a carry in the most significant position is called overflow Figure 35: ddition of 4 bit numbers, yielding an overflow Notes on Fundamentals of Computer Engineering 6

62 inary rithmetic ddition and Subtraction of signed numbers inary Subtraction of unsigned numbers inary Subtraction can be done likewise the subtraction of decimal numbers. Likewise the addition, the subtraction of each bit of a number can lead to a borrow bit in the next position. Thus to understand the subtraction of bits consider the following cases: = = = = orrow = orrow = orrow The problem in the binary subtraction are the same as for the addition: there could be a borrow bit coming from the MS. For the subtraction the overflow occurs when the subtrahend is greater than the minuend and the difference would be negative. s we intended to deal with unsigned numbers up to here it is no surprise that negative results lead to problems. ddition and Subtraction of signed numbers The preceeding section showed that using unsigned numbers in subtraction puts us up against to tight limits. In digital circuits it is usually easier invert the subtrahend and use an addition instead: Z Z2 = Z + ( Z2 ) Of course there is the old problem of overflows and it is a lot nastier than before. ddition The Two Complement s addition can be visualized as running around the already known circle in Figure 36. The overflow as known before i.e. a carry from the most significant position is nothing more than stepping from the negative to the positive half at the gateway / (consider + = = ). Therefore a carry from the most significant position has to be discarded. Nevertheless the Two Complement s addition has a different overflow. s 8 is just one step away from 7 the addition of two positive numbers can yield a negative one: = = - 8 Notes on Fundamentals of Computer Engineering 6

63 inary rithmetic ddition and Subtraction of signed numbers Thus an overflow in a Two Complement s addition can only occur if both numbers are positive or both are negative. Discard carry Overflow Figure 36: Numbers in Two s complement Examples If you have problems understanding the examples just think of the first number as starting point in the circle. The second number indicates the steps clockwise (positive) or counter-clockwise (negative) round the circle. ddition without overflow MS -3 Discard Notes on Fundamentals of Computer Engineering 62

64 inary rithmetic ddition and Subtraction of signed numbers Discard MS 4 + +(-3) MS ddition with overflow 3 + +(-5) MS Discard MS (-2) 7 Notes on Fundamentals of Computer Engineering 63

65 inary rithmetic inary Multiplication inary Multiplication We begin considering unsigned integer numbers. In the decimal system the multiplication a b is usually done by multiplying the factor a with each digit of b and consecutively adding these results. Thereby the single results are multiplied by powers of ten according to the digit s position: = In general and for all number systems this is can be expressed by Z = a b = a n i i= m i x = n i= m a x i i In binary the multiplication is outstanding easy as xi is either or and therefore a xi is either a or. The multiplication can be visualized in the same scheme as above: Fractional numbers are multiplied the same way by just ignoring the point during the multiplication procedure. The result has as many fraction digits as both factors together:.. 5 fraction digits, multiplication is the same as above =. Notes on Fundamentals of Computer Engineering 64

66 inary rithmetic inary Multiplication inary Multiplication of Signed Numbers Signed numbers in Sign-Magnitude-Representation cannot be multiplied directly. Instead they have to be split up into sign and magnitude and both parts have to be treated separately. The magnitudes are then multiplied as above. The sign of the result is determined from the signs of the factors: st factor 2 nd factor st sign bit 2 nd sign bit Result Result s sign bit Positive Positive Positive Positive Negative Negative Negative Positive Negative Negative Negative Positive C = Example (word length 6 bit): 3 (-4) = 2 2 Sign st factor Sign 2 nd factor Magnitude st factor Magnitude 2 nd factor Product of Magnitudes: = Sign of Result : 3 (-4) = inary Multiplication in Two s-complement representation cannot be done. Instead the numbers are converted to Sign-Magnitude representation to do the calculation. Notes on Fundamentals of Computer Engineering 65

67 Combinational Circuit Design Design of combinational circuits in 3 steps Combinational Circuit Design Introduction asically we distinguish two types of digital circuits: combinational circuits 8 sequential circuits. combinational circuit is a composition of digital gates without any feedback. Therefore the output is at any time only dependent on the actual inputs: In sequential circuits there do exist feedbacks, so the outputs depend on the actual inputs as well as on former inputs. Sequential circuits will be discussed in more extensively in later chapters Digital Circuits Combinational Circuits Sequential Circuits Two Level Circuit Multiple Level Circuit Design of combinational circuits in 3 steps In this chapter we want to focus on the design of combinational circuits. s mentioned before, in a combinational circuit the outputs are only dependent on the inputs. Every output can therefore be described as a oolean function of the inputs or to say it even more mathematical, the output vector is a function of the input vector (and only of the input vector). 8 lso called combinatorial circuits Notes on Fundamentals of Computer Engineering 66

68 Combinational Circuit Design Design of combinational circuits in 3 steps = f( E) i = 2 f( E, E... E ) n E E2 Combinational Circuit 2 E n m Figure 37: Combinational Circuit in general Formulate the problem: efore you can design your circuit, the problem has to be brought into the appropriate form. That means that the problem has to be formulated in a way that fits to the structure shown above: a digital output vector that is a function of an digital input vector E.Either write a truth table or a set of boolean functions to describe all the outputs, 2,, n as logical functions of the inputs E,E 2,,E n Minimise the output functions: Use KV Maps, oolean lgebra or (if necessary) a minimisation algorithm (like the Quine-McCluskey algorithm 9 ) to minimize every output function as much as possible Draw the circuit: Find the according circuit to the minimised function choosing the appropriate elements (only NOR gates, only NND gates, mixed gates, two-input gates etc) to meet the requirements (which can be costs, availability, speed etc) Note that this 3-step approach is just the very basics of combinational circuit design. More sophisticated approaches deal with additional requirements like Hazard free design: iming at a circuit that does not produce unwanted glitches as described Minimizing multiple output circuits: In a multiple output circuits there is not only one function to minimise but multiple. In these circuits the total number of gates needed might decrease if parts of the circuitry are used for more than one output. Therefore minimisation has to be done paying attention to similar parts in different output functions Limited Fan In/Fan Out: For technical reason the number of gates that can be connected to either the inputs or outputs of another gate is limited (and varies from gate to gate). This 9 The Quine-McCluskey is a algorithm that can deal with any number of input variables and is often employed within computer programs for digital circuit minimisation. This algorithm is not treated in this course. Notes on Fundamentals of Computer Engineering 67

69 Combinational Circuit Design Design examples asic combinational circuits maximum number(s) needs to be taken into account in every circuit design as dismissing them can lead to unstable or self-destructing circuits. Discussing these problems are not part of this course, but it is important to know that there is much more to the topic as it might seem. Design examples asic combinational circuits This chapter is meant to demonstrate the design principles as well as introducing some of the most basic combinational circuits. Note that these basic circuits are also available as ready-to-use devices, so it is a must to know their hand how to use them. Code Converter We already came to know the importance of representing things numbers, texts etc. ll the representing is done by codes and depending on the actual task, given information usually has to be converted between different codes. This is done by code converters i.e. combinational circuits that output a code word of a code X for any given code word of a code Y. The following example shows the design of a code converter for transforming 4-bit words in iken code to 4-bit words in dual code. Formulation of the problem code conversion can be easily expressed by just listing the code words of both codes that correspond to each other. If the codes are digital codes we just have to order the conversion list to receive a truth table. ctually that usually means putting several truth tables in one as for every input combination we denote the value for more than one output (in this case we have four outputs D to D4, so it is a four-in-one table): Do not bother about how the iken code is defined. For the moment it is just important, that it assigns a different set of binary combinations to the decimal numbers than the dual code. Notes on Fundamentals of Computer Engineering 68

70 Combinational Circuit Design Design examples asic combinational circuits Decimal number iken-code Dual code D D2 D3 D Minimise the output functions Table 8: Conversion table iken Code Dual code To find the minimised functions Di=f(, 2, 3, 4) we use KV-Maps. Please note also that a 4-bit iken code only has code words for the decimal numbers to 9 so there are 6 binary combinations unused, thus there are 6 don t cares. KV Map for D KV Map for D2 x x x x 2 x x 2 4 x 4 x x x x x 3 3 Notes on Fundamentals of Computer Engineering 69

71 Combinational Circuit Design Design examples asic combinational circuits KV Map for D3 KV Map for D4 x x x x 2 x x 2 4 x 4 x x x x x 3 3 Output functions for the code converter are therefore: D = 23 D2 = D3 = 3+ 3 = 3 D4 = 4 Draw the circuit Now we can draw the circuit for the converter: D D 2 D 3 D 4 Figure 38: Circuit for the 4 bit iken-dual Code converter Notes on Fundamentals of Computer Engineering 7

72 Combinational Circuit Design Design examples asic combinational circuits Multiplexer multiplexer is a digital switch that passes the value of on selected input to the output. The values of the control inputs are interpreted as a dual number that specifies, which of the input lines is to be selected. Thus with n control inputs, m=2 n inputs can be controlled: C C2... Cn Controls I I I O I... MUX O... Im Im Figure 39: Multiplexer a) schematic, and b) functionality 4-to- Multiplexer would therefore have 4 inputs and 2 control lines. The according truth table is as below: I I I2 I3 C C2 O X X X X X X X X X X X X X X X X X X X X X X X X Table 9: Truth table of a 4- multiplexer For this circuit there is no simplification possible, so the output function is Demulitplexer O= CCI 2 + CCI 2 + CCI CCI 2 3 Demultiplexer performs the inverse action of a multiplexer : routing one input to one of the m outputs specified by a dual number given with n control lines. Notes on Fundamentals of Computer Engineering 7

73 Combinational Circuit Design Design examples asic combinational circuits C C2... Cn Controls O O I O I MUX O Om Om Figure 4: Demultiplexer a) schematic and b) functionality C C I O O O2 O3 Table 2: Truth table for a -4 Demultiplexer O = CCI O = CCI O2 = CCI O3 = C C I Half dder half adder is a device performing a bit addition i.e. it adds up two bits. In the chapter on binary math it was shown that this addition only has three possible results: + = + = + = In the last case of + we usually say that the sum is with a carry of, so we could write down a truth tables with two inputs and two outputs (sum and carry): Notes on Fundamentals of Computer Engineering 72

74 Combinational Circuit Design Design examples asic combinational circuits S C Table 2: Truth table of a Half dder ( bit addition) Thus the -bit addition can be expressed with the logical functions XOR and ND: S = + = C = Half dder (H) S S C C Full dder full adder is a device that performs a bit addition under respect of an existing carry bit. Therefore it has an additional input for the incoming carry bit. s the addition is commutative, we only have 4 possible results for this addition of three inputs: + + = + + = + + = + + = For the truth table we need of course all 8 input combinations: C in S C out Table 22: Truth table of a Full adder Hence a full adder is equivalent to the logical operations Notes on Fundamentals of Computer Engineering 73

75 Combinational Circuit Design Design examples asic combinational circuits S S = C + C + C + C = ( ) C in in in in in Full adder (F) Cout = + C+ C Cin Cout Figure 4: Full dder (Symbolic) Parallel dder dding bit is not something to go far with. ut half and full adder are just basic devices to build real calculation machines. To realise n bit adders with combinational circuits we have to use a parallel approach one basic adder for every bit. For the least significant bit we get away with a half adder, for every other digit we need to employ a full adder. 3 2 F F F H 3 2 C S3 S2 S S Figure 42: 4 bit Parallel dder Notes on Fundamentals of Computer Engineering 74

76 Flip-Flops Sequential Circuits and Flip-Flops Flip-Flops Sequential Circuits vs. Combinational Circuits The circuits we examined so far were all combinational circuits: the outputs of these circuits are at any time only dependent on the state of the inputs. Now we want to focus on circuits that take into account their own state too. The output of such a sequential circuit is at any time dependent on the state of the input and the actual state of its own output at that time. s a basic structure a sequential circuit consists of a memory part, combinational part and a feedback. It is thereby possible to generate the outputs in the combinational subcircuit or to take the output values from the memories outputs. primary inputs secondary (feedback) inputs combinational logic external outputs memory primary inputs feedback inputs combinational logic memory outputs from memory Figure 43: Sequential circuit: the two basic approaches asically we distinguish synchronous and asynchronous sequential circuits. In synchronous circuits all elements are synchronized by a master clock so that their states change when the clock sends a clock pulse regardless of what the inputs do in the meantime. In asynchronous circuits there is no such master clock pulse so the behaviour of the circuit only depends on the order in which the input signals change. Sequential Circuits and Flip-Flops To remember its state at any time a sequential circuit needs a memory. This memory is realized with flip-flops (sometimes called latches). flip-flop is a bistable device i.e. an element that can stay in one of two logic states until it is called to change its state. asically that means, that there is a input combination to set the flip-flop and the Notes on Fundamentals of Computer Engineering 75

77 Flip-Flops The roots: Set-Reset Flip-Flop (SR flip-flop) flip-flop will remain set when its input changed back to again. To reset the flipflop to there is a second input combination. Usually flip-flops come along with two outputs, one for the its state Q and another one for the complemented state Q. When a flip-flop outputs a at its output Q it is called to be set, if it outputs Q= it is said to be reset. The output Q for a time t2 is a function of the inputs, 2.. m at t2 and the state of Q at the time t <t 2. Thus we denote Q(t+ t) = f(q(t- t), (t), 2 (t).. m (t)) or Q n+ = f(q n,, 2.. m ). In words : ctual output = f(ctual inputs + old output) The truth table for a flip-flop is called transition table, accordingly the characteristic equation is also called the transition equation. The transition equation usually comes along in the form Q n+ = f n (, 2... m ) Q + f 2 (, 2... ) Q m n est thing to understand flip-flops is just to look at the most simple one and see what it does. Therefore we first introduce an unclocked SR flip-flop to clarify the basic concept. Then the principle of a clocked FF is explained. In the next step the other basic flip-flops are presented. The roots: Set-Reset Flip-Flop (SR flip-flop) SR flip-flop (sometimes called RS flip flop as well) has two inputs, as you would never have guessed they are called set and reset. If the set input is given a, the flipflop and its output Q is set to. If the reset input is given a, the flip-flop changes to. If both inputs are, the flip-flop keeps its actual state. S R Q n Q n+ Functionality X X n+ Characteristic equation: Q = S + RQ Table 23: Truth table of a SR flip-flop n with SR = oth inputs are, the state is preserved. The reset input is, the FF is set to. The set input is, the FF is set to The FF s behaviour can not be predicted Notes on Fundamentals of Computer Engineering 76

78 Flip-Flops Clocked Flip-Flops Figure 44: Uncontrolled SR-flip-flop: symbol and one possible realisation Note that for the SR flip-flop the input combination S= and R= is not allowed as it would lead to unpredictable behaviour. With the SR Flip-Flop we have a means to store information i.e. a SR flip-flop can store one bit of information. Therefore it is also called SR latch. The flip-flop as shown above is asynchronous, it changes as soon as the inputs force a change (with only a short time delay t caused by the gates propagation delays). Clocked Flip-Flops Figure 45 shows a clocked SR flip flop where the outputs only react to the inputs during the time when the control input C is. This is an example for a synchronous clocked flip-flop. It is called clocked because in many circuits the control signal is generated periodically by a clock. Even though you should keep in mind, that the clock input is at first a control input that is used to block the inputs: as long as the control signal is the inputs can not influence the outputs. That means that the outputs remain the same it is the inputs that are blocked not the outputs! Just think of the control/clock input as a mask that you put in front of the flip-flop s eyes it just cannot see the inputs. Do not get misled by the input s name it is not necessarily connected to a periodic clock signal. In fact we can use more or less any signal source (e.g. the output of another flip-flop). In this case the flip-flop is asynchronous clocked. C S R Q n+ Functionality X X Q n the output preserves its Inputs disabled state Q n X Inputs enabled SR FF acts as described above Table 24: Transition table of a controlled SR flip-flop The characteristic equations and transitions tables usually do not contain the control input but describe the behaviour for the flip-flop when the inputs are visible. Just for illustration let s have a look at a general transition equation for clocked flipflops: if f c is the characteristic equation of any flip-flop (without clock) then the complete behaviour including the clock input C would be given by Notes on Fundamentals of Computer Engineering 77

79 Flip-Flops Clocked Flip-Flops n+ Q = C f c + CQ n Figure 45: Clocked SR Flip-Flop with NND gates and as graphic symbol Different Types Of Clock Inputs In the preceding section we used a positive clock pulse to trigger the flip-flop (to trigger means to make him react to its inputs. Regarding a typical clock pulse as in Figure 4 it becomes obvious that there are multiple possibilities to trigger the flipflop: we can use the levels or the edges of the clock pulse. Figure 46: Clock pulse s there are always positive and negative levels/edges we end up with four types of clock inputs: Positive level triggered Negative level triggered Raising edge triggered Falling edge triggered Figure 47: Flip-Flops symbols for different types of clock inputs The difference between level triggered and edge triggered flip-flops is illustrated in Notes on Fundamentals of Computer Engineering 78

80 Flip-Flops Jump-and-Kill Flip-Flop (JK Flip-Flop) Figure 48: the level triggered FF goes to one at t 3 because the clock signal is already so it can see the set input S. The edge triggered FF does not recognize the set input at t3 as there is no edge in the clock signal at this time! This edge occurs at t 5 and gives the second flip-flop a chance to have a glance at the set input. S t t 2 t 3 t 4 t 5 R Clock Q positive level Q raising edge Figure 48: Timing diagram for level triggered and edge triggered SR flip-flop Jump-and-Kill Flip-Flop (JK Flip-Flop) The JK flip-flop is a simple enhancement of the SR flip-flop where the state J=K= is not forbidden. It works just like a SR FF where J is serving as set input (sometimes called jump ) and K serving as reset ( kill ). The only difference is that for the formerly forbidden combination J=K= this flip-flop now performs an action: it inverts its state. JK FF can be build using a SR FF as seen in Figure 49. Cl J K Q n+ Functionality X X Q n Disabled Preserve Q n Inputs Preserve Set Reset n Q Toggle Table 25: Truth table of a (controlled) JK flip-flop Characteristic equation: Q n+ = J Q n + K Q n Notes on Fundamentals of Computer Engineering 79

81 Flip-Flops Delay Flip-Flop (D flip-flop) s the behavior of the JK flip-flop is completely predictable under all conditions, this is the preferred type of flip-flop for most logic circuit designs. The RS flip-flop is only used in applications where it can be guaranteed that both R and S cannot be at the same time. Figure 49: JK flip-flop built with an SR flip-flop Delay Flip-Flop (D flip-flop) D flip-flop takes on the value of its input. Thus the input value appears at the output with a delay of td, where td is the propagation delay. D flip-flop is like a SR flip-flop whit R = S - for any input it is either set or reset. The only way to preserve the actual state of a D flip-flop is to disable the input with the control input. Figure 5: D flip-flop from SR flip-flop and D flip-flop (with inverted clock input) Characteristic equation: C D Q n+ Functionality X Q n Disabled Preserve Table 26: Transition table of a D flip-flop Q n + = D Take on input controlled D flip-flop is a bit memory: the value to store is put to the FF s input and FF is enabled. Now the FF s states equals the value we wanted to save. The FF is disabled and the value will be stored until a new value is written to the flip-flop in the same way. Notes on Fundamentals of Computer Engineering 8

82 Flip-Flops synchronous Set and Reset Trigger Flip-Flops (T Flip-Flops) T flip-flop is a JK flip-flop with connected inputs. Therefore it can only toggle or preserve its state. toggle flip-flop only makes sense with a control input, otherwise it would just flip around the whole time and would be a pulse generator but not a real flip-flop. Note that in a synchronous circuit the T input is connected to the J- and K- Input, thus the T input controls if the FF toggles while the clock determines when the FF toggles. In asynchronous circuits the T input is connected to the clock line of the JK FF and the J and K input are set to. Therefore the asynchronous T flipflop toggles as soon as T is set to. Figure 5: Synchronous (a) and asynchronous (b) T flip-flop C T Q n+ Functionality X Q n Disabled Preserve Q n T= Preserve n Q Toggle state Table 27: Transition table for a synchronous T flip-flop T Q n+ Functionality Q n Preserve state n Q Toggle state Table 28: Transition table for an asynchronous T flip-flop Characteristic equation (both): Q + = T Q + T Q = T Q n n n n synchronous Set and Reset In some applications it is necessary to set or reset a clocked flipflop without waiting for the clock. The figure nearby shows a D S D Q flip-flop with an asynchronous preset and reset input. The flipflop s output will be one if S is set, regardless of the values of D CP Q _ R and CP. ccordingly, R set the FF to in any case. Such a flipflop could be seen as a mixture of an unclocked SR FF with a clocked D FF. Its Notes on Fundamentals of Computer Engineering 8

83 Flip-Flops synchronous Set and Reset truth table is shown below C S R D Q n+ Functionality X X Preset FF X X Reset FF X Q n Preserve State X D Take on input Table 29: Function table of a asynchronous D flip-flop Notes on Fundamentals of Computer Engineering 82

84 asic Sequential Circuits Counters asic Sequential Circuits Introduction efore introducing state machines and the general design process for sequential circuits we want to present some of the most basic sequential circuits. The design of these basic circuits can usually be understood intuitively. s they are available as ready-to-use components it is important to not only understand their design but even more their functionality. Counters counter is a sequential circuit that counts. That means it proceeds through a pre-defined sequence of states where the state of the circuit is determined by the states of all its flip flops. s every state of the circuit can be given a number we can say that a counter produces a sequence of numbers. commonly used approach is to interpret a circuits state as dual number, so if flip-flop, and C are all the counter s state is. if is, is and C is the counter s state is 2 = 5 and so on. The most basic counters will simply increment by with every clock pulse, so after state it will go to ; the next pulse will let it switch to etc. It is possible to design counters with any needed counting sequence. Even though asynchronous sequential circuits are not subject of this course the asynchronous counter is presented here exceptionally to give a slight impression on how asynchronous circuits work. synchronous Counter The following example of an asynchronous counter (also called ripple counters ) is build with T flip-flops (which are realised by using JK flip-flops). The flip-flops are falling edge triggered so that the output En is toggled when the output En+ goes from to. Figure 52: synchronous incrementing counter To understand asynchronous circuits we usually have to do a timing diagram first. If we write down the timing diagram for this circuit (Figure 53) and derive the truth table from it (Table 3) we can see, that it is an upward counter. s stated above, the interpretation of the outputs as binary numbers can be done differently; if we read Notes on Fundamentals of Computer Engineering 83

85 asic Sequential Circuits Counters them as a dual number with E4 as MS and E as LS the given circuit is counting dual numbers from to 5. Figure 53: Timing diagram for asynchronous upward counter Clock T E3 E2 E E Number Table 3: State table for the asynchronous upward counter With a slight change the same design can be used to create a backward counter (doing a countdown): the T inputs of the flip-flops are connected to the inverted outputs. Notes on Fundamentals of Computer Engineering 84

86 asic Sequential Circuits Counters Synchronous Counters Figure 54: synchronous backwards counter In a synchronous counter all flip-flops receive the same clock pulse so changes at the outputs appear simultaneously. s in synchronous counters flip-flops are connected serially while being triggered simultaneously they are usually built using Master-Slave flip-flops. Figure 55 shows a synchronous upwards counter that makes use of the fact that any digit of a dual number only toggles in that moment, when all less significant digits are (compare in Table 3 the steps from 3 to 4, 7 to 8 and 5 to ). Toggling an output is done by setting both inputs of a JK flip-flop to, so the upward counting can be done by doing an ND for all less significant bits and feeding the result to both input of the actual digit s flip-flop: 424 Q6 Q5 Q4 CP Q3 Q2 MR Q Q Figure 55: Synchronous upwards counter a) circuit b) symbol for Counter IC 424 s counters are needed all the time they are available as ready-to-use Integrated Circuits. Figure 55.b shows the IC 424, a 7 bit counter. part from the clock input CP it offers a Master Reset pin to reset the counter at any time. The synchronous backward counting is done the same way as with the asynchronous counter: by using the inverted outputs: Figure 56:Synchronous backward counter Counting any Sequence - Counter Design In some applications it might be necessary to have a counter counting something different from just up or down dual numbers. Let s say we want a counter that counts a circular sequence The sequence contains 5 different numbers so we need n=int (log 2 5) + = 3 Flip-Flops. s the highest number is 7, which can be represented with 3 bit, we can interpret the Flip-Flop s outputs E to E2 as dual numbers. The state table in Table 3 lists the desired next states for all possible states of this 3 flip-flop circuit. Notes on Fundamentals of Computer Engineering 85

87 asic Sequential Circuits Counters ctual State Next State Number E 2 E E E + 2 E + E + Number + 4 x x x x x x x x 6 x x x x 7 2 Table 3: State table for a sequence counter Note that some of the state do not have a succeeding state and are treated as don t care. From the state table we read the KV Maps to determine the simplified transitions functions E + i = f( E, E2, E3) for all outputs. KV Map for E + KV Map for E + KV Map for E 2 + E 2 E 2 E 2 x E x x x E x x x E x x E E E E + = EE + E2E E + = E + 2 E + E E + = E 2 These equations tell us, how the next state of every single flip-flop is determined by the actual state of all three flip-flops. In the last step we compare these equations to the flip-flop s characteristic equation to find out, how the outputs have to be fed back to the inputs. In this example JK flip-flops are used: Characteristic Equation for JK FF : Q + = JQ+ KQ E + = E E + E E = ( E + E E ) E + E E E = JE E + KE E J = E + E E = E + E E E 2 2 K = E E = E + E 2 2 Notes on Fundamentals of Computer Engineering 86

88 asic Sequential Circuits Registers E + = E + E + E = ( E + + E ) E + ( E + E ) E = J E + K E J E E E E = K = E + E = E E 2 2 E + = E = E E + E E = J E + K E J K E2 2 E2 2 E2 E2 = E = E The actual counter is shown in Figure 57. E E E 2 J CP K Q _ Q J CP K Q _ Q J CP K Q _ Q Clock Figure 57: Synchronous counter for the sequence Registers With flip-flop we can store data bitwise but usually data does not appear as single bits. Instead it is common to store data words of n bit with typical word lengths of 4, 8, 6, 32 or 64 bit. Thus, several flip-flops are combined to form a register to store whole data words. Registers are synchronous circuits thus all flip-flops are controlled by a common clock line. s registers are often use to collect serial data they are also called accumulators. There exist several types of registers as there are several ways of receiving and sending data. Shift Registers Information often comes bitwise i.e. one bit every clock pulse. To store such data shift registers are used. shift register has one input. Every clock pulse one bit is loaded into the first flip-flop of the register while all the actual flip-flop contents are shifted and the oldest bit got dropped. circuit as in Figure 58 works as a Serial In Serial Out or Serial-In Parallel Out register: data input is done with line D. If the Notes on Fundamentals of Computer Engineering 87

89 asic Sequential Circuits Registers output of all flip-flops (and therefore the register s complete content) are read from the lines Q to Qn the register is used as Serial In Parallel Out (SIPO). typical purpose for such a SIPO register is to collect data that is delivered bitwise and that is needed in n-bit data words (e.g. to convert the signals from serial ports of a computer: the line transports bit a time, the computer uses 8, 6 or 32 bit data words). The same circuit can also be used as Serial In- Serial Out register by exclusively using the rightmost output Qn. Figure 58: Shift register with 4 bit Shifting bits are important for mathematical operations: if the output of the whole register is interpreted as a dual number, shifting by on bit corresponds to multiplying or dividing by 2 (depends on which flip-flop is interpreted as MS). Cyclic Registers Sometimes it is necessary to recycle the same values again and again. Thus the bit that usually would get dropped is feed to the register input again to receive a cyclic serial register. Parallel In Serial Out Figure 59: Cyclic serial shift register s there is a need for serial parallel conversion the inverse operation is equally required. It is done by a Parallel In Serial Out register (PISO) that allows loading data as whole data words and serial shifting. For this operation it needs two control lines: one to trigger the shifting (TS) and one to control when a new data word is loaded to the register (TP). The example circuit in Figure 6 makes use of the flipflop s asynchronous set and reset inputs so that the parallel loading is independent of the shifting clock. Notes on Fundamentals of Computer Engineering 88

90 asic Sequential Circuits Serial dder Figure 6: Parallel In Serial Out register Note that the same circuit can as well be used as Serial In Serial Out by employing the input of the first flip-flop s input. Equally it is possible to wire output lines to the flip-flop s outputs so parallel output is also possible with this kind of circuit it is some kind of an all-star. The IC 435 nearby is a good example for such an universal register: the four bit can be loaded by inputs P to P3, loading is enabled with PE. Pins J 435 P3 Q3 P2 Q2 P Q P Q PE J K CP MR T/C and K are the inputs of the first flip-flop in line and serve as serial input. Serial input & shifting is triggered via the clock input CP. The MR pin can be used to reset the register asynchronously, whereas T/C controls if the outputs appear true or complemented. Serial dder The chapter on combinational circuits already introduced a parallel approach to perform an addition. The disadvantage of the parallel approach was that there was one adder needed for every bit. serial approach only needs one full adder and employs a flip-flop to keep in mind the carry bit. Two shift registers are used to feed the summands bitwise to the serial adder. The first register (accumulator) is additionally used to receive and store the result. control circuit has to make sure, that the appropriate number of shifts is done. serial adder can be used to add data words of any length (the serial adder itself is just the full adder and the flip-flop); only the registers and the control circuit have to be modified appropriately. Notes on Fundamentals of Computer Engineering 89

91 asic Sequential Circuits Serial dder Figure 6: Serial adder Notes on Fundamentals of Computer Engineering 9

92 Finite State Machines (utomata) Mealy and Moore Machines Finite State Machines (utomata) Introduction What is a Finite State Machine? In the section on counters and register we developed simple sequential circuits which was possible due to their regular design. To find a solution for more complex and irregular device it is necessary to employ a way of describing what the system is supposed to do a intermediate step between what we want and how the circuit looks like. This model language is provided by the theory of finite state machines as every sequential circuit is a finite state machine. So what is a finite state machine? finite state machine is a kind of black box' device that responds to external stimuli. Seen from the outside, the device appears as if it can occupy any of a finite number of states. Depending on the current state, a given input causes the device to issue a particular output and then enter a new state. Our FSM's are deterministic in the sense that the current state and the input uniquely determine the output and the new state. Have a closer look at a Flip-Flop and you will realize, that all this is exactly fulfilled by Flip-Flops and the circuit made of them. Even though, do not misinterpret the term the term FSM as being always something physically like a circuit or some steaming monster it is a concept in the first place (FSM s are a quite powerful mean of modelling software too). In the following we only treat synchronous machines (and therefore circuits) as the design of asynchronous circuits (apart from some exceptions) is a very complicated stuff (some people might call it voodoo). Mealy and Moore Machines In the Flip-Flop chapter we always introduced the distinction between sequential circuit by the dependency of the outputs on either states and inputs or states only. In the FSM theory these two types are given the names Mealy and Moore Machines. The Moore Machine The Moore Machine is the one where outputs only depend on the state. That does of course not mean, that the inputs have no influence on the outputs of course the next state depends on the inputs and the actual inputs: From Notes on Fundamentals of Computer Engineering 9

93 Finite State Machines (utomata) State Graphs S n+ = f( I n,s n ) O n = f( S n ) Thus there are two characteristics of the Moore Machine: One State One Output 2 The effect of input changes on the outputs is delayed primary inputs feedback inputs combinational logic memory outputs from memory Figure 62: Moore Machines No direct connections between inputs and outputs The Mealy Machine ccordingly, the Mealy Machine s outputs are functions of the inputs and the state: S n+ = f( I n,s n ) O n+ = f( I n+,s n ) Therefore the characteristics of a (digital) Mealy Machine are One state 2 n possible states (n is the number of inputs) Distinct outputs can be made while the machine is remaining in one state primary inputs secondary (feedback) inputs combinational logic external outputs memory Figure 63: Mealy Machines Outputs are generated according to actual state and actual inputs State Graphs There are two means of describing a Finite State Machine, State Graphs and State Tables. State Graphs (also called State Diagrams) are the medium closest to human perception of what a machine is doing (or meant to do). State graphs are a rather 2 Help your memory: Moore One State = One Output Notes on Fundamentals of Computer Engineering 92