Outline. Introduction to number systems: sign/magnitude, ones complement, twos complement Review of latches, flip flops, counters

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1 Outline Last time: Introuction to number systems: sign/magnitue, ones complement, twos complement Review of latches, flip flops, counters This lecture: Review Tables & Transition Diagrams Implementation Using D Flip-Flops Machine Equivalence Incompletely Specifie Machines Assignment & Coing Schemes Design Example: Assign Coes to s Design Example: Implement Using D flip-flops Design Example: Implement Using T flip-flops CS5 Newton/Pister 8.. Clocke Synchronous Finite- Machines Example: Consier the stuent association coffee vening machine which sells coffee at 5 /cup. The machine will accept nickles, imes, an quarters, one at a time. The coffee release line will be set to true when 5 or more has been put into the machine an the machine will return the correct change. CS5 Newton/Pister 8..2 CS5 Sp 98 R. Newton & K. Pister

2 primary inputs (σ(t)) seconary inputs (q(t)) Definition: Mealy Machine Next- Logic Memory Output Logic l seconary outputs (q(t+)) primary outputs (z(t)) A sequential machine or Mealy Machine can be characterize by the quintuple: M = ( S, Q, Z,, l) where S = finite non-empty set of input symbols σ, σ2,..., σi Q = finite non-empty set of states q, q2,..., qn Z = finite non-empty set of output symbols z, z2,..., zm = next-state function, which maps Q S fi Q l = the output function, which maps Q S fi Z CS5 Newton/Pister 8..3 primary inputs (σ(t)) seconary inputs (q(t)) Definition: Moore Machine Next- Logic Memory Output Logic l seconary outputs (q(t+)) primary outputs (z(t)) A sequential machine is sai to be of the Moore type (Moore Machine ) if its output function is a function only of its states (i.e. l : Q fi Z) Every Mealy Machine can be converte to a Moore Machine an vice versa. If the Memory is clocke, the machines are Clocke, Synchronous Mealy an Moore machines respectively. CS5 Newton/Pister 8..4 CS5 Sp 98 R. Newton & K. Pister 2

3 Design Example: Inputs, Outputs an s Example: Consier the stuent association coffee vening machine which sells coffee at 5 /cup. The machine will accept nickles, imes, an quarters, one at a time. The coffee release line will be set to true when 5 or more has been put into the machine an the machine will return the correct change. Input S = { 5,, 25 } M = ( S, Q, Z,, l ) Sequential Machine Output Z = { D, R, R5, R, R5, R2 } Q = { q, q5, q } CS5 Newton/Pister 8..5 Next- an Output Functions /Output table ( symbol roppe for clarity): q\s 5 25 q q5,d q,d q,r q5 q,d q,r q,r5 q q,r q,r5 q,r2 Input q Next, Output q5 q q 5/D q5 CS5 Newton/Pister Means that upon the insertion of 5, when the machine is in state q, it will go to state q5, the coffee will not be release an no change ( ) will be returne CS5 Sp 98 R. Newton & K. Pister 3

4 How About a Moore Machine? Input S = { 5,, 25 } Next- Logic Memory Output Logic l Output Z = { D, R, R5, R, R5, R2 } Q = { q, q5, q, } CS5 Newton/Pister 8..7 Input /Output Transition Table an Transition Diagram: Moore Machine q\s 5 25 z q q5 q q25 D q5 q q5 q3 D q q5 q2 q35 D q5 q5 q q25 R q2 q5 q q25 R5 q25 q5 q q25 R q3 q5 q q25 R5 q35 q5 q q25 R2 q/d q5/r q5/d q/d q2/r5 q3/5 Next Output q25/r q35/2 CS5 Newton/Pister 8..8 CS5 Sp 98 R. Newton & K. Pister 4

5 Conversion to Mealy Machine Input q\s 5 25 q q5,d q,d q25,r q5 q q,d q5,r q3,r5 q5,r q2,r5 q35,r2 q5 q5,d q,d q25,r q2 q5,d q,d q25,r q25 q5,d q,d q25,r q3 q5,d q,d q25,r q35 q5,d q,d q25,r Next, Output CS5 Newton/Pister 8..9 Machine Equivalence Let qa an qb be two states of machines Ma an Mb respectively. s qa an qb are sai to be equivalent iff, starting with qa an qb, for any sequence of input symbols applie to the two machines, the output sequences are ientical. If qa an i are not ientical, they are sai to be istinguishable. Let Ma an Mb be two sequential machines. Ma an Mb are sai to be eqivalent iff for every state of Ma there exists at least one equivalent state in Mb, an vice versa. Similarly, if Ma an Mb are not equivalent we say they are istinguishable. Two states qa an qb are equivalent if: () qa an qb prouce the same output values (for Mealy machines, they must prouce the same outputs for all legal input conitions). (2) For each input combination, qa an qb must have the same next state, or equivalent next states. CS5 Newton/Pister 8.. CS5 Sp 98 R. Newton & K. Pister 5

6 Minimization of Completely-Specifie Machines Two states are sai to be k-equivalent if, when excite by an input sequence of k symbols, yiel ientical output sequences. The machine can be partitione by this k-equivalence relation into k-equivalence classes. For any n-state machine, there can be at most (n-) successive, istinct partitions. For any n-state machine, these equivalence classes contain one an only one unique state. To minimize a completely-specifie machine: () Fin the -equivalence classes, 2-equivalence classes, etc. until the k+ equivalence classes are the same as the K equivalence classes, then stop. (2) Combine all the states in the same class into a single state. If the machine has m equivalence classes, the machine has m states. CS5 Newton/Pister 8.. Design Example: Minimization q \ s partition q q5,d q,d q25,r I q5 q,d q5,r q3,r5 II q q5,r q2,r5 q35,r2 III q5 q5,d q,d q25,r I q2 q5,d q,d q25,r I q25 q5,d q,d q25,r I q3 q5,d q,d q25,r I q35 q5,d q,d q25,r I CS5 Newton/Pister 8..2 CS5 Sp 98 R. Newton & K. Pister 6

7 Design Example: Minimization -partition q \ s partition q q5,d q,d q25,r q5 q5,d q,d q25,r I q2 q5,d q,d q25,r q25 q5,d q,d q25,r q3 q5,d q,d q25,r q35 q5,d q,d q25,r II q5 q,d q5,r q3,r5 III q q5,r q2,r5 q35,r2 CS5 Newton/Pister 8..3 Assignment q\s 5 25 q q5,d q,d q,r q5 q,d q,r q,r5 q q,r q,r5 q,r2 We must assign coes to symbolic values. Coes for input an output symbols are usually "given" so we must etermine coes for the state symbols. This process is calle state assignment or state coing. If binary storage elements are use we nee: Ølog2(N s )ø < N m < N s CS5 Newton/Pister 8..4 CS5 Sp 98 R. Newton & K. Pister 7

8 Design Example: Assignment Minimum-Length Coe For this example, 2 < N m < 3. If we choose N m = 2, an assign coes ranomly, then we have the state table: q\σ 5 25,D,D,R,D,R,R5,R,R5,R2??,????,????,?? unuse state CS5 Newton/Pister 8..5 Implementation Using D Flip-Flops Can use positive-ege-triggere D flop-flop irectly to implement storage element: Input S = { 5,, 25 } Next- Logic D Q CLK D Q Output Logic l Output Z = { D, R, R5, R, R5, R2 } CLK D Q CLK CLK Q = {,,} CS5 Newton/Pister 8..6 CS5 Sp 98 R. Newton & K. Pister 8

9 Design Example: Assignment One-Hot Coe For this example, 2 < N m < 3. If we choose N m = 3, an assign coes ranomly but where exactly one bit of the coe is "" for each vali state, then we have the state table: q\s 5 25,D,D,R,D,R,R5,R,R5,R2???,?????,?????,?????,?????,?????,?????,?????,?????,?????,?????,?????,?????,?????,?????,?? unuse states CS5 Newton/Pister 8..7 Steps to FSM Design Construct a state/output table from the wor escription (or a state graph). Minimization: Minimize the number of states (usually helps). Assignment: Coose a set of state variables an assign coes to name states. Substitute the state-variable combinations into the state/output table to create a transition/output table that shows the esire next-state variable combination for each state/input combination. Choose a flip-flop type (e.g. D, J-K, T) for the state memory. Construct an excitation table that shows the excitation values require to obtain the esire next-state value for each state/input combination. Derive excitation equations from excitation table. Derive output equations from transition/output table. Draw logic iagram that shows combinational next-state an output functions as well as flip-flops. CS5 Newton/Pister 8..8 CS5 Sp 98 R. Newton & K. Pister 9

10 Minimization Using an Implication Table Buil a compatibility checking table in a laer shape, as shown, an label each row q2, q3,... qn an column q, q2, qn- (no nee for iagonal). b q\s z a b c e f g h c f h e a e c a f b b h c g c e f g h a b c e f g CS5 Newton/Pister 8..9 Minimization Using am Implication Table: Summary of Approach Construct an implication table which contains a square for each pair of states. Label each row q2, q3,... qn an column q, q2, qn- (no nee for iagonal). Compare each each pair of rows in the state table. If the outputs associate with states i an j are ifferent, put an in square i-j to inicate that i j (trivial non-equivalence). If the outputs an the next states are the same, put a in square i-j to inicate i j (trivial equivalence). In all other squares, put state-pairs that must be equivalent if states i-j are to be equivalent (if the next states of i an j are m an n for some input σ, then m-n is an implie pair an goes in square i-j). Go through the non- an non- squares, one at a time. If square i-j contains an implie pair an square m-n contains an, then i j so put an in i-j as well. If any 's were ae in the last step, repeat it until no more 's are ae. For each square i-j which not containing an, i j. CS5 Newton/Pister 8..2 CS5 Sp 98 R. Newton & K. Pister

11 Implication Table Example: Pass q\s z a b c e f g h c f h e a e c a f b b h c g b c e f g h -f c-h c-e b- c-h a-f e-h b-f a- e-f b- c-e -g a-b e-h c-f a-b a-g c-f b-g a b c e f g CS5 Newton/Pister 8..2 Implication Table Example: Pass an Pass 2 b c -f c-h c-e a-f e-h b c -f c-h c-e a-f e-h e f g h b- c-h b-f a- e-f b- c-e -g a-b e-h c-f a-b a-g c-f b-g a b c e f g e f g h b- c-h b-f a- e-f b- c-e -g a-b e-h c-f a-b a-g c-f b-g a b c e f g CS5 Newton/Pister CS5 Sp 98 R. Newton & K. Pister

12 Implication Table Example: Final Table q\s z a b c f g h c f h c a f b b h c g CS5 Newton/Pister Steps to FSM Design Construct a state/output table from the wor escription (or a state graph). Minimization: Minimize the number of states (usually helps a bit). Assignment: Coose a set of state variables an assign coes to name states. Substitute the state-variable combinations into the state/output table to create a transition/output table (next-state table) that shows the esire next-state variable combination for each state/input combination. Construct next-state K-maps as neee. Choose a flip-flop type (e.g. D, J-K, T) for the state memory. Construct an excitation table that shows the flip-flop input excitation values require to obtain the esire next-state value for each state/input combination. Derive flip-flop excitation equations from excitation table. Derive output equations from transition/output table. Draw logic iagram that shows combinational next-state an output functions as well as flip-flops. CS5 Newton/Pister CS5 Sp 98 R. Newton & K. Pister 2

13 Guielines for Assignment The iea of the following heuristics is to try to get the 's together (in the same implicant) on the flip-flop input maps. This metho oes not apply to all problems an even when it is applicable it oes not guarantee a minimum soultion. s which have the same next state, for a given input, shoul be given ajacent assignments ("fan-out oriente"). s which are the next states of the same state shoul be given ajacent assignments ("fan-in oriente"). Thir priority, to simplify the output function, states which have the same output for a given input shoul be given ajacent assignments (this will help put the 's together in the output K- maps; "output oriente"). / b a / / c / / e / f / / {a,b}; {,e}; {c,f} CS5 Newton/Pister But How Do You Actually Do It? Write own all of the states that shoul be given ajacent assignments accoring to the criteria above ("assignment constraints", or "face embeing constraints.") Then, using a Karnaugh-map, try to satisfy as many of them as possible (or use a computer program which oes it: Kiss, Nova, Mustang, Jei). Some guielines to help are: Assign the starting state to the "" square on the map (picking a ifferent square oesn't help, since all squares have the same number of ajacencies an it's easier to reset to ""). Fanout-oriente guielines an ajacency conitions require more than once shoul be satisfie first. When guielines require that 3 or 4 states be ajacent, these states shoul be place within a group of 4 on the assignment map. If there are only a few outputs, the output guieline shoul be applie last. If there are lots of outputs an only a few states, then give more weight to the thir guieline. CS5 Newton/Pister CS5 Sp 98 R. Newton & K. Pister 3

14 Assignment: Design Example q \ s q q, q2, q q3, q2, q2 q, q4, q3 q5, q2, q4 q, q6, q5 q5, q2, q6 q, q6, Consier the state table opposite: Guieline : {q,q2,q4,q6} since all have q as next-state with input. Similary {q,q,q3,q5}; {q3,q5}; {q4,q6}. Guieline 2: {q,q2} since nextstates of q. Similarly {q2,q3}; {q,q4}; {q2,q5} twice; {q,q6} twice. Guieline 3: woul not be worth using here. We alreay have a lot of constraints an their is only one output, mostly. CS5 Newton/Pister Assignment: Design Example Given the ajacency constraints: : {q,q2,q4,q6}; {q,q,q3,q5}; {q3,q5}; {q4,q6}. 2: {q,q2}; {q2,q3}; {q,q4}; {q2,q5} twice; {q,q6} twice. Choose number of flip-flops: 6 states so nee at least 3 an no more than 6. Try with 3 -A, B, C say. Task is now to choose assignment of 3-bit (ABC) state coes to q-q6 so that as many of the above constraints as possible are satisfie, in the orer state earlier. AB A C B AB A C q q2 q q q6 q4 q5 q B q q3 q2 q q q6 5 CS5 Newton/Pister CS5 Sp 98 R. Newton & K. Pister 4

15 Assignment: Design Example Assignments achieve by trial-anerror (question: woul we have been able to satisfy more constraints using 4 flip-flops instea of 3?). Top assignment leas to coes: q =, q =, q2 =, q3 =, q4 =, q5 =, q6 = Now we can construct the next-state maps for the assignment. {q,q2,q4,q6} sa BC q q q 3 * 4 q q5 q2 q5 q {q3,q5} * q2 q2 {q,q3,q5} q2 q4 q6 8 9 q6 {q4,q6} CS5 Newton/Pister Steps to FSM Design Construct a state/output table from the wor escription (or a state graph). Minimization: Minimize the number of states (usually helps a bit). Assignment: Coose a set of state variables an assign coes to name states. Substitute the state-variable combinations into the state/output table to create a transition/output table (next-state table) that shows the esire next-state variable combination for each state/input combination. Construct next-state K-maps as neee. Choose a flip-flop type (e.g. D, J-K, T) for the state memory. Construct an excitation table that shows the flip-flop input excitation values require to obtain the esire next-state value for each state/input combination. Derive flip-flop excitation equations from excitation table. Derive output equations from transition/output table. Draw logic iagram that shows combinational next-state an output functions as well as flip-flops. CS5 Newton/Pister 8..3 CS5 Sp 98 R. Newton & K. Pister 5

16 Guielines for Determining Flip-Flop Input Equations from Next- Map Qn = Qn = Rules for forming input map from nextstate map (2) Type Input D T EN S-R S R J-K J K Qn+= Qn+= * * * Qn+= Qn+ = * * * Qn = half no change no change Qn = half no change complement no change replace s with *s replace s with *s complement no change fill in with *s fill in with *s complement Notes: () * = "on't care" (2) Always copy *s from next-state map to input map first (3) For S, Qn= half an R, Qn= half, fill remaining entries with s. CS5 Newton/Pister 8..3 Flip-Flop Input Equations From Next- Map: Example AB Qn * AB Qn * AB Qn * Qn+ next-state map D input map T input map AB AB Qn Qn S * * * * * * J CS5 Newton/Pister AB Qn R * * * 5 S-R input map AB Qn * * * 2 6 * * 5 J-K input map K CS5 Sp 98 R. Newton & K. Pister 6

17 Next- Maps: Design Example Choose flip-flop types: D flip-flops Recall assignments: q =, q =, q2 =, q3 =, q4 =, q5 =, q6 = Construct D input maps from next-state map, substituting state coes. A BC * * A BC * 4 7 * sa BC 3 * 4 5 * An+ Bn+ Cn+ CS5 Newton/Pister Steps to FSM Design Construct a state/output table from the wor escription (or a state graph). Minimization: Minimize the number of states (usually helps a bit). Assignment: Coose a set of state variables an assign coes to name states. Substitute the state-variable combinations into the state/output table to create a transition/output table (next-state table) that shows the esire next-state variable combination for each state/input combination. Construct next-state K-maps as neee. Choose a flip-flop type (e.g. D, J-K, T) for the state memory. Construct an excitation table that shows the flip-flop input excitation values require to obtain the esire next-state value for each state/input combination. Derive flip-flop excitation equations from excitation table. Derive output equations from transition/output table. Draw logic iagram that shows combinational next-state an output functions as well as flip-flops. CS5 Newton/Pister CS5 Sp 98 R. Newton & K. Pister 7

18 Next- Maps: Summary of Example Nee 6 gates an 3 gate-inputs to implement the machine using this assignment. Straight binary assignment (q=, q=, etc.) woul yiel gates an 39 gate-inputs. The approach gave goo results in this example, but that is not always the case. CS5 Newton/Pister Derive Output Equations from Output Maps A BC 3 * * Output map from Transition/Output Table CS5 Newton/Pister CS5 Sp 98 R. Newton & K. Pister 8

19 Steps to FSM Design Construct a state/output table from the wor escription (or a state graph). Minimization: Minimize the number of states (usually helps a bit). Assignment: Coose a set of state variables an assign coes to name states. Substitute the state-variable combinations into the state/output table to create a transition/output table (next-state table) that shows the esire next-state variable combination for each state/input combination. Construct next-state K-maps as neee. Choose a flip-flop type (e.g. D, J-K, T) for the state memory. Construct an excitation table that shows the flip-flop input excitation values require to obtain the esire next-state value for each state/input combination. Derive flip-flop excitation equations from excitation table. Derive output equations from transition/output table. Draw logic iagram that shows combinational next-state an output functions as well as flip-flops. CS5 Newton/Pister CS5 Sp 98 R. Newton & K. Pister 9

Chapter 5 Synchronous Sequential Logic

Chapter 5 Synchronous Sequential Logic Chih-Tsun Huang ( 黃稚存 ) http://nthucad.cs.nthu.edu.tw/~cthuang/ Department of Computer Science National Tsing Hua University Outline Introduction Storage Elements: