Efficient Building Blocks for Reversible Sequential

Size: px

Start display at page:

Download "Efficient Building Blocks for Reversible Sequential"

Kevin Douglas
5 years ago
Views:

1 Effiient Building Bloks for Reversile Sequentil Ciruit Design Siv Kumr Sstry Hri Shym Shroff Sk. Noor Mhmmd V. Kmkoti Reonfigurle nd Intelligent Systems Engineering Group, Deprtment of Computer Siene nd Engineering, Indin Institute of Tehnology, Mdrs, Chenni , Indi. Emil: km@s.iitm.ernet.in Telephone: (9) , Fx: (9) Astrt- Reversile logi is gining interest in the reent pst due to its less het dissipting hrteristis. It hs een proved tht ny Boolen funtion n e implemented using reversile gtes. In this pper we propose set of si sequentil elements tht ould e used for uilding lrge reversile sequentil iruits leding to logi nd grge redution y ftor of 2 to 6 when ompred to existing reversile designs reported in the literture. Keywords: Reversile Logi, Reversile Gte, Power Dissiption, Flip-Flop, Grge. I. INTRODUCTION Energy dissiption is eoming mjor rrier in the evolving nno-omputing er. As reversile logi ensures low energy dissiption [] [2] it hs gined importne in the reent pst. An opertion is sid to e physilly reversile if there is no energy to het onversion nd no hnge in entropy. On sme lines, reversile logi omputtion implies tht no informtion out the omputtionl stte n ever e lost. R. Lnduer [3] hs shown tht for every it of informtion tht is ersed during n irreversile logi omputtion ktln2 joules of het energy is generted, where k is the Boltzmnn onstnt nd T is the temperture in kelvin t whih the system is operting. C. H. Bennett [] showed tht the ktln2 mount of energy dissiption would not our if omputtion is rried out in reversile wy. A reversile gte is logil ell tht hs the sme numer of inputs nd outputs with ijetive mpping etween the input nd output vetors. Diret fn-outs from the reversile gte nd feedks from gte output diretly to its inputs re not permitted. A reversile gte with n-inputs nd n- outputs is lled n x n reversile gte. An elorte list of reversile gtes studied in the literture is presented in [5]. Some prominent mong them re the Feynmn gte [6] (Figure ()), the Toffoli Gte [7] (Figure ()), the Fredkin gte [8] (Figure ()), the Kerntopf gte [5] nd the Mrgolus gte [9]. Some of the prominent CMOS-sed implementtion tehniques for reversile iruits reported in the literture inlude the Chrge Reovery Logi (CRL) [], the Split-Level Chrge Reovery Logi (SCRL) [], the Reversile Energy Reovery () () () ED Fig.. Reversile Gtes: () Feynmn () Toffoli () Fredkin Logi (RERL) iruits [2] [3] nd the nmos Reversile Energy Reovery Logi (nrerl) []. In ddition, optoeletroni nd nnoeletroni implementtions of reversile gtes were lso found in the literture [5] [6]. There is reltively little progress in the synthesis of reversile gtes. A omprehensive survey of synthesis tehniques for reversile logi long with inry deision digrm-sed inrementl lgorithm for reversile logi synthesis is presented in [7]. An importnt metri for evluting reversile iruits is the Grge ount. Grge is defined s the numer of outputs dded to mke n n-input k-output Boolen funtion ((n, k) funtion) reversile [8]. Hene, one of the mjor issues in designing reversile iruit is grge minimiztion. II. AN UNIVERSAL REVERSIBLE GATE In this setion we propose new universl reversile logi gte s shown in Figure 2. The truth tle for the sme s shown in Tle I, implies ijetive mpping etween the input nd output vetors. Hene, the gte is reversile. It is esy to infer from Figure 2 tht y setting input to logi, the AND nd OR funtions of nd re relized t outputs oi nd 3 respetively. Similrly, y setting input to logi, the NAND nd NOR funtionlities n e relized. There re ertin importnt dvntges of this new gte /6/$2. 26 IEEE. 37

2 It hs een proved tht relizing oth NOR nd NAND funtionlities on the sme reversile gte is dvntgeous for synthesizing multivlued reversile logi [5]. Aprt from this, the gte proves to e very hndy for designing sequentil elements like the RS lth s disussed in the following setions. In the rest of this pper URG will denote the proposed reversile gte shown in Figure 2. Proposed Design Existing Design 2 2 Improvement ftor 2 2 TABLE II COMPARISON OF PROPOSED RS LATCH WITH - C Fig. 2. f(+) ED() The New Gte (G) The dvntge of using URG is tht we n design oth the NAND Lth nd NOR Lth using the sme si unit. The existing design did not utilize the sme output oming out of the reversile gte. Insted they were expliitly produing n dditionl fn-out y using n extr reversile gte mking the iruit omplex nd ostly. The omprison of the proposed design nd the existing design is shown in Tle II o l o 2 O 3 S- () () TABLE I TRUTH TABLE NEW GATE (G) III. REVERSIBLE SEQUENTIAL CIRCUITS Very little previous reserh hs een done on designing sequentil iruits using reversile logi. Synthesis of sequentil iruits is very different from tht of omintionl iruits. The diffiulty rise from the ft tht sequentil iruits require feedk from one of the outputs nd reversile logi gtes do not llow fn-out of more thn one. The most reently reported work [9] in this topi fouses on the onstrution of reversile sequentil iruits y repling the irreversile gtes of norml irreversile sequentil iruit with the pproprite reversile gtes. The study did not fous on the optimiztion in terms of logi gtes nd grge minimiztion. In this pper we propose set of si sequentil elements tht ould e used for uilding lrge reversile sequentil iruits leding to logi nd grge redution y ftor of 2 to 6 when ompred to those proposed in [9]. IV. RS LATCH In this setion we propose reversile iruit designs for RS Lth. The NOR Lth iruit is shown in Figure 3(). Eh NOR gte is repled with URG nd the iruit design is shown in Figure 3(). The iruit shown in Figure 3() is si NAND Lth. The reversile NAND Lth design using the Toffoli gte is shown in Figure 3(e) nd the design using URG is shown in Figure 3(d). () Fig. 3. Lthes () NOR () Reversile NOR () NAND (d) Reversile NAND (e) Reversile NAND lth using toffoli Q V. D FLIP-FLOP In this setion we design reversile positive level triggered D Flip-Flop. The truth tle of D Flip-Flop is shown in Tle III. The design of the D Flip-Flop is shown in Figure. A Fredkin gte is used s 2: mux nd the Feynmn gte is used for getting fn-out of 2. Similrly, we design negtive level triggered D Flip-Flop. The design of the negtive level triggered D Flip-Flop is shown in Figure 5. The power of the Fredkin gte tht it n t s 2: mux for oth the selet nd the NOT of selet t the (d) 38

3 enle d Q x Q(t-l) TABLE III POSITIVE LEVEL TRIGGERED DATA FLIP-FLOP enle j k Q no-hnge Toggle x x no-hnge TABLE V POSITIVE LEVEL TRIGGERED JK FLIP-FLOP Fig.. Reversile positive level triggered D Flip-Flop sme time hs een exploited. The proposed design requires less numer of logi gtes nd the grge generted is lso lesser s ompred to the older designs. Tle IV ompres the proposed design nd the existing design. If we design the D Flip-Flop y using the design of the RS nd y setting R nd S vlues ppropritely we inur lrge omplexity in the iruit, hene we hve designed the iruit from the logi nd did not extend the design of RS Lth. VI. JK FLIP-FLOP In this setion we design reversile level triggered JK Flip- Flop. The truth tle for JK Flip-Flop is shown in Tle V. From the truth tle we see tht the JK Flip-Flop is sme s D Flip-Flop with D = JQ + KQ. By oserving the formul JQ + KQ we see tht it is 2: mux with inputs s J nd K nd selet line s Q. Hene, we ple Fredkin gte nd Feynmn gte for getting NOT of K. The design of positive level triggered JK Flip-Flop is shown in Figure 6. Similrly, we n design negtive level triggered JK Flip-Flop. The proposed designs require less numer of logi gtes ompred to older designs nd the grge generted y the proposed design is lso muh less thn the existing design. Tle VI ompres the proposed design nd the existing design. If we design the JK Flip-Flop y using the design of Fig. 5. Reversile negtive level triggered D Flip-Flop Proposed Design 2 2 Existing Design 7 8 Improvement ftor 3.5 TABLE IV COMPARISON OF PROPOSED D FLIP-FLOP WITH Proposed Design Existing Design 2 Improvement ftor TABLE VI COMPARISON OF PROPOSED JK FLIP-FLOP WITH the RS nd y setting R nd S vlues ppropritely we inur lrge omplexity in the iruit. Hene we hve designed the iruit from the logi nd did not extend the design of RS Lth. K - Enle o Feynmn J Fredkin Fredkin Fredkin ~~~K Fig. 6. Reversile positive level triggered JK Flip-Flop VII. LQ T FLIP-FLOP In this setion we design reversile level triggered T Flip-Flop. From the truth tle of T Flip-Flop (Tle VII) we n sy tht the T Flip-Flop is sme s D Flip-Flop with D = T+ Q. Hene, y utilizing the effiient design of D Flip-Flop we onstrut T Flip-Flop y dding the funtionlity to D. The XOR funtionlity is dded y single Feynmn gte. The design of positive level triggered T Flip-Flop is shown in Figure 7. Similrly, we n design negtive level triggered T Flip-Flop. The proposed design requires lesser numer of logi gtes nd the grge generted is lso less s ompred to the existing design. Tle VIII ompres the proposed design nd the existing design. enle t Q(t -) Q I xi x IIno-hngeI TABLE VII POSITIVE LEVEL TRIGGERED T FLIP-FLOP 39

4 TfQ Fig. 7. Reversile positive level triggered T Flip-Flop Proposed Design Existing Design Improvement ftor 5.66 TABLE X COMPARISON OF PROPOSED MASTER-SLAVE D FLIP-FLOP WITH Proposed Design 3 2 Existing Design 2 Improvement ftor TABLE VIII COMPARISON OF PROPOSED T FLIP-FLOP WITH Clok j k Q pos -edge no-hnge pos-edge pos-edge pos-edge Toggle neg-edge x x no-hnge TABLE XI POSITIVE EDGE TRIGGERED JK FLIP-FLOP VIII. MASTER-SLAVE D FLIP-FLOP In this setion we propose the onstrution of Mster- Slve edge triggered D Flip-Flop using reversile gtes. The onstrution of the mster-slve D Flip-Flop is shown in Figure 8. The truth tle of the positive edge triggered D Flip- Flop is shown in Tle IX. It n e esily verified tht the onstrutions meets the desired hrteristis of the positive edge triggered D Flip-Flop. Similrly, we n onstrut the negtive edge triggered D Flip-Flop. There is no expliit mention of the reversile edge triggered D Flip-Flop. If we do the nive onstrution y repling every irreversile gte y pproprite reversile gte, then the numer of gtes in the design will e 6 nd the grge outputs will e 7. The omprison is shown in the Tle X. IX. MASTER-SLAVE JK FLIP-FLOP In this setion we propose the onstrution of Mster-Slve JK Flip-Flop using reversile gtes. The truth tle is shown in Tle XI. The design is shown in the Figure 9. We dded Fredkin gte nd Feynmn gte to get the funtionlity of JQ + KQ. The omprison of the proposed design with the existing ones is shown in the Tle XII. Clok X. MASTER-SLAVE T FLIP-FLOP In this setion we propose the onstrution of Mster-Slve T Flip-Flop using reversile gtes. The truth tle is shown in the Tle XIII. The design is shown in the Figure. We dded Feynmn gte to get the desired funtionlity of TeQ. The omprison of the proposed design with the existing ones is shown in the Tle XIV. There is no expliit mention of the reversile edge triggered T Flip-Flop. If we do the nive onstrution y repling every irreversile gte y pproprite reversile gte, then the numer of gtes in the design nd the grge outputs will e 8. The omprison is shown in the Tle XIV. XI. CONCLUSIONS The pper proposed the design of new reversile logi gte whih is shown to e dvntgeous for synthesizing multivlued reversile logi [5]. The proposed reversile gte is utilized for effiiently designing the RS lth. The pper proposes the designs of the reversile Flip-Flops nd Lth using the proposed gte, Fredkin gte, Toffoli gte Proposed Design 6 6 Existing Design 8 2 Improvement ftor D Fig. 8. Reversile positive edge triggered D Flip-Flop Clok d Q (t) pos-edge pos-edge neg-edge x Q(t- ) TABLE IX POSITIVE EDGE TRIGGERED DATA FLIP-FLOP TABLE XII COMPARISON OF PROPOSED MASTER-SLAVE JK FLIP-FLOP WITH Clok T Q (t) pos-edge Q(t l) pos-edge Q(t- ) neg-edge x - Q(t- ) TABLE XIII POSITIVE EDGE TRIGGERED T FLIP-FLOP

5 K Q Fig. 9. Reversile positive edge triggered JK Flip-Flop Fig.. Reversile positive edge triggered T Flip-Flop Proposed Design 5 3 Existing Design 8 8 Improvement ftor TABLE XIV COMPARISON OF PROPOSED MASTER-SLAVE T FLIP-FLOP WITH nd the Feynmn gte. The designs re ompred with the existing design nd re shown to e hve n improvement y ftor of 2 to 6. The proposed designs utilized the ft tht the reversile iruits onstruted from the logi re etter in terms of logi omplexity nd grge minimiztion thn the one otined y onverting the irreversile designs y repling gtes ppropritely. The proposed designs re highly optimized. The numer of grge outputs generted nd the numer of gtes used in the designs re very smll s ompred to the erlier implementtions. REFERENCES [] R. W. Keyes nd R. Lnduer, "Miniml energy dissiption in logi," IBM J. Reserh nd Development, pp , Mrh 97. [2] C. H. Bennett, "Notes on the history of reversile omputtion," IBM J. Reserh nd Development, vol. 32, pp. 6-23, Jnury 988. [3] R. Lnduer, "Irreversiility nd het genertion in the omputing proess," IBM J. Reserh nd Development, vol. 3, pp. 83-9, July 96. [] C. H. Bennett, "Logil reversiility of omputtion," IBM J. Reserh nd Development, pp , Novemer 973. [5] P. Kemtopf, "Synthesis of multipurpose reversile logi gtes," Euromiro Symposium on Digitl System Design (DSD'2), pp , 22. [6] R. Feynmn, "Quntum mehnil omputers," Optis News, vol., pp. -2, 985. [7] T. Toffoli, "Reversile omputing," Automt, Lnguges nd Progrmming, pp , 98. [8] E. Fredkin nd T. Toffoli, "Conservtive logi," Int'l Journl of Theoretil Physis, vol. 2, pp , 982. [9] N. Mrgolus, "Physis nd omputtion," Ph. D. Thesis, Msshusetts Institute of Tehnology, Cmridge, MA, 988. [] S. G. Younis nd T. F. Knight, "Prtil implementtion of hrge reovering symptotilly zero power mos," Proeeding of the 993 symposium on Reserh on integrted systems, MIT press, pp , 993. [], "Asymptotilly zero energy split-level hrge reovery logi," Pro. Workshop Low Power Design, Np Vlley Cliforni, pp , 99. [2] J. Lim, K. Kwon, nd S.-I. Che, "Reversile energy reovery logi iruit without non-diti energy loss," Eletroni Letters, vol. 3, No., pp. 3-36, Ferury 998. [3] J. Lim, D.-G. Kim, nd S.-I. Che, "Reversile energy reovery logi iruits nd its 8-phse loked power genertor for ultr-low-energy pplitions," IEICE Trns. Eletron, vol. E82-C, No., pp , April 999. [], "nmos reversile energy reovery logi for ultr-low-energy pplitions," IEEE Journl of Solid-Stte Ciruits, vol. 35, No.6, pp , June 2. [5] P.Piton, "Optoeletroni multi-vlued onservtive logi," Int. Journl of Optil Computing, vol. 2, pp. 9-29, 99. [6] S. Bndyopdhyy, "Nnoeletri implementtions of reversile nd quntum logi," Supperltties nd Mirostrutures, vol. 23, pp. 5-6, 998. [7] P. Kemtopf, "A new heuristi lgorithm for reversile logi synthesis," Design Automtion Conferene, (DAC 2), pp , 2. [8] D. Mslov nd G. W. Duek, "Grge in reversile design of multiple output funtions," In 6th Interntionl Symposium on Representtions nd Methodology of Future Computing Tehnologies, pp. 62-7, Mrh 23. [9] H. Thpliyl nd M. Srinivs, "A eginning in the reversile logi synthesis of sequentil iruits," MAPLD Interntionl Conferene, Septemer 25.

Hierarchical Reversible Logic Synthesis Using LUTs

Hierarchical Reversible Logic Synthesis Using LUTs Hierrhil Reversile Logi Synthesis Using LUTs Mthis Soeken Mrtin Roetteler Nthn Wiee Giovnni De Miheli Integrted Systems Lortory, EPFL, Lusnne, Switzerlnd Mirosoft Reserh, Redmond, WA, USA ABSTRACT Tody