DIGITAL ELECTRONICS & it0203 Semester 3

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1 DIGITAL ELECTRONICS & it0203 Semester 3 P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur School of Computing, Department of IT 8/22/20

2 Disclaimer The contents of the slides are solely for the purpose of teaching students at SRM University. All copyrights and Trademarks of organizations/persons apply even if not specified explicitly. School of Computing, Department of IT 8/22/20 2

3 UNIT 3 COMBINATIONAL CIRCUIT 3

4 Selecting Selecting of data or information is a critical function in digital systems and computers Circuits that perform selecting have: A set of information inputs from which the selection is made A single output A set of control lines for making the selection Logic circuits that perform selecting are called multiplexers Selecting can also be done by three state logic or transmission gates 4

5 Multiplexers A multiplexer selects information from an input line and directs the information to an output line A typical multiplexer has n control inputs (S n, S 0 ) called selection inputs, 2 n information inputs (I 2 n, I 0 ), and one output Y A multiplexer can be designed to have m information inputs with m < 2 n as well as n selection inputs 5

6 2 to Line Multiplexer Since 2 = 2, n = The single selection variable S has two values: S = 0 selects input I 0 S = selects input I The equation: Y = I 0 + SI The circuit: S 6

7 2 to Line Multiplexer (continued) Note the regions of the multiplexer circuit shown: to 2 line Decoder 2 Enabling circuits 2 input OR gate To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a 2 2 AND OR circuit: to 2 line decoder 2 2 AND OR In general, for an 2 n to line multiplexer: n to 2 n line decoder 2 n 2 AND OR 7

8 Example: 4 to line Multiplexer 2 to 2 2 line decoder AND OR 8

9 Multiplexer With Expansion Select vectors of bits instead of bits Use multiple copies of 2 n 2 AND OR in parallel Example: 4 to line quad multiplexer 9

10 Decoding Decoding the conversion of an n bit input code to an m bit output code with n m 2 n such that each valid code word produces a unique output code Circuits that perform decoding are called decoders Here, functional blocks for decoding are called n to m line decoders, where m 2 n, and generate 2 n (or fewer) minterms for the n input variables 0

11 Decoder Examples to 2 Line Decoder 2 to 4 Line Decoder Note that the 2 4 line made up of 2 to 2 line decoders and 4 AND gates.

12 Decoder Expansion General procedure given in book for any decoder with n inputs and 2 n outputs. This procedure builds a decoder backward from the outputs. The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by. These decoders are then designed using the same procedure until 2 to line decoders are reached. The procedure can be modified to apply to decoders with the number of outputs 2 n 2

13 Decoder Expansion Example 3 to 8 line decoder Number of output ANDs = 8 Number of inputs to decoders driving output ANDs = 3 Closest possible split to equal 2 to 4 line decoder to 2 line decoder 2 to 4 line decoder Number of output ANDs = 4 Number of inputs to decoders driving output ANDs = 2 Closest possible split to equal Two to 2 line decoders See next slide for result 3

14 Decoder Expansion Example Result 4

15 Decoder Expansion Example 2 7 to 28 line decoder Number of output ANDs = 28 Number of inputs to decoders driving output ANDs = 7 Closest possible split to equal 4 to 6 line decoder 3 to 8 line decoder 4 to 6 line decoder Number of output ANDs = 6 Number of inputs to decoders driving output ANDs = 2 Closest possible split to equal 2 2 to 4 line decoders Complete using known 3 8 and 2 to 4 line decoders 5

Decoder with Enable In general, attach m enabling circuits to the outputs See truth table below for function Note use of s to denote both 0 and Combination

16 Decoder with Enable In general, attach m enabling circuits to the outputs See truth table below for function Note use of s to denote both 0 and Combination containing two s represent four binary combinations Alternatively, can be viewed as distributing value of signal EN to of 4 outputs In this case, called a demultiplexer 6

17 Encoding Encoding the opposite of decoding the conversion of an m bit input code to a n bit output code with n m 2 n such that each valid code word produces a unique output code Circuits that perform encoding are called encoders An encoder has 2 n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is to a binary code corres ponding to the position in which the appears. 7

18 Encoder Example A decimal to BCD encoder Inputs: 0 bits corresponding to decimal digits 0 through 9, (D 0,, D 9 ) Outputs: 4 bits with BCD codes Function: If input bit D i is a, then the output (A 3, A 2, A, A 0 ) is the BCD code for i, The truth table could be formed, but alternatively, the equations for each of the four outputs can be obtained directly. 8

19 Encoder Example (continued) Input D i is a term in equation A j if bit A j is in the binary value for i. Equations: A 3 = D 8 + D 9 A 2 = D 4 + D 5 + D 6 + D 7 A = D 2 + D 3 + D 6 + D 7 A 0 = D + D 3 + D 5 + D 7 + D 9 F = D 6 + D 7 can be extracted from A 2 and A Is there any cost saving? 9

20 Priority Encoder If more than one input value is, then the encoder just designed does not work. One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder. Among the s that appear, it selects the most significant input position (or the least significant input position) containing a and responds with the corresponding binary code for that position. 20

21 Priority Encoder Example Priority encoder with 5 inputs (D 4, D 3, D 2, D, D 0 ) highest priority to most significant present Code outputs A2, A, A0 and V where V indicates at least one present. No. of Minterms/Row Inputs Outputs D4 D3 D2 D D0 A2 A A0 V s in input part of table represent 0 or ; thus table entries correspond to product terms instead of minterms. The column on the left shows that all 32 minterms are present in the product terms in the table 2

22 Code Converters BCD to Seven Segment Converters 4 bit BCD into a 7 bit code to drive display segments Useful in calculators and any application that requires a 7 segment display. 22

23 Seven Segment Decoders LED or LCD (liquid crystal display) Common anode or common cathode Chapter 3 23

24 Seven Segment Decoders(2) 24

25 Code Converters Gray Code used to indicate angular position of rotating shafts varies by only bit from one entry to the next 25

26 Code Converters Gray Code Comparison between regular binary and Gray code: 26

27 Code Converters Conversion between binary and Gray code using OR gates 27

28 Read Only Memory Functions are implemented by storing the truth table Other representations such as equations more convenient Generation of programming information from equations usually done by software Text Example 4 0 Issue Two outputs are generated outside of the ROM In the implementation of the system, these two functions are hardwired and even if the ROM is reprogrammable or removable, cannot be corrected or updated 28

29 Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have: N input lines, M output lines, and 2 N decoded minterms. Fixed AND array with 2 N outputs implementing all N literal minterms. Programmable OR Array with M outputs lines to form up to M sum of minterm expressions. A program for a ROM or PROM is simply a multiple output truth table If a entry, a connection is made to the corresponding minterm for the corresponding output If a 0, no connection is made Can be viewed as a memory with the inputs as addresses of data (output values), hence ROM or PROM names! 29

30 Read Only Memory Example Example: A 8 4 ROM (N = 3 input lines, M= 4 output lines) The fixed "AND" array is a decoder with 3 inputs and 8 outputs implementing minterms. The programmable "OR array uses a single line to represent all inputs to an OR gate. An in the array corresponds to attaching the minterm to the OR Read Example: For input (A 2,A,A 0 ) = 0, output is (F 3,F 2,F,F 0 ) = 00. F3 F2 F What are functions F 3, F 2, F and F 0 in terms of (A 2, A, A 0 )? A B C A2 A A0 D7 D6 D5 D4 D3 D2 D D0 F0 30

31 Internal logic of ROM 3

32 Programming ROM 32

33 Programming ROM ROM Logic 33

34 Combinational circuit implementation using ROM Design a combinational circuit with three bit inputs which outputs the square of the input in binary. 34

35 Combinational circuit implementation using ROM Design a combinational circuit with three bit inputs which outputs the square of the input in binary. 35

36 Programmable Array Logic There is no sharing of AND gates as in the ROM and PLA Design requires fitting functions within the limited number of ANDs per OR gate Single function optimization is the first step to fitting Otherwise, if the number of terms in a function is greater than the number of ANDs per OR gate, then factoring is necessary 36

37 Prog ram m able Array Log ic Example Equations: F = A B C+ B A + C AC B+ ABC F2 = AB + BC + AC F must be factored since four terms Factor out last two terms as W Product term AND Inputs A B C D W Outputs W = A BC + ABC F = = A B C + AB C + W F2 = Y = AB + BC +AC 37

38 Prog ram m able Array Log ic Product term AND gates inputs A A B B C C D D W W 2 W 3 A 4 All fuses intact (always 5 0) 5 F 6 B 7 8 F2 9 C 0 2 D A A B B C C D D W W Fuse intact Fuse blown 38

39 Programmable Logic Array The set of functions to be implemented must fit the available number of product terms The number of literals per term is less important in fitting The best approach to fitting is multiple output, two level optimization (which has not been discussed) Since output inversion is available, terms can implement either a function or its complement For small circuits, K maps can be used to visualize product term sharing and use of complements For larger circuits, software is used to do the optimization including use of complemented functions 39

40 Prog ram m able Log ic Array Example K map specification How can this be implemented with four terms? BC A A Complete the programming table 0 B C F 5 A BC + A B C + A B C F 5 AB + AC + BC + A B C BC A A 0 PLA programming table B C F 2 5 AB + AC +BC F 2 5 AC + AB + B C Product term Inputs A B C Outputs ( ) F (T) F 2 AB AC BC

41 Prog ram m able Log ic Array Example A B C 2 Fuse intact Fuse blown 3 4 C C B B A A 0 F F 2 4

42 ROM, PAL and PLA Config ura tions Inputs Fixed AND array (decoder) Programmable Connections Programmable OR array Outputs (a) Programmable read-only memory (PROM) Inputs Programmable Connections Programmable AND array Fixed OR array Outputs (b) Programmable array logic (PAL) device Inputs Programmable Connections Programmable AND array Programmable Connections Programmable OR array Outputs (c) Programmable logic array (PLA) device 42

43 Programmable Array Logic(PAL) The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs. Disadvantage ROM guaranteed to implement any M functions of N inputs. PAL may have too few inputs to the OR gates. Advantages For given internal complexity, a PAL can have larger N and M Some PALs have outputs that can be complemented, adding POS functions No multilevel circuit implementations in ROM (without external connections from output to input). PAL has outputs from OR terms as internal inputs to all AND terms, making implementation of multi level circuits easier. 43

44 Prog ram m able Array Log ic Example AND gates inputs 4 input, 3 output PAL with fixed, 3 input OR terms I 5 A Product term F What are the equations for F through F4? F 2 I 25 B 7 8 F 3 I 35 C 9 0 F 4 2 I

45 Pr og ram m able Log ic Array (P LA) Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs. Advantages A PLA can have large N and M permitting implementation of equations that are impractical for a ROM (because of the number of inputs, N, required A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL Ors Some PLAs have outputs that can be complemented, adding POS functions Disadvantage Often, the product term count limits the application of a PLA. Twolevel multiple output optimization reduces the number of product terms in an implementation, helping to fit it into a PLA. 45

46 Prog ram m able Log ic Array Example A B What are the equations for F and F 2? Could the PLA implement the functions without the OR gates? C A B 2 3 B C A C Fuse intact Fuse blown 3 input, 3 output PLA with 4 product terms 4 C C B B A A 0 A B F F 2 46

47 Pr og ram m able Log ic Array (P LA) Disadvantages Often, the product term count limits the application of a PLA. Two level multiple output optimization is required to reduce the number of product terms in an implementation, helping to fit it into a PLA. Multi level circuit capability available in PAL not available in PLA. PLA requires external connections to do multi level circuits. 47

48 PLA Example A B What are the equations for F and F2? Could the PLA implement the functions without the OR gates? C A B 2 3 B C A C Fuse intact Fuse blown 3 input, 3 output PLA with 4 product terms 4 C C B B A A 0 A B F F 2 48

49 Bibliography Charles H. Roth Jr., Fundamentals of logic design, Thomson Asia,5th edition 2004 (CH,CH2,CH3,CH4,CH5,CH6,CH7,CH9,CH,CH2) M. Morris Mano, Digital Logic and Computer Design, Prentice Hall of India Floyd, Digital Fundamentals, Universal Book Stall, 3rd Edition,986 Morris Mano, Digital Design, Prentice Hall of India, 2nd Edition 99 Bigell & Donovan, Digital Electronics, Thomson Asia Pvt. Ltd., 4th Edition School of Computing, Department of IT 8/22/20 49

50 Review questions. Define code conversion networks. 2. What is the need for code conversion networks? 3. List out the advantages of ROM? 4. Mention the basic types of ROMs? 5. List out the advantages of EPROM over PROM? 6. What is a programmable logic device? 7. Define PLA? School of Computing, Department of IT 8/22/20 50

9 Programmable Logic Devices

9 Programmable Logic Devices Introduction to Programmable Logic Devices A programmable logic device is an IC that is user configurable and is capable of implementing logic functions. It is an LSI chip that contains a 'regular' structure