4:1 Mux Symbol 4:1 Mux Circuit
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1 Exercise 6: Combinational Circuit Blocks Revision: October 20, E Main Suite D Pullman, WA (509) Voice and Fax STUDT I am submitting my own work, and I understand penalties will be assessed if I submit work for credit that is not my own. Print Name Sign Name Estimated Work Hours ID Number Date Overall Weight GRADER # Points Score Total Score Weeks late Adjusted Score Adjusted Score: Deduct 20% from score for each week late Problem 1. Complete the 4:1 mux circuit by sketching the missing wires. I2 Y I2 Y 4:1 Mux Symbol 4:1 Mux Circuit Contains material Digilent, Inc. 7 pages
2 Problem 2. Complete the truth table and circuit sketch for a 4:1 mux. When completing the truth table, make use of don t care s to reduce the number of required rows. Y Y I2 I2 Y 4:1 mux with enable truth table 4:1 Mux with enable Problem 3. Sketch an 8:1 mux using two 4:1 muxes and one 2:1 mux. Be sure to label all inputs and outputs.
3 Problem 4: Compete a circuit sketch to show how F = m(0, 2, 4, 5, 6) can be implemented using the mux shown. (Hint: prepare an enteredvariable K-map). I2 Y Problem 5. Complete the 3:8 decoder schematic on the right by sketching the missing wires. S2 S2 3:8 Decoder Symbol 3:8 Decoder Circuit S2 Problem 6. Complete the 3:8 decoder with enable schematic by sketching the missing wires. S2
4 Problem 7: Complete the 4:16 decoder built from 4 2:4 decoders below by sketching the missing wires. Label all inputs and outputs. Problem 8. Complete a sketch to show how the 3:8 decoder can be used to implement the logic equation F = m(1, 2, 4, 6) Decoder inputs and outputs are all asserted HIGH. S2
5 Problem 9. Complete the truth table. The table shows the nine decimal digits, their binary equivalents, and seven columns labeled A- G. The columns labeled A-G can be used to record when a segment must be illuminated to display a given digit. For example, in the first row corresponding to the digit '0', segments A, B, C, D, E, and F must be illuminated, so a '1' must be placed in those columns. When completed, the table can serve as a truth table for the seven-segment controller it shows the required logic relationship between the four inputs and seven outputs. Note that in the truth table, the last six input patterns (1010 through 1111) Digit Inputs 4-bit numbers Outputs Segment-drive functions B3 B2 B1 B0 A B C D E F G NA NA NA NA NA NA are not associated with a decimal digit. They are therefore "illegal" inputs, so outputs can receive a don't care for those rows. Problem 10. Complete the truth table for a three-input priority encoder. When completing the truth table, note that if is a 1, it DOES NOT matter what I2,, or are the encoded output will be 11. This information can result in don t cares in the truth table, which makes the design much easier (note that X s have been used in the truth table to indicate don t care input conditions). When the truth table is complete, write VHDL equations to define the encoder circuits. I2 GS E OUT 0 X X X X X X X X X X Priority encoder truth table
6 Problem 11. Complete the truth table for a 4-bit shifter that has no enable input, no rotate input, two inputs that dictate whether the input is to be shifted 0, 1, 2, or 3 bits, a direction input, and a fill input. A1 A0 F D Problem 12. Complete the table below to show the numerical results from applying the indicated operation to the data shown. Opcodes are six-bit numbers defined as shown below. R = 1 for Rotate; D = 1 for Right; F is fill, and A2-A0 define the number of bits. Show all work to be eligible for partial credit. R D F A2 A1 A0 Input (Base10) Input (Base2/8-bit) Op Code Output (Base10) Output (Base2/8-bit))
7 Problem 13. Modify only two characters in the code below to add a Fill bit. entity my_shift is port (din: in std_logic_vector (7 downto 0); r, d, f, en: in std_logic; dout: out std_logic_vector (7 downto 0)); end my_shift; architecture my_shift_arch of my_shift is begin dout <= when en = '0' else din(6 downto 0) & din(7) when (r = '1' and d = '0') else din(0) & din(7 downto 1) when (r = '1' and d = '1') else din(6 downto 0) & '0' when (r = '0' and d = '0') else '0' & din(7 downto 1); end my_shift_arch;
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