Direct RDRAM 128/144-MBit (256K 16/18 32s)

Transcription

1 Overview The Rambus Direc RDRAM is a general purpose high-performance memory device suiable for use in a broad range of applicaions including compuer memory, graphics, video, and any oher applicaion where high bandwidh and low laency are required. The 128/144-Mbi Direc Rambus DRAMs (RDRAM ) are exremely high-speed CMOS DRAMs organized as 8M words by 16 or 18 bis. The use of Rambus Signaling Level (RSL) echnology permis 600 MHz o 800 MHz ransfer raes while using convenional sysem and board design echnologies. Direc RDRAM devices are capable of susained daa ransfers a 1.25 ns per wo byes (10 ns per sixeen byes). The archiecure of he Direc RDRAMs allows he highes susained bandwidh for muliple, simulaneous randomly addressed memory ransacions. The separae conrol and daa buses wih independen row and column conrol yield over 95% bus efficiency. The Direc RDRAM s hiry-wo banks suppor up o four simulaneous ransacions. Sysem oriened feaures for mobile, graphics and large memory sysems include power managemen, bye masking, and x18 organizaion. The wo daa bis in he x18 organizaion are general and can be used for addiional sorage and bandwidh or for error correcion. Feaures Highes susained bandwidh per DRAM device 1.6 GB/s susained daa ransfer rae Separae conrol and daa buses for maximized efficiency Separae row and column conrol buses for easy scheduling and highes performance 32 banks: four ransacions can ake place simulaneously a full bandwidh daa raes Low laency feaures Wrie buffer o reduce read laency 3 precharge mechanisms for conroller flexibiliy Inerleaved ransacions Advanced power managemen: Muliple low power saes allows flexibiliy in power consumpion versus ime o ransiion o acive sae Power-down self-refresh Organizaion: 1 Kbye pages and 32 banks, x16/18 x18 organizaion allows ECC configuraions or increased sorage/bandwidh x16 organizaion for low cos applicaions Uses Rambus Signaling Level (RSL) for up o 800 MHz operaion Daa Book

2 Figure 1 Direc RDRAM CSP Package The 128/144-Mbi Direc RDRAMs are offered in a CSP horizonal package suiable for deskop as well as low-profile add-in card and mobile applicaions. Direc RDRAMs operae from a 2.5 V supply. Table 1 Key Timing Parameers/Par Numbers Organizaion I/O Freq. MHz Trac Normal Package: Par Number 8M ns HYB25R144180C-653 8M ns HYB25R144180C-745 8M ns HYB25R144180C-845 8M ns HYB25R144180C-840 8M ns HYB25R128160C-653 8M n s HYB25R128160C-745 8M ns HYB25R128160C-845 8M ns HYB25R128160C-840 Mirror Package: 8M ns HYB25M144180C-653 8M ns HYB25M144180C-745 8M ns HYB25M144180C-845 8M ns HYB25M144180C-840 8M ns HYB25M128160C-653 8M n s HYB25M128160C-745 8M ns HYB25M128160C-845 8M ns HYB25M128160C-840 Daa Book

3 Pinous and Definiions This ables show he pin assignmens of he RDRAM package from he op-side of he package (he view looking down on he package as i is mouned on he circui board). The mechanical dimensions of his package are shown in a laer secion. Refer o Secion Cener-Bonded FBGA Package on page 86. Noe - pin #1 is a he A1 posiion. DQA8/DQB8 are used for 144 Mbi only. They are N.C. for 128Mbi. Table 2 Normal Package (op view) 12 GND VDD V DD GND DQA7 DQA4 CFM CFMN RQ5 RQ3 DQB0 DQB4 DQB7 9 GND V DD GND GNDa V DD GND V DD V DD GND 8 CMD DQA5 DQA2 V DDa RQ6 RQ2 DQB1 DQB5 SIO SCK DQA6 DQA1 V REF RQ7 RQ1 DQB2 DQB6 SIO0 4 V CMOS GND V DD GND GND V DD GND GND V CMOS 3 DQA8 DQA3 DQA0 CTMN CTM RQ4 RQ0 DQB3 DQB8 2 1 GND V DD V DD GND A B C D E F G H J Table 3 Mirrored Package (op view) 12 GND VDD V DD GND DQA8 DQA3 DQA0 CTMN CTM RQ4 RQ0 DQB3 DQB8 9 V CMOS GND V DD GND GND V DD GND GND V CMOS 8 SCK DQA6 DQA1 V REF RQ7 RQ1 DQB2 DQB6 SIO CMD DQA5 DQA2 V DDa RQ6 RQ2 DQB1 DQB5 SIO1 4 GND V DD GND GNDa V DD GND V DD V DD GND 3 DQA7 DQA4 CFM CFMN RQ5 RQ3 DQB0 DQB4 DQB7 2 1 GND V DD V DD GND A B C D E F G H J Daa Book

4 Table 4 Signal I/O Type # Pins Edge # Pins Cener Descripion SIO1,SIO0 I/O CMOS 1) 2 2 Serial inpu/oupu. Pins for reading from and wriing o he conrol regisers using a serial access proocol. Also used for power managemen. CMD I CMOS 1) 1 1 Command inpu. Pins used in conjuncion wih SIO0 and SIO1 for reading from and wriing o he conrol regisers. Also used for power managemen. SCK I CMOS 1) 1 1 Serial clock inpu. Clock source used for reading from and wriing o he conrol regisers. V DD 14 6 Supply volage for he RDRAM core and inerface logic. V DDa 2 1 Supply volage for he RDRAM analog circuiry. V CMOS 2 2 Supply volage for CMOS inpu/oupu pins. GND 19 9 Ground reference for RDRAM core and inerface. GNDa 2 1 Ground reference for RDRAM analog circuiry. DQA8 DQA0 I/O RSL 2) 9 9 Daa bye A. Nine pins which carry a bye of read or wrie daa beween he Channel and he RDRAM. DQA8 is no used by RDRAMs wih a x16 organizaion. CFM I RSL 2) 1 1 Clock from maser. Inerface clock used for receiving RSL signals from he Channel. Posiive polariy. CFMN I RSL 2) 1 1 Clock from maser. Inerface clock used for receiving RSL signals from he Channel. Negaive polariy V REF 1 1 Logic hreshold reference volage for RSL signals CTMN I RSL 2) 1 1 Clock o maser. Inerface clock used for ransmiing RSL signals o he Channel. Negaive polariy. CTM I RSL 2) 1 1 Clock o maser. Inerface clock used for ransmiing RSL signals o he Channel. Posiive polariy. RQ7 RQ5 or ROW2 ROW0 RQ4 RQ0 or COL4 COL0 I RSL 2) 3 3 Row access conrol. Three pins conaining conrol and address informaion for row accesses. I RSL 2) 5 5 Column access conrol. Five pins conaining conrol and address informaion for column accesses. DQB8 DQB0 I/O RSL 2) 9 9 Daa bye B. Nine pins which carry a bye of read or wrie daa beween he Channel and he RDRAM. DQB8 is no used by RDRAMs wih a x16 organizaion. Toal pin coun per package ) All CMOS signals are high-rue; a high volage is a logic one and a low volage is logic zero. 2) All RSL signals are low-rue; a low volage is a logic one and a high volage is logic zero. Daa Book

5 DQB8...DQB0 RQ7...RQ5 or ROW2...ROW0 CTM CTMN SCK, CMD SIO0, SIO1 CFM CFMN RQ4...RQ0 or COL4...COL0 DQA8...DQA :8 Demux RCLK 1:8 Demux RCLK Packe Decode ROWR ROWA 9 TCLK Conrol Regisers RCLK COLX Packe Decode COLC COLM 8 8 ROPAV DR BR R REFR Power Modes DEVID XOPM DX BX COPS DC BC C MB MA RCLK Mach DM 9 Mux Row Decode Inernal DQB Daa Pah 9 Sense Amp 32 x 72 SAmp PRER ACT Bank 0 SAmp 0/1 SAmp 1/2 DRAM Core 32 x x x 64 x 144 Bank 1 Bank 2 Mach Mach Wrie Buffer XOP Decode SAmp 0 SAmp 0/1 SAmp 1/2 Mux Mux Column Decode & Mask PREX RD, WR Inernal DQA Daa Pah 9 9 RCLK 9 1:8 Demux Wrie Buffer Bank 13 Wrie Buffer 1:8 Demux 9 SAmp 13/14 Bank 14 SAmp 13/14 SAmp 14/15 Bank 15 SAmp 14/15 SAmp 15 SAmp 15 SAmp 16 SAmp 16 9 Bank 16 9 TCLK SAmp 16/17 Bank 17 SAmp 16/17 TCLK 9 8:1 Mux SAmp 17/18 Bank 18 SAmp 17/18 8:1 Mux 9 Bank 29 SAmp 29/30 SAmp 30/31 SAmp 31 Bank 30 Bank 31 SAmp 29/30 SAmp 30/31 SAmp 31 SPB04206 Figure 2 128/144-MBi Direc RDRAM Block Diagram Daa Book

6 General Descripion Figure 2 is a block diagram of he 128/144 Mbi Direc RDRAM. I consiss of wo major blocks: a core block buil from banks and sense amps similar o hose found in oher ypes of DRAM, and a Direc Rambus inerface block which permis an exernal conroller o access his core a up o 1.6 GB/s. Conrol Regisers: The CMD, SCK, SIO0, and SIO1 pins appear in he upper cener of Figure 2. They are used o wrie and read a block of conrol regisers. These regisers supply he RDRAM configuraion informaion o a conroller and hey selec he operaing modes of he device. The nine bi REFR value is used for racking he las refreshed row. Mos imporanly, he five bi DEVID specifies he device address of he RDRAM on he Channel. Clocking: The CTM and CTMN pins (Clock-To-Maser) generae TCLK (Transmi Clock), he inernal clock used o ransmi read daa. The CFM and CFMN pins (Clock-From-Maser) generae RCLK (Receive Clock), he inernal clock signal used o receive wrie daa and o receive he ROW and COL pins. DQA, DQB Pins: These 18 pins carry read (Q) and wrie (D) daa across he Channel. They are muliplexed/de-muliplexed from/o wo 72-bi daa pahs (running a one-eighh he daa frequency) inside he RDRAM. Banks: The 16 Mbye core of he RDRAM is divided ino Mbye banks, each organized as 512 rows, wih each row conaining 64 dualocs, and each dualoc conaining 16 byes. A dualoc is he smalles uni of daa ha can be addressed. Sense Amps: The RDRAM conains 34 sense amps. Each sense amp consiss of 512 byes of fas sorage (256 for DQA and 256 for DQB) and can hold one-half of one row of one bank of he RDRAM. The sense amp may hold any of he 512 half-rows of an associaed bank. However, each sense amp is shared beween wo adjacen banks of he RDRAM (excep for numbers 0, 15, 30, and 31). This inroduces he resricion ha adjacen banks may no be simulaneously accessed. RQ Pins: These pins carry conrol and address informaion. They are broken ino wo groups. RQ7 RQ5 are also called ROW2 ROW0, and are used primarily for conrolling row accesses. RQ4 RQ0 are also called COL4 COL0, and are used primarily for conrolling column accesses. ROW Pins: The principle use of hese hree pins is o manage he ransfer of daa beween he banks and he sense amps of he RDRAM. These pins are de-muliplexed ino a 24-bi ROWA (row-acivae) or ROWR (row-operaion) packe. COL Pins: The principle use of hese five pins is o manage he ransfer of daa beween he DQA/DQB pins and he sense amps of he RDRAM. These pins are de-muliplexed ino a 23-bi COLC (column-operaion) packe and eiher a 17-bi COLM (mask) packe or a 17-bi COLX (exended-operaion) packe. ACT Command: An ACT (acivae) command from an ROWA packe causes one of he 512 rows of he seleced bank o be loaded o is associaed sense amps (wo 256 bye sense amps for DQA and wo for DQB). PRER Command: A PRER (precharge) command from an ROWR packe causes he seleced bank o release is wo associaed sense amps, permiing a differen row in ha bank o be acivaed, or permiing adjacen banks o be acivaed. Daa Book

7 RD Command: The RD (read) command causes one of he 64 dualocs of one of he sense amps o be ransmied on he DQA/DQB pins of he Channel. WR Command: The WR (wrie) command causes a dualoc received from he DQA/DQB daa pins of he Channel o be loaded ino he wrie buffer. There is also space in he wrie buffer for he BC bank address and C column address informaion. The daa in he wrie buffer is auomaically reired (wrien wih opional byemask) o one of he 64 dualocs of one of he sense amps during a subsequen COP command. A reire can ake place during a RD, WR, or NOCOP o anoher device, or during a WR or NOCOP o he same device. The wrie buffer will no reire during a RD o he same device. The wrie buffer reduces he delay needed for he inernal DQA/DQB daa pah urnaround. PREC Precharge: The PREC, RDA and WRA commands are similar o NOCOP, RD and WR, excep ha a precharge operaion is performed a he end of he column operaion. These commands provide a second mechanism for performing precharge. PREX Precharge: Afer a RD command, or afer a WR command wih no bye masking (M = 0), a COLX packe may be used o specify an exended operaion (XOP). The mos imporan XOP command is PREX. This command provides a hird mechanism for performing precharge. Packe Forma Figure 3 shows he formas of he ROWA and ROWR packes on he ROW pins. Table 5 describes he fields which comprise hese packes. DR4T and DR4F bis are encoded o conain boh he DR4 device address bi and a framing bi which allows he ROWA or ROWR packe o be recognized by he RDRAM. The AV (ROWA/ROWR packe selecion) bi disinguishes beween he wo packe ypes. Boh he ROWA and ROWR packe provide a five bi device address and a five bi bank address. An ROWA packe uses he remaining bis o specify a nine bi row address, and he ROWR packe uses he remaining bis for an eleven bi opcode field. Noe he use of he RsvX noaion o reserve bis for fuure address field exension. Table 5 Field Descripion for ROWA Packe and ROWR Packe Field Descripion DR4T, DR4F Bis for framing (recognizing) a ROWA or ROWR packe. Also encodes highes device address bi. DR3 DR0 Device address for ROWA or ROWR packe. BR4 BR0 Bank address for ROWA or ROWR packe. RsvB denoes bis ignored by he RDRAM. AV Selecs beween ROWA packe (AV = 1) and ROWR packe (AV = 0). R8 R0 Row address for ROWA packe. RsvR denoes bis ignored by he RDRAM. ROP10 ROP0 Opcode field for ROWR packe. Specifies precharge, refresh, and power managemen funcions. Figure 3 also shows he formas of he COLC, COLM, and COLX packes on he COL pins. Table 6 describes he fields which comprise hese packes. Daa Book

8 The COLC packe uses he S (Sar) bi for framing. A COLM or COLX packe is aligned wih his COLC packe, and is also framed by he S bi. The 23 bi COLC packe has a five bi device address, a five bi bank address, a six bi column address, and a four bi opcode. The COLC packe specifies a read or wrie command, as well as some power managemen commands. The remaining 17 bis are inerpreed as a COLM (M = 1) or COLX (M = 0) packe. A COLM packe is used for a COLC wrie command which needs byemask conrol. The COLM packe is associaed wih he COLC packe from a ime RTR earlier. An COLX packe may be used o specify an independen precharge command. I conains a five bi device address, a five bi bank address, and a five bi opcode. The COLX packe may also be used o specify some housekeeping and power managemen commands. The COLX packe is framed wihin a COLC packe bu is no oherwise associaed wih any oher packe. Table 6 Field Descripion for COLC Packe, COLM Packe, and COLX Packe Field Descripion S Bi for framing (recognizing) a COLC packe, and indirecly for framing COLM and COLX packes. DC4 DC0 Device address for COLC packe. BC4 BC0 Bank address for COLC packe. RsvB denoes bis reserved for fuure exension (conroller drives 0 s). C5 C0 Column address for COLC packe. RsvC denoes bis ignored by he RDRAM. COP3 COP0 Opcode field for COLC packe. Specifies read, wrie, precharge, and power managemen funcions. M Selecs beween COLM packe (M = 1) and COLX packe (M = 0). MA7 MA0 Byemask wrie conrol bis. 1 = wrie, 0 = no-wrie. MA0 conrols he earlies bye on DQA8 0. MB7 MB0 Byemask wrie conrol bis. 1 = wrie, 0 = no-wrie. MB0 conrols he earlies bye on DQB8 0. DX4 DX0 Device address for COLX packe. BX4 BX0 Bank address for COLX packe. RsvB denoes bis reserved for fuure exension (conroller drives 0 s). XOP4 XOP0 Opcode field for COLX packe. Specifies precharge, I OL conrol, and power managemen funcions. Daa Book

9 ROWA Packe ROWR Packe T0 T1 T2 T3 T8 T9 T10 T11 CTM/CFM CTM/CFM ROW2 DR4T DR2 BR0 BR3 RsvR R8 R5 R2 ROW2 DR4T DR2 BR0 BR3 ROP10 ROP8 ROP5 ROP2 ROW1 DR4F DR1 BR1 BR4 RsvR R7 R4 R1 ROW1 DR4F DR1 BR1 4RsvB ROP9 ROP7 ROP4 ROP1 ROW0 DR3 DR0 BR2 RsvB AV=1 R6 R3 R0 ROW0 DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0 COLC Packe CTM/CFM T0 T1 T2 T3 CTM/CFM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 COL4 DC4 S = 1 RsvC C4 ROW2...ROW0 ACT a0 PRER c0 COL3 COL2 COL1 DC3 DC2 DC1 COP1 COP0 RsvB BC4 C5 BC2 BC1 C3 C2 C1 COL4...COL0 DQA8...0 DQB8...0 Packe WR b1 MSK (b1) PREX (d0) COL0 DC0 COP2 COP3 BC3 BC0 C0 COLM Packe COLX Packe T8 T9 T10 T11 T12 T13 T14 T15 CTM/CFM CTM/CFM COL4 S=1 a MA7 MA5 MA3 MA1 COL4 b S=1 DX4 XOP4 RsvB BX1 COL3 M = 1 MA6 MA4 MA2 MA0 COL3 M = 0 DX3 XOP3 BX4 BX0 COL2 MB7 MB4 MB1 COL2 DX2 XOP2 BX3 COL1 MB6 MB3 MB0 COL1 DX1 XOP1 BX2 COL0 MB5 MB2 COL0 DX0 XOP0 a) The COLM is associaed wih a previous COLC, and is aligned wih he presen COLC, indicaed by he Sar bi (S = 1) posiion. b) The COLX is aligned wih he presen COLC, indicaed by he Sar bi (S = 1) posiion. SPB04207 Figure 3 Packe Formas Daa Book

10 Field Encoding Summary Table 7 shows how he six device address bis are decoded for he ROWA and ROWR packes. The DR4T and DR4F encoding merges a fifh device bi wih a framing bi. When neiher bi is assered, he device is no seleced. Noe ha a broadcas operaion is indicaed when boh bis are se. Broadcas operaion would ypically be used for refresh and power managemen commands. If he device is seleced, he DM (DeviceMach) signal is assered and an ACT or ROP command is performed. Table 7 Device Field Encodings for ROWA Packe and ROWR Packe DR4T DR4F Device Selecion Device Mach Signal (DM) 1 1 All devices (broadcas) DM is se o One device seleced DM is se o 1 if {DEVID4 DEVID0} == {0, DR3 DR0} else DM is se o One device seleced DM is se o 1 if {DEVID4 DEVID0} == {1, DR3 DR0} else DM is se o No packe presen DM is se o 0 Table 8 shows he encodings of he remaining fields of he ROWA and ROWR packes. An ROWA packe is specified by assering he AV bi. This causes he specified row of he specified bank of his device o be loaded ino he associaed sense amps. An ROWR packe is specified when AV is no assered. An 11 bi opcode field encodes a command for one of he banks of his device. The PRER command causes a bank and is wo associaed sense amps o precharge, so anoher row or an adjacen bank may be acivaed. The REFA (refresh-acivae) command is similar o he ACT command, excep he row address comes from an inernal regiser REFR, and REFR is incremened a he larges bank address. The REFP (refreshprecharge) command is idenical o a PRER command. The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing he power dissipaion of he RDRAM and are described in more deail in Power Sae Managemen on page 58. The TCEN and TCAL commands are used o adjus he oupu driver slew rae and hey are described in more deail in Curren and Temperaure Conrol on page 65. Daa Book

11 Table 8 ROWA Packe and ROWR Packe Field Encodings DM 1) AV ROP10 ROP0 Field Name Command Descripion : No operaion. 1 1 Row address ACT Acivae row R8 R0 of bank BR4 BR0 of device and move device o ATTN 2) x 3) x x 000 PRER Precharge bank BR4 BR0 of his device x 000 REFA Refresh (acivae) row REFR8 REFR0 of bank BR3 BR0 of device. Incremen REFR if BR4 BR0 = 1111 (see Figure 50) x 000 REFP Precharge bank BR4 BR0 of his device afer REFA (see Figure 50). 1 0 x x x 000 PDNR Move his device ino he powerdown (PDN) power sae (see Figure 47). 1 0 x x x 000 NAPR Move his device ino he nap (NAP) power sae (see Figure 47). 1 0 x x x 000 NAPRC Move his device ino he nap (NAP) power sae condiionally. 1 0 x x x x x x x ATTN 2) Move his device ino he aenion (ATTN) power sae (see Figure 45). 1 0 x x x x x x x RLXR Move his device ino he sandby (STBY) power sae (see Figure 46) x 001 TCAL Temperaure calibrae his device (see Figure 52) x 010 TCEN Temperaure calibrae/enable his device (see Figure 52) NOROP No operaion. 1) The DM (Device Mach signal) value is deermined by he DR4T,DR4F, DR3 DR0 field of he ROWA and ROWR packes. See Table 7. 2) 3) The ATTN command does no cause a RLX-o-ATTN ransiion for a broadcas operaion (DR4T/DR4F = 1/1). An x enry indicaes which commands may be combined. For insance, he hree commands PRER/NAPRC/RLXR may be specified in one ROP value ( ). Table 9 shows he COP field encoding. The device mus be in he ATTN power sae in order o receive COLC packes. The COLC packe is used primarily o specify RD (read) and WR (wrie) commands. Reire operaions (moving daa from he wrie buffer o a sense amp) happen auomaically. See Figure 17 for a more deailed descripion. The COLC packe can also specify a PREC command, which precharges a bank and is associaed sense amps. The RDA/WRA commands are equivalen o combining RD/WR wih a PREC. RLXC (relax) performs a power mode ransiion. See Power Sae Managemen on page 58. Daa Book

12 Table 9 COLC Packe Field Encodings S DC4 DC0 COP3 0 Name Command Descripion (selec device) 1) No operaion. 1 /= (DEVID4 0) Reire wrie buffer of his device. 1 == (DEVID4 0) x000 2) NOCOP Reire wrie buffer of his device. 1 == (DEVID4 0) x001 WR Reire wrie buffer of his device, hen wrie column C5 C0 of bank BC4 BC0 o wrie buffer. 1 == (DEVID4 0) x010 RSRV Reserved, no operaion. 1 == (DEVID4 0) x011 RD Read column C5 C0 of bank BC4 BC0 of his device. 1 == (DEVID4 0) x100 PREC Reire wrie buffer of his device, hen precharge bank BC4 BC0 (see Figure 14). 1 == (DEVID4 0) x101 WRA Same as WR, bu precharge bank BC4 BC0 afer wrie buffer (wih new daa) is reired. 1 == (DEVID4 0) x110 RSRV Reserved, no operaion. 1 == (DEVID4 0) x111 RDA Same as RD, bu precharge bank BC4 BC0 aferward. 1 == (DEVID4 0) 1xxx RLXC Move his device ino he sandby (STBY) power sae (see Figure 46). 1) /= means no equal, == means equal. 2) An x enry indicaes which commands may be combined. For insance, he wo commands WR/RLXC may be specified in one COP value (1001). Daa Book

13 Table 10 shows he COLM and COLX field encodings. The M bi is assered o specify a COLM packe wih wo 8 bi byemask fields MA and MB. If he M bi is no assered, an COLX is specified. I has device and bank address fields, and an opcode field. The primary use of he COLX packe is o permi an independen PREX (precharge) command o be specified wihou consuming conrol bandwidh on he ROW pins. I is also used for he CAL (calibrae) and SAM (sample) curren conrol commands (see Curren and Temperaure Conrol on page 65), and for he RLXX power mode command (see Power Sae Managemen on page 58). Table 10 COLM Packe and COLX Packe Field Encodings M DX4 DX0 XOP4 Name Command Descripion (selecs device) MSK MB/MA byemasks used by WR/WRA. 0 /= (DEVID4 0) No operaion. 0 == (DEVID4 0) NOXOP No operaion. 0 == (DEVID4 0) 1xxx0 1) PREX Precharge bank BX4 BX0 of his device (see Figure 14). 0 == (DEVID4 0) x10x0 CAL Calibrae (drive) I OL curren for his device (see Figure 51). 0 == (DEVID4 0) x11x0 CAL/SAM Calibrae (drive) and Sample (updae) I OL curren for his device (see Figure 51). 0 == (DEVID4 0) xxx10 RLXX Move his device ino he sandby (STBY) power sae (see Figure 46). 0 == (DEVID4 0) xxxx1 RSRV Reserved, no operaion. 1) An x enry indicaes which commands may be combined. For insance, he wo commands PREX/RLXX may be specified in one XOP value (10010). Daa Book

14 DQ Packe Timing Figure 4 shows he iming relaionship of COLC packes wih D and Q daa packes. This documen uses a specific convenion for measuring ime inervals beween packes: all packes on he ROW and COL pins (ROWA, ROWR, COLC, COLM, COLX) use he railing edge of he packe as a reference poin, and all packes on he DQA/DQB pins (D and Q) use he leading edge of he packe as a reference poin. An RD or RDA command will ransmi a dualoc of read daa Q a ime CAC laer. This ime includes one o five cycles of round-rip propagaion delay on he Channel. The CAC parameer may be programmed o a one of a range of values (7, 8, 9, 10, 11, or 12 CYCLE ). The value chosen depends upon he number of RDRAM devices on he Channel and he RDRAM iming bin. See Figure 39 for more informaion. A WR or WRA command will receive a dualoc of wrie daa D a ime CWD laer. This ime does no need o include he round-rip propagaion ime of he Channel since he COLC and D packes are raveling in he same direcion. When a Q packe follows a D packe (shown in he lef half of he figure), a gap ( CAC CWD ) will auomaically appear beween hem because he CWD value is always less han he CAC value. There will be no gap beween he wo COLC packes wih he WR and RD commands which schedule he D and Q packes. When a D packe follows a Q packe (shown in he righ half of he figure), no gap is needed beween hem because he CWD value is less han he CAC value. However, a gap of CAC CWD or greaer mus be insered beween he COLC packes wih he RD WR commands by he conroller so he Q and D packes do no overlap. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM ROW2... ROW0 This gap on he DQA/DQB pins appears auomaically CAC - CWD This gap on he COL pins mus be insered by he conroller CAC - CWD CWD WR d1 COL4...COL0 WR a1 RD b1 RD c1 CWD CAC CAC DQA8...0 DQB8...0 Q (y1) Q (b1) Q (c1) D (d1) SPA04208 Figure 4 Read (Q) and Wrie (D) Daa Packe - Timing for CAC = 7, 8, 9, 10, 11, or 12 CYCLE Daa Book

15 COLM Packe o D Packe Mapping Figure 5 shows a wrie operaion iniiaed by a WR command in a COLC packe. If a subse of he 16 byes of wrie daa are o be wrien, hen a COLM packe is ransmied on he COL pins a ime RTR afer he COLC packe conaining he WR command. The M bi of he COLM packe is se o indicae ha i conains he MA and MB mask fields. Noe ha his COLM packe is aligned wih he COLC packe which causes he wrie buffer o be reired. See Figure 17 for more deails. If all 16 byes of he D daa packe are o be wrien, hen no furher conrol informaion is required. The packe slo ha would have been used by he COLM packe ( RTR afer he COLC packe) is available o be used as an COLX packe. This could be used for a PREX precharge command or for a housekeeping command (his case is no shown). The M bi is no assered in an COLX packe and causes all 16 byes of he previous WR o be wrien uncondiionally. Noe ha a RD command will never need a COLM packe, and will always be able o use he COLX packe opion (a read operaion has no need for he bye-wrie-enable conrol bis). Figure 5 also shows he mapping beween he MA and MB fields of he COLM packe and byes of he D packe on he DQA and DQB pins. Each mask bi conrols wheher a bye of daa is wrien (= 1) or no wrien (= 0). Daa Book

16 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM ROW2... ROW0 ACT a0 PRER a2 ACT b0 COL4...COL0 WR a1 RTR reire (a1) MSK (a1) DQA8...0 DQB8...0 CWD D (a1) Transacion a: WR a0 = {Da, Ba, Ra} a1 = {Da, Ba, Ca1} a3 = {Da, Ba} COLM Packe D Packe T17 T18 T19 T20 T19 T20 T21 T22 CTM/CFM CTM/CFM COL4 MA7 MA5 MA3 MA1 DQB8 DB8 DB17 DB26 DB35 DB45 DB53 DB62 DB71 COL3 M = 1 MA6 MA4 MA2 MA0 DQB7 DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70 COL2 MB7 MB4 MB1 COL1 MB6 MB3 MB0 DQB1 DB1 DB10 DB19 DB28 DB37 DB46 DB55 DB64 COL0 MB5 MB2 DQB0 DB0 DB9 DB18 DB27 DB36 DB45 DB54 DB63 Each bi of he MB7...MB0 field conrols wriing (= 1) or no wriing (= 0) of he indicaed DB bis when he M bi of he COLM packe is one. DQA8 MB0 DA8 MB1 DA17 MB2 DA26 MB3 DA35 MB4 DA45 MB5 DA53 MB6 DA62 MB7 DA71 DQA7 DA7 DA16 DA25 DA34 DA44 DA52 DA61 DA70 When M = 1, he MA and MB fields conrol wriing of individual daa byes. When M = 0, all daa byes are wriing uncondiionally. DQA1 DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64 Each bi of he MA7...MA0 field conrols wriing (= 1) or no wriing (= 0) of he indicaed DA bis when he M bi of he COLM packe is one. DQA0 DA0 MA0 DA9 MA1 DA18 MA2 DA27 MA3 DA36 MA4 DA45 MA5 DA54 MA6 DA63 MA7 SPA04209 Figure 5 Mapping Beween COLM Packe and D Packe for WR Command Daa Book

17 ROW-o-ROW Packe Ineracion T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CTM/CFM ROW2... ROW0 ROPa a0 RRDELAY ROPb b0 COL4...COL0 DQA8...0 DQB8...0 Transacion a: ROPa Transacion b: ROPb a0 = {Da, Ba, Ra} b0 = {Db, Bb, Rb} SPT04210 Figure 6 ROW-o-ROW Packe Ineracion-Timing Figure 6 shows wo packes on he ROW pins separaed by an inerval RRDELAY which depends upon he packe conens. No oher ROW packes are sen o banks {Ba, Ba+1, Ba-1} beween packe a and packe b unless noed oherwise. Table 11 summarizes he RRDELAY values for all possible cases. Cases RR1 hrough RR4 show wo successive ACT commands. In case RR1, here is no resricion since he ACT commands are o differen devices. In case RR2, he RR resricion applies o he same device wih non-adjacen banks. Cases RR3 and RR4 are illegal (as shown) since bank Ba needs o be precharged. If a PRER o Ba, Ba+1, or Ba-1 is insered, RRDELAY is RC ( RAS o he PRER command, and RP o he nex ACT). Cases RR5 hrough RR8 show an ACT command followed by a PRER command. In cases RR5 and RR6, here are no resricions since he commands are o differen devices or o non-adjacen banks of he same device. In cases RR7 and RR8, he RAS resricion means he acivaed bank mus wai before i can be precharged. Cases RR9 hrough RR12 show a PRER command followed by an ACT command. In cases RR9 and RR10, here are essenially no resricions since he commands are o differen devices or o non-adjacen banks of he same device. RR10a and RR10b depend upon wheher a brackeed bank (Ba ± 1) is precharged or acivaed. In cases RR11 and RR12, he same and adjacen banks mus all wai RP for he sense amp and bank o precharge before being acivaed. Daa Book

18 Table 11 ROW-o-ROW Packe Ineracion - Rules Case # ROPa Da Ba Ra ROPb Db Bb Rb RRDELAY Example RR1 ACT Da Ba Ra ACT /= Da xxxx x x PACKET Figure 11 RR2 ACT Da Ba Ra ACT == Da /= {Ba, Ba+1, Ba-1} x x RR Figure 11 RR3 ACT Da Ba Ra ACT == Da == {Ba+1, Ba-1} x x RC - illegal unless Figure 10 PRER o Ba/Ba+1/Ba-1 RR4 ACT Da Ba Ra ACT == Da == {Ba} x x RC - illegal unless Figure 10 PRER o Ba/Ba+1/Ba-1 RR5 ACT Da Ba Ra PRER /= Da xxxx x x PACKET Figure 11 RR6 ACT Da Ba Ra PRER == Da /= {Ba, Ba+1, Ba-1} x x PACKET Figure 11 RR7 ACT Da Ba Ra PRER == Da == {Ba+1, Ba-1} x x RAS Figure 10 RR8 ACT Da Ba Ra PRER == Da == {Ba} x x RAS Figure 15 RR9 PRER Da Ba Ra ACT /= Da xxxx x x PACKET Figure 12 RR10 PRER Da Ba Ra ACT == Da /= {Ba, Ba±1, x x PACKET Figure 12 Ba±2} RR10a PRER Da Ba Ra ACT == Da == {Ba+2} x x PACKET / RP if Ba+1 is precharged/acivaed. RR10b PRER Da Ba Ra ACT == Da == {Ba-2} x x PACKET / RP if Ba-1 is precharged/acivaed. RR11 PRER Da Ba Ra ACT == Da == {Ba+1, Ba-1} x x RP Figure 10 RR12 PRER Da Ba Ra ACT == Da == {Ba} x x RP Figure 10 RR13 PRER Da Ba Ra PRER /= Da xxxx x x PACKET Figure 12 RR14 PRER Da Ba Ra PRER == Da /= {Ba, Ba+1, Ba-1} x x PP Figure 12 RR15 PRER Da Ba Ra PRER == Da == {Ba+1, Ba-1} x x PP Figure 12 RR16 PRER Da Ba Ra PRER == Da == Ba x x PP Figure 12 ROW-o-ROW Ineracion (con d) Cases RR13 hrough RR16 summarize he combinaions of wo successive PRER commands. In case RR13 here is no resricion since wo devices are addressed. In RR14, PP applies, since he same device is addressed. In RR15 and RR16, he same bank or an adjacen bank may be given repeaed PRER commands wih only he PP resricion. Two adjacen banks can be acivae simulaneously. A precharge command o one bank will hus affec he sae of he adjacen banks (and sense amps). If bank Ba is acivae and a PRER is direced o Ba, hen bank Ba will be precharged along wih sense amps Ba-1/Ba and Ba/Ba+1. If bank Ba+1 is acivae and a PRER is direced o Ba, hen bank Ba+1 will be precharged along wih sense amps Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is acivae and a PRER is direced o Ba, hen bank Ba-1 will be precharged along wih sense amps Ba/Ba-1 and Ba-1/Ba-2. A ROW packe may conain commands oher han ACT or PRER. The REFA and REFP commands are equivalen o ACT and PRER for ineracion analysis purposes. The ineracion rules of he NAPR, NAPRC, PDNR, RLXR, ATTN, TCAL, and TCEN commands are discussed in laer secions (see Table 8 for cross-ref). Daa Book

19 ROW-o-COL Packe Ineracion Figure 7 shows wo packes on he ROW and COL pins. They mus be separaed by an inerval RCDELAY which depends upon he packe conens. Table 12 summarizes he RCDELAY values for all possible cases. Noe ha if he COL packe is earlier han he ROW packe, i is considered a COL-o-ROW packe ineracion. Cases RC1 hrough RC5 summarize he rules when he ROW packe has an ACT command. Figure 15 and Figure 16 show examples of RC5 - an acivaion followed by a read or wrie. RC4 is an illegal siuaion, since a read or wrie of a precharged banks is being aemped (remember ha for a bank o be acivaed, adjacen banks mus be precharged). In cases RC1, RC2, and RC3, here is no ineracion of he ROW and COL packes. CTM/CFM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 RCDELAY ROW2... ROW0 ROPa a0 COL4...COL0 COPb b1 DQA8...0 DQB8...0 Transacion a: ROPa Transacion b: COPb a0 = {Da, Ba, Ra} b1 = {Db, Bb, Cb1} SPT04211 Figure 7 ROW-o-COL Packe Ineracion - Timing Cases RC6 hrough RC8 summarize he rules when he ROW packe has a PRER command. There is eiher no ineracion (RC6 hrough RC9) or an illegal siuaion wih a read or wrie of a precharged bank (RC9). The COL pins can also schedule a precharge operaion wih a RDA, WRA, or PREC command in a COLC packe or a PREX command in a COLX packe. The consrains of hese precharge operaions may be convered o equivalen PRER command consrains using he rules summarized in Figure 14. Daa Book

20 Table 12 ROW-o-COL Packe Ineracion - Rules Case # ROPa Da Ba Ra COPb Db Bb Cb1 RCDELAY Example RC1 ACT Da Ba Ra NOCOP, RD, reire /= Da xxxx x x 0 RC2 ACT Da Ba Ra NOCOP == Da xxxx x x 0 RC3 ACT Da Ba Ra RD, reire == Da /= {Ba, Ba+1, Ba-1} x x 0 RC4 ACT Da Ba Ra RD, reire == Da == {Ba+1, Ba-1} x x Illegal RC5 ACT Da Ba Ra RD, reire == Da == Ba x x RCD Figure 15 RC6 PRER Da Ba Ra NOCOP, RD, reire /= Da xxxx x x 0 RC7 PRER Da Ba Ra NOCOP == Da xxxx x x 0 RC8 PRER Da Ba Ra RD, reire == Da /= {Ba, Ba+1, Ba-1} x x 0 RC9 PRER Da Ba Ra RD, reire == Da == {Ba+1, Ba-1} x x Illegal COL-o-COL Packe Ineracion CTM/CFM ROW2... ROW0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CCDELAY COL4...COL0 COPa a1 COPb b1 COPc c1 DQA8...0 DQB8...0 Transacion a: COPa Transacion b: COPb Transacion c: COPc a1 = {Da, Ba, Ca1} b1 = {Db, Bb, Cb1} c1 = {Dc, Bc, Cc1} SPT04212 Figure 8 COL-o-COL Packe Ineracion-Timing Figure 8 shows hree arbirary packes on he COL pins. Packes b and c mus be separaed by an inerval CCDELAY which depends upon he command and address values in all hree packes. Table 13 summarizes he CCDELAY values for all possible cases. Cases CC1 hrough CC5 summarize he rules for every siuaion oher han he case when COPb is a WR command and COPc is a RD command. In CC3, when a RD command is followed by a WR command, a gap of CAC CWD mus be insered beween he wo COL packes. See Figure 4 for more explanaion of why his gap is needed. For cases CC1, CC2, CC4, and CC5, here is no resricion ( CCDELAY is CC ). Daa Book

21 In cases CC6 hrough CC10, COPb is a WR command and COPc is a RD command. The CCDELAY value needed beween hese wo packes depends upon he command and address in he packe wih COPa. In paricular, in case CC6 when here is WR-WR-RD command sequence direced o he same device, a gap will be needed beween he packes wih COPb and COPc. The gap will need a COLC packe wih a NOCOP command direced o any device in order o force an auomaic reire o ake place. Figure 18 (righ) provides a more deailed explanaion of his case. In case CC10, here is a RD-WR-RD sequence direced o he same device. If a prior wrie o he same device is unreired when COPa is issued, hen a gap will be needed beween he packes wih COPb and COPc as in case CC6. The gap will need a COLC packe wih a NOCOP command direced o any device in order o force an auomaic reire o ake place. Cases CC7, CC8, and CC9 have no resricion ( CCDELAY is CC ). For he purposes of analyzing COL-o-ROW ineracions, he PREC, WRA, and RDA commands of he COLC packe are equivalen o he NOCOP, WR, and RD commands. These commands also cause a precharge operaion PREC o ake place. This precharge may be convered o an equivalen PRER command on he ROW pins using he rules summarized in Figure 14. Table 13 COL-o-COL Packe Ineracion - Rules Case # COPa Da Ba Ca1 COPb Db Bb Cb1 COPc Dc Bc Cc1 CCDELAY Example CC1 xxxx xxxxx x x x x NOCOP Db Bb Cb1 xxxx xxxxx x x x x CC CC2 xxxx xxxxx x x x x RD,WR Db Bb Cb1 NOCOP xxxxx x x x x CC CC3 xxxx xxxxx x x x x RD Db Bb Cb1 WR xxxxx x x x x CC + CAC - CWD Figure 4 CC4 xxxx xxxxx x x x x RD Db Bb Cb1 RD xxxxx x x x x CC Figure 15 CC5 xxxx xxxxx x x x x WR Db Bb Cb1 WR xxxxx x x x x CC Figure 16 CC6 WR == Db x x x WR Db Bb Cb1 RD == Db x x x x RTR Figure 18 CC7 WR == Db x x x WR Db Bb Cb1 RD /= Db x x x x CC CC8 WR /= Db x x x WR Db Bb Cb1 RD == Db x x x x CC CC9 NOCOP == Db x x x WR Db Bb Cb1 RD == Db x x x x CC CC10 RD == Db x x x WR Db Bb Cb1 RD == Db x x x x CC Daa Book

22 COL-o-ROW Packe Ineracion T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CTM/CFM CRDELAY ROW2... ROW0 ROPb b0 COL4...COL0 COPa a1 DQA8...0 DQB8...0 Transacion a: COPa Transacion b: ROPb a1 = {Da, Ba, Ca1} b0 = {Db, Bb, Rb} SPT04213 Figure 9 COL-o-ROW Packe Ineracion - Timing Figure 9 shows arbirary packes on he COL and ROW pins. They mus be separaed by an inerval CRDELAY which depends upon he command and address values in he packes. Table 14 summarizes he CRDELAY value for all possible cases. Cases CR1, CR2, CR3, and CR9 show no ineracion beween he COL and ROW packes, eiher because one of he commands is a NOP or because he packes are direced o differen devices or o non-adjacen banks. Case CR4 is illegal because an already-acivaed bank is o be re-acivaed wihou being precharged Case CR5 is illegal because an adjacen bank can be acivaed or precharged unil bank Ba is precharged firs. In case CR6, he COLC packe conains a RD command, and he ROW packe conains a PRER command for he same bank. The RDP parameer specifies he required spacing. Likewise, in case CR7, he COLC packe causes an auomaic reire o ake place, and he ROW packe conains a PRER command for he same bank. The RTP parameer specifies he required spacing. Case CR8 is labeled Hazardous because a WR command should always be followed by an auomaic reire before a precharge is scheduled. Figure 19 shows an example of wha can happen when he reire is no able o happen before he precharge. For he purposes of analyzing COL-o-ROW ineracions, he PREC, WRA, and RDA commands of he COLC packe are equivalen o he NOCOP, WR, and RD commands. These commands also cause a precharge operaion o ake place. This precharge may convered o an equivalen PRER command on he ROW pins using he rules summarized in Figure 14. A ROW packe may conain commands oher han ACT or PRER. The REFA and REFP commands are equivalen o ACT and PRER for ineracion analysis purposes. The ineracion rules of he NAPR, PDNR, and RLXR commands are discussed in a laer secion. Daa Book

23 Table 14 COL-o-ROW Packe Ineracion - Rules Case # COPa Da Ba Ca1 ROPb Db Bb Rb CRDELAY Example CR1 NOCOP Da Ba Ca1 x x xxxxx xxxx x x 0 CR2 RD/WR Da Ba Ca1 x x /= Da xxxx x x 0 CR3 RD/WR Da Ba Ca1 x x == Da /= {Ba, Ba+1, Ba-1} x x 0 CR4 RD/WR Da Ba Ca1 ACT == Da == {Ba} x x Illegal CR5 RD/WR Da Ba Ca1 ACT == Da == {Ba+1, Ba-1} x x Illegal CR6 RD Da Ba Ca1 PRER == Da == {Ba, Ba+1, Ba-1} x x RDP Figure 15 CR7 reire 1) Da Ba Ca1 PRER == Da == {Ba, Ba+1, Ba-1} x x RTP Figure 16 CR8 WR 2) Da Ba Ca1 PRER == Da == {Ba, Ba+1, Ba-1} x x 0 Figure 19 CR9 xxxx Da Ba Ca1 NOROP xxxxx xxxx x x 0 1) This is any command which permis he wrie buffer of device Da o reire (see Table 9). Ba is he bank address in he wrie buffer. 2) This siuaion is hazardous because he wrie buffer will be lef unreired while he argeed bank is precharged. See Figure 19. Daa Book

24 ROW-o-ROW Examples Figure 10 shows examples of some of he ROW-o-ROW packe spacings from Table 11. A complee sequence of acivae and precharge commands is direced o a bank. The RR8 and RR12 rules apply o his sequence. In addiion o saisfying he RAS and RP iming parameers, he separaion beween ACT commands o he same bank mus also saisfy he RC iming parameer (RR4). When a bank is acivaed, i is necessary for adjacen banks o remain precharged. As a resul, he adjacen banks will also saisfy parallel iming consrains; in he example, he RR11 and RR3 rules are analogous o he RR12 and RR4 rules. Same Device Same Device Same Device Same Device Same Device Adjacen Bank Adjacen Bank Same Bank Adjacen Bank Same Bank RR7 RR3 RR4 RR11 RR12 a0 = {Da, Ba, Ra} a1 = {Da, Ba+1} b0 = {Da, Ba+1, Rb} b0 = {Da, Ba, Rb} b0 = {Da, Ba+1, Rb} b0 = {Da, Ba, Rb} T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM ROW2... ROW0 ACT a0 PRER a1 ACT b0 RAS RP COL4...COL0 RC DQA8...0 DQB8...0 SPA04214 Figure 10 Row Packe Example Figure 11 shows examples of he ACT-o-ACT (RR1, RR2) and ACT-o-PRER (RR5, RR6) command spacings from Table 11. In general, he commands in ROW packes may be spaced an inerval PACKET apar unless hey are direced o he same or adjacen banks or unless hey are a similar command ype (boh PRER or boh ACT) direced o he same device. Daa Book

25 Differen Device Any Bank Same Device Differen Device Non-adjacen Bank Any Bank Same Device Non-adjacen Bank RR1 RR2 RR5 RR6 a0 = {Da, Ba, Ra} b0 = {Db, Bb, Rb} c0 = {Da, Bc, Rc} b0 = {Db, Bb, Rb} c0 = {Da, Bc, Rc} T0 T1 T2 T3 T4 T5 T6 T7 T8 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM ROW2... ROW0 ACT a0 PACKET ACT b0 ACT a0 RR ACT c0 ACT a0 PACKET PRER b0 ACT a0 PACKET PRER c0 COL4...COL0 DQA8...0 DQB8...0 SPA04215 Figure 11 Row Packe Example Figure 12 shows examples of he PRER-o-PRER (RR13, RR14) and PRER-o-ACT (RR9, RR10) command spacings from Table 12. The RR15 and RR16 cases (PRER-o-PRER o same or adjacen banks) are no shown, bu are similar o RR14. In general, he commands in ROW packes may be spaced an inerval PACKET apar unless hey are direced o he same or adjacen banks or unless hey are a similar command ype (boh PRER or boh ACT) direced o he same device. Daa Book

26 Differen Device Any Bank RR13 Same Device Non-adjacen Bank RR14 Same Device Same Device Differen Device Adjacen Bank Same Bank Any Bank RR15 RR16 RR9 Same Device Non-adjacen Bank RR10 a0 = {Da, Ba, Ra} b0 = {Db, Bb, Rb} c0 = {Da, Bc, Rc} c0 = {Da, Ba, Rc} c0 = {Da, Ba+1, Rc} b0 = {Db, Bb, Rb} c0 = {Da, Bc, Rc} T0 T1 T2 T3 T4 T5 T6 T7 T8 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T39 T40 T41 T42 T43 T44 T45 T46 T47 CTM/CFM ROW2... ROW0 PRER a0 PACKET PRER b0 PRER a0 PP PRER c0 PRER a0 PACKET ACT b0 PRER a0 PACKET ACT c0 COL4...COL0 DQA8...0 DQB8...0 SPA04216 Figure 12 Row Packe Examples Row and Column Cycle Descripion Acivae: A row cycle begins wih he acivae (ACT) operaion. The acivaion process is desrucive; he ac of sensing he value of a bi in a bank s sorage cell ransfers he bi o he sense amp, bu leaves he original bi in he sorage cell wih an incorrec value. Resore: Because he acivaion process is desrucive, a hidden operaion called resore is auomaically performed. The resore operaion rewries he bis in he sense amp back ino he sorage cells of he acivaed row of he bank. Read/Wrie: While he resore operaion akes place, he sense amp may be read (RD) and wrien (WR) using column operaions. If new daa is wrien ino he sense amp, i is auomaically forwarded o he sorage cells of he bank so he daa in he acivaed row and he daa in he sense amp remain idenical. Precharge: When boh he resore operaion and he column operaions are compleed, he sense amp and bank are precharged (PRE). This leaves hem in he proper sae o begin anoher acivae operaion. Inervals: The acivae operaion requires he inerval RCD,MIN o complee. The hidden resore operaion requires he inerval RAS,MIN RCD,MIN o complee. Column read and wrie operaions are also performed during he RAS,MIN RCD,MIN inerval (if more han abou four column operaions are Daa Book

27 performed, his inerval mus be increased). The precharge operaion requires he inerval RP,MIN o complee. Adjacen Banks: An RDRAM wih a s designaion (256K 32s 16/18) indicaes i conains spli banks. This means he sense amps are shared beween wo adjacen banks. The only excepion is ha sense amp 0, 15, 30, and 31 are no shared. When a row in a bank is acivaed, he wo adjacen sense amps are conneced o (associaed wih) ha bank and are no available for use by he wo adjacen banks. These wo adjacen banks mus remain precharged while he seleced bank goes hrough is acivae, resore, read/wrie, and precharge operaions. For example (referring o he block diagram of Figure 2), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will boh be loaded wih one of he 512 rows (wih 512 byes loaded ino each sense amp from he 1 Kbye row byes o he DQA side and 256 byes o he DQB side). While his row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of he sense amp sharing. Precharge Mechanisms Figure 13 shows an example of precharge wih he ROWR packe mechanism. The PRER command mus occur a ime RAS afer he ACT command, and a ime RP before he nex ACT command. This iming will serve as a baseline agains which he oher precharge mechanisms can be compared. a0 = {Da, Ba, Ra} a5 = {Da, Ba} b0 = {Da, Ba, Rb} CTM/CFM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 ROW2... ROW0 ACT a0 PRER a5 ACT b0 RAS RP COL4...COL0 RC DQA8...0 DQB8...0 Figure 13 Precharge via PRER Command in ROWR Packe SPA04217 Figure 14 (op) shows an example of precharge wih a RDA command. A bank is acivaed wih an ROWA packe on he ROW pins. Then, a series of four dualocs are read wih RD commands in COLC packes on he COL pins. The fourh of hese commands is a RDA, which causes he bank o auomaically precharge when he final read has finished. The iming of his auomaic precharge is equivalen o a PRER command in an ROWR packe on he ROW pins ha is offse a ime OFFP Daa Book

28 from he COLC packe wih he RDA command. The RDA command should be reaed as a RD command in a COLC packe as well as a simulaneous (bu offse) PRER command in an ROWR packe when analyzing ineracions wih oher packes. Figure 14 (middle) shows an example of precharge wih a WRA command. As in he RDA example, a bank is acivaed wih an ROWA packe on he ROW pins. Then, wo dualocs are wrien wih WR commands in COLC packes on he COL pins. The second of hese commands is a WRA, which causes he bank o auomaically precharge when he final wrie has been reired. The iming of his auomaic precharge is equivalen o a PRER command in an ROWR packe on he ROW pins ha is offse a ime OFFP from he COLC packe ha causes he auomaic reire. The WRA command should be reaed as a WR command in a COLC packe as well as a simulaneous (bu offse) PRER command in an ROWR packe when analyzing ineracions wih oher packes. Noe ha he auomaic reire is riggered by a COLC packe a ime RTR afer he COLC packe wih he WR command unless he second COLC conains a RD command o he same device. This is described in more deail in Figure 17. Figure 14 (boom) shows an example of precharge wih a PREX command in an COLX packe. A bank is acivaed wih an ROWA packe on he ROW pins. Then, a series of four dualocs are read wih RD commands in COLC packes on he COL pins. The fourh of hese COLC packes includes an COLX packe wih a PREX command. This causes he bank o precharge wih iming equivalen o a PRER command in an ROWR packe on he ROW pins ha is offse a ime OFFP from he COLX packe wih he PREX command. Daa Book

29 COLC Packe: RDA Precharge Offse CTM/CFM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 The RDA precharge is equivalen o a PRER command here ROW2... ROW0 ACT a0 PRER a5 ACT b0 OFFP COL4...COL0 RD a1 RD a2 RD a3 RD a4 DQA8...0 DQB8...0 Q (a1) Q (a2) Q (a3) Q (a4) Transacion a: RD COLC Packe: WRA Precharge Offse CTM/CFM T0 T1 T2 T3 T4 a0 = {Da, Ba, Ra} a1 = {Da, Ba, Ca1} a3 = {Da, Ba, Ca3} a2 = {Da, Ba, Ca2} a4 = {Da, Ba, Ca4} T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 The WRA precharge (riggered by he auomaic reire) is equivalen o a PRER command here a5 = {Da, Ba} T45 T46 T47 ROW2... ROW0 ACT a0 PRER a5 ACT b0 RTR OFFP COL4...COL0 WR a1 WRA a2 reire (a1) MSK (a1) reire (a2) MSK (a2) DQA8...0 DQB8...0 D (a1) D (a2) Transacion a: WR a0 = {Da, Ba, Ra} a1 = {Da, Ba, Ca1} a2 = {Da, Ba, Ca2} a5 = {Da, Ba} COLC Packe: PREX Precharge Offse CTM/CFM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 The PREX precharge is equivalen o a PRER command here T45 T46 T47 ROW2... ROW0 ACT a0 PRER a5 ACT b0 OFFP COL4...COL0 RD a1 RD a2 RD a3 RD a4 PREX a5 DQA8...0 DQB8...0 Q (a1) Q (a2) Q (a3) Q (a4) Transacion a: RD a0 = {Da, Ba, Ra} a1 = {Da, Ba, Ca1} a3 = {Da, Ba, Ca3} a2 = {Da, Ba, Ca2} a4 = {Da, Ba, Ca4} a5 = {Da, Ba} SPA04218 Figure 14 Offses for Alernae Precharge Mechanisms Daa Book

30 Read Transacion - Example Figure 15 shows an example of a read ransacion. I begins by acivaing a bank wih an ACT a0 command in an ROWA packe. A ime RCD laer a RD a1 command is issued in a COLC packe. Noe ha he ACT command includes he device, bank, and row address (abbreviaed as a0) while he RD command includes device, bank, and column address (abbreviaed as a1). A ime CAC afer he RD command he read daa dualoc Q(a1) is reurned by he device. Noe ha he packes on he ROW and COL pins use he end of he packe as a iming reference poin, while he packes on he DQA/DQB pins use he beginning of he packe as a iming reference poin. A ime CC afer he firs COLC packe on he COL pins a second is issued. I conains a RD a2 command. The a2 address has he same device and bank address as he a1 address (and a0 address), bu a differen column address. A ime CAC afer he second RD command a second read daa dualoc Q(a2) is reurned by he device. Nex, a PRER a3 command is issued in an ROWR packe on he ROW pins. This causes he bank o precharge so ha a differen row may be acivaed in a subsequen ransacion or so ha an adjacen bank may be acivaed. The a3 address includes he same device and bank address as he a0, a1, and a2 addresses. The PRER command mus occur a ime RAS or more afer he original ACT command (he acivaion operaion in any DRAM is desrucive, and he conens of he seleced row mus be resored from he wo associaed sense amps of he bank during he RAS inerval). The PRER command mus also occur a ime RDP or more afer he las RD command. Noe ha he RDP value shown is greaer han he RDP,MIN specificaion in Table 23. This ransacion example reads wo dualocs, bu here is acually enough ime o read hree dualocs before RDP becomes he limiing parameer raher han RAS. If four dualocs were read, he packe wih PRER would need o shif righ (be delayed) by one CYCLE (noe - his case is no shown). Finally, an ACT b0 command is issued in an ROWR packe on he ROW pins. The second ACT command mus occur a ime RC or more afer he firs ACT command and a ime RP or more afer he PRER command. This ensures ha he bank and is associaed sense amps are precharged. This example assumes ha he second ransacion has he same device and bank address as he firs ransacion, bu a differen row address. Transacion b may no be sared unil ransacion a has finished. However, ransacions o oher banks or oher devices may be issued during ransacion a Daa Book