Sequential Circuits. Building Block: Flip-Flops

Size: px
Start display at page:

Download "Sequential Circuits. Building Block: Flip-Flops"

Transcription

1 Tele 26 Sequential ircuits State epenent Present State Next State ompose of ombinational ircuits Storage Elements Often Require a lock Regular Pulse Train efinitions Perio With Rising Ege Trailing Ege The Spee of a Sequential ircuit is the Spee of the lock Sequential ircuits - Tele 26 uiling lock: Flip-Flops asic Unit of Sequential ircuits an ssume iscrete States State hanges a Function of the Inputs May or May Not e locke Sequential ircuits - 2

2 Tele 26 Set-Reset (SR) S S R Set Reset R x x Unefine Sequential ircuits - 3 Tele 26 Set-Reset with lock S S R Next State of x x No hange No hange Reset R Set Ineterminate Sequential ircuits - 4

3 Tele 26 (ata) Flip Flop Next State of x No hange = = Sequential ircuits - 5 Tele 26 - Flip Flop Next State of x x No hange No hange (=) Reset (=) Set (=) Invert State (=) Sequential ircuits - 6

4 Tele 26 T (Toggle) Flip Flop T T Next State of x No hange No hange (=) Invert State (=) Sequential ircuits - 7 Tele 26 Summary of Flip Flop haracteristic Tables S R (t+) T (t+) (t)??? (t) (t) (t+) (t) (t) (t+) Sequential ircuits - 8

5 Tele 26 nalysis proceure Ientify Inputs To the System To the Flip Flops Input Equations efine the Relationship etween the System Inputs an the FF Inputs Write State Table omponents Inputs States Outputs reate Relationships mong These omponents reate State iagrams Use for nalysis of Sequential ircuits Graphical Representation of the State Table Sequential ircuits - 9 Tele 26 Example Y 2 Z Y Y 2 Y Y 2 lock Sequential ircuits -

6 Tele 26 Example: Flip-Flop Input/Output Equations Flip Flop Input Equations =Y 2 =+Y 2 =Y Y 2 + Y 2 Output Equation: Z = Y Y 2 Sequential ircuits - Tele 26 Example: Flip-Flop Truth Tables Y Y 2 Y Y 2 Y Y 2 Y Y 2 Y (t+) Y Y 2 Y Y 2 Sequential ircuits - 2 Y 2 (t+)

7 Tele 26 Example: System Tables Transition Table State Table Output Table State Y Y 2 Y Y 2 (t+) Y Y 2 (t+) Z Sequential ircuits - 3 Tele 26 Example: State iagram / / / / / / / Format: Input/Output /Z / Sequential ircuits - 4

8 Tele 26 Sequential ircuit esign Proceure reate a State Table/State iagram From the Problem Statement erive Flip Flop Input Equations From the Next State onitions in the State Table erive Output Functions Simplify Use oolean lgebra Use -Maps raw Logic iagrams Sequential ircuits - 5 Tele 26 Example: Soa Machine Nee a System that Releases a ottle fter $.3 in oins Has een Receive Returns ppropriate hange Nickels imes Inputs Nickel ime uarter Sequential ircuits - 6

9 Tele 26 State iagram efinitions States = $. = $.5 = $. = $.5 E = $.2 F = $.25 G = $.5 Ege Labels N/RN,R,R N = Nickel, ime, uarter (Inputs) RN,R,R = Release Nickel, Release ime, Release ottle (Outputs) Sequential ircuits - 7 Tele 26 Example: State iagram States = =5 = =5 E=2 F=25 G=5 / (by clock) / G / / / / / F / / / / / / / / E / / / / Sequential ircuits - 8

10 Tele 26 Example: State Transition Table States = =5 = =5 E=2 F=25 G=5 Present E F Next State E F E F F G (Input (N)) Sequential ircuits - 9 Tele 26 Example: Observations an Strategy Given the Seven States Ientifie, it is Possible to Implement the System with log 2 7 = 3 Flip Flops Let us rbitrarily Select Flip Flops for This Project We Must Now Ientify the Transition Tables, Input Tables, an Output Tables for Each Flip Flop From These Tables, We an Write Input Output Equations an Reuce Them These Reuce Equations an Then be Use to Prouce a Logic iagram Sequential ircuits - 2

11 Tele 26 Example: Flip Flop Transition an Output Tables Present F/F Outputs Y Y 2 Y 3 (N) Next State (N) Output E F Y Y 2 Y 3 Y Y 2 Y 3 Y Y 2 Y 3 RN,R,R Y Sequential ircuits - 2 Tele 26 Example: Flip-Flop Transition Tables Y Flip Flop Y 2 Flip Flop 2 Y 3 Flip Flop 3 Sequential ircuits - 22

12 Tele 26 Example: Flip-Flop Input Tables What Inputs to Each Flip-Flop re Necessary to Prouce the Require Transition Tables? Y Y 2 Y 3 Flip Flop Flip Flop Flip Flop 3 (t+) (t) (t) Sequential ircuits - 23 (t) (t+) Tele 26 Example: onclusion It is Now Possible to Write Separate Tables for Each Input:, 2, 3 an, 2, 3 From the Iniviual Tables, it is Possible to Write the Equation The Output Equations an be Written from the Output Table Presente Earlier Example: 2 2= YYY 2 3N + YYY 2 3N + YYY 2 3N + YYY 2 3N + YYYN YYY 2 3N Sequential ircuits - 24

13 Tele 26 uiling locks Using Sequential ircuits Registers Stanar Register Shift Register ounters inary Uses of ounters Event ounting Frequency ivier Sequential ircuits - 25 Tele 26 ata Registers Nee One Flip Flop for Each ata it -Type Flip Flops re Preferre Nee a Loa ontrol Signal Nee a lock Signal Sequential ircuits - 26

14 Tele 26 Four it ata Register I I I 2 I 3 Loa Sequential ircuits - 27 lock Tele 26 Shift Register Nee a Loa Signal Parallel Loa Serial Loa Nee a Shift Signal Shift Right Shift Left No Shift Nee a lock Signal Sequential ircuits - 28

15 Tele 26 Simple Four it Serial Loa Shift Register Input Output lock ssume Positive Ege Triggere Flip-Flops Input Timing iagram lock Sequential ircuits - 29 Tele 26 ounters esirable Features Loa lear ount Up or own Types of ounters Ripple ounters Pulses Ripple Through the ounter Variable State hanges cross ounter its inary ounters ll Flip Flops Use the Same lock onsistent State hange cross its Sequential ircuits - 3

16 Tele 26 Four it Ripple ounter Event ssume Negative Ege Triggere Flip-Flops Event Timing iagram Sequential ircuits - 3 Propagation elay Tele 26 Four it Synchronous inary ounter Event ssume Positive Ege Triggere Flip-Flops lock Event Timing iagram lock Sequential ircuits - 32

`COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University

`COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University `OEN 32 IGITL SYSTEMS ESIGN - LETURE NOTES oncordia University hapter 5: Synchronous Sequential Logic NOTE: For more eamples and detailed description of the material in the lecture notes, please refer

More information

Sequential Circuits. Introduction to Digital Logic. Course Outline. Overview. Introduction to Digital Logic. Introduction to Sequential Circuits

Sequential Circuits. Introduction to Digital Logic. Course Outline. Overview. Introduction to Digital Logic. Introduction to Sequential Circuits Introduction to igital Logic Prof. Nizamettin IN naydin@yildiz.edu.tr naydin@ieee.org ourse Outline. igital omputers, Number ystems, rithmetic Operations, ecimal, lphanumeric, and Gray odes 2. inary Logic,

More information

Chapter 6 Sequential Circuits

Chapter 6 Sequential Circuits Overview Logic and omputer esign Fundamentals hapter 6 equential ircuits Part torage Elements and equential ircuit nalysis pring 4 Part - torage Elements and nalysis Introduction to sequential circuits

More information

ECE 25 Introduction to Digital Design. Chapter 5 Sequential Circuits ( ) Part 1 Storage Elements and Sequential Circuit Analysis

ECE 25 Introduction to Digital Design. Chapter 5 Sequential Circuits ( ) Part 1 Storage Elements and Sequential Circuit Analysis EE 25 Introduction to igital esign hapter 5 Sequential ircuits (5.1-5.4) Part 1 Storage Elements and Sequential ircuit Analysis Logic and omputer esign Fundamentals harles Kime & Thomas Kaminski 2008 Pearson

More information

Registers & Counters. Logic and Digital System Design - CS 303 Erkay Savaş Sabanci University

Registers & Counters. Logic and Digital System Design - CS 303 Erkay Savaş Sabanci University Registers & ounters Logic and igital System esign - S 33 Erkay Savaş Sabanci University Registers Registers like counters are clocked sequential circuits A register is a group of flip-flops Each flip-flop

More information

Chapter 3 Unit Combinational

Chapter 3 Unit Combinational EE 2: igital Logic ircuit esign r Radwan E Abdel-Aal, OE Logic and omputer esign Fundamentals hapter 3 Unit ombinational 4 Sequential Logic esign ircuits Part Implementation Technology and Logic esign

More information

Page 1. Some Definitions. Chapter 3: Sequential Logic. Sequential Logic. The Combinational Logic Unit. A NOR Gate with a Lumped Delay

Page 1. Some Definitions. Chapter 3: Sequential Logic. Sequential Logic. The Combinational Logic Unit. A NOR Gate with a Lumped Delay 3- hapter 3 equential Logic hapter 3: equential Logic 3-2 hapter 3 equential Logic ome efinitions r. Tim McGuire am Houston tate University ased on notes by Miles Murdocca ombinational logic: a digital

More information

Chapter 5 Sequential Circuits

Chapter 5 Sequential Circuits Logic and omputer esign Fundamentals hapter 5 Sequential ircuits Part - Storage Elements Part Storage Elements and Sequential ircuit Analysis harles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks

More information

Overview of Chapter 4

Overview of Chapter 4 Overview of hapter 4 Types of equential ircuits torage Elements Latches Flip-Flops equential ircuit nalysis tate Tables tate iagrams equential ircuit esign pecification ssignment of tate odes Implementation

More information

Problems with D-Latch

Problems with D-Latch Problems with -Latch If changes while is true, the new value of will appear at the output. The latch is transparent. If the stored value can change state more than once during a single clock pulse, the

More information

Chapter 5 Sequential Circuits

Chapter 5 Sequential Circuits Logic and omputer Design Fundamentals hapter 5 Sequential ircuits Part 1 Storage Elements and Sequential ircuit Analysis harles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active

More information

Review of digital electronics. Storage units Sequential circuits Counters Shifters

Review of digital electronics. Storage units Sequential circuits Counters Shifters Review of digital electronics Storage units Sequential circuits ounters Shifters ounting in Binary A counter can form the same pattern of 0 s and 1 s with logic levels. The first stage in the counter represents

More information

Chapter 5 Sequential Systems. Introduction

Chapter 5 Sequential Systems. Introduction hapter 5 Seuential Systems Latches and Flip-flops Synchronous ounter synchronous ounter 7822 igital Logic esign @epartment of omputer Engineering U. Introduction Up to now everything has been combinational

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;

More information

Registers & Counters. BME208 Logic Circuits Yalçın İŞLER

Registers & Counters. BME208 Logic Circuits Yalçın İŞLER Registers & ounters BME28 Logic ircuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Registers Registers are clocked sequential circuits A register is a group of flip-flops 2 Each flip-flop capable

More information

Agenda. EE 260: Introduction to Digital Design Counters and Registers. Asynchronous (Ripple) Counters. Asynchronous (Ripple) Counters

Agenda. EE 260: Introduction to Digital Design Counters and Registers. Asynchronous (Ripple) Counters. Asynchronous (Ripple) Counters EE26: igital esign, Spring 28 4/8/8 EE 26: Introduction to igital esign ounters and Registers Yao Zheng epartment of Electrical Engineering University of Hawaiʻi at Mānoa Agenda ounters Introduction: ounters

More information

THE UNIVERSITY OF TRINIDAD & TOBAGO

THE UNIVERSITY OF TRINIDAD & TOBAGO THE UNIVERSITY OF TRINI & TOGO FINL SSESSMENT/EXMINTIONS PRIL/MY 2014 ourse ode and Title: igital Systems and Logic esign Programme: Sc omputer Engineering ate and Time: Wednesday 23 rd. pril, 2014 uration:

More information

ASYNCHRONOUS SEQUENTIAL CIRCUIT CONCEPTS

ASYNCHRONOUS SEQUENTIAL CIRCUIT CONCEPTS ASYNHRONOUS SEQUENTIAL IRUIT ONEPTS Synchronous ircuit Asynchronous ircuit (a) Synchronous to Asynchronous Asynchronous ircuit Asynchronous Signals Synchronous ircuit (b) Asynchronous to Synchronous Synchronous

More information

6. Sequential Logic Flip-Flops

6. Sequential Logic Flip-Flops ection 6. equential Logic Flip-Flops Page of 5 6. equential Logic Flip-Flops ombinatorial components: their output values are computed entirely from their present input values. equential components: their

More information

Sequential Logic. E&CE 223 Digital Circuits and Systems (A. Kennings) Page 1

Sequential Logic. E&CE 223 Digital Circuits and Systems (A. Kennings) Page 1 Sequential Logic E&CE 223 igital Circuits and Systems (A. Kennings) Page 1 Sequential Circuits Have considered only combinational circuits in which circuit outputs are determined entirely by current circuit

More information

Sequential Logic Counters and Registers

Sequential Logic Counters and Registers Sequential Logic ounters and Registers ounters Introduction: ounters Asynchronous (Ripple) ounters Asynchronous ounters with MOD number < 2 n Asynchronous Down ounters ascading Asynchronous ounters svbitec.wordpress.com

More information

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced

More information

ECE 3401 Lecture 12. Sequential Circuits (II)

ECE 3401 Lecture 12. Sequential Circuits (II) EE 34 Lecture 2 Sequential ircuits (II) Overview of Sequential ircuits Storage Elements Sequential circuits Storage elements: Latches & Flip-flops Registers and counters ircuit and System Timing Sequential

More information

COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem   ahmadsm AT kfupm Phone: Office: COE 202: Digital Logic Design Sequential Circuits Part 1 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Sequential Circuits Memory Elements Latches Flip-Flops Combinational

More information

EET2411 DIGITAL ELECTRONICS

EET2411 DIGITAL ELECTRONICS 5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Lecture material adapted from R. Katz, G. Borriello, Contemporary Logic esign (second edition), Prentice-Hall/Pearson

More information

Sequential Logic Circuit

Sequential Logic Circuit Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ` 4 Sequential Logic ircuit hapter-4(hours : Marks: )(269 Principle of Digital Electronics) SEUENTIL LOGI IRUIT 4. Introduction to Sequential Logic

More information

Chapter 6. Flip-Flops and Simple Flip-Flop Applications

Chapter 6. Flip-Flops and Simple Flip-Flop Applications Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic

More information

CSE140: Components and Design Techniques for Digital Systems. More D-Flip-Flops. Tajana Simunic Rosing. Sources: TSR, Katz, Boriello & Vahid

CSE140: Components and Design Techniques for Digital Systems. More D-Flip-Flops. Tajana Simunic Rosing. Sources: TSR, Katz, Boriello & Vahid CSE140: Components and esign Techniques for igital Systems More -Flip-Flops Tajana Simunic Rosing Where we are now. What we covered last time: SRAM cell, SR latch, latch, -FF What we ll do next: -FF review,

More information

ECE 3401 Lecture 11. Sequential Circuits

ECE 3401 Lecture 11. Sequential Circuits EE 3401 Lecture 11 Sequential ircuits Overview of Sequential ircuits Storage Elements Sequential circuits Storage elements: Latches & Flip-flops Registers and counters ircuit and System Timing Sequential

More information

Part 4: Introduction to Sequential Logic. Basic Sequential structure. Positive-edge-triggered D flip-flop. Flip-flops classified by inputs

Part 4: Introduction to Sequential Logic. Basic Sequential structure. Positive-edge-triggered D flip-flop. Flip-flops classified by inputs Part 4: Introduction to Sequential Logic Basic Sequential structure There are two kinds of components in a sequential circuit: () combinational blocks (2) storage elements Combinational blocks provide

More information

1. (1pts) What is the Hamming distance between these two bit patterns: and ?

1. (1pts) What is the Hamming distance between these two bit patterns: and ? . (pts) What is the Hamming istance between these two bit patterns: 00 an 00? 2. (2pts) Write the equation for the carry out of the 4th aer cell in an ALU using carrylookahea, in terms of P s an G s. 3.

More information

CSC Computer Architecture and Organization

CSC Computer Architecture and Organization S 37 - omputer Architecture and Organization Lecture 6: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store n

More information

Spring 2017 EE 3613: Computer Organization Chapter 5: The Processor: Datapath & Control - 1

Spring 2017 EE 3613: Computer Organization Chapter 5: The Processor: Datapath & Control - 1 Spring 27 EE 363: Computer Organization Chapter 5: The Processor: atapath & Control - Avinash Kodi epartment of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 457 E-mail: kodi@ohio.edu

More information

Chapter. Synchronous Sequential Circuits

Chapter. Synchronous Sequential Circuits Chapter 5 Synchronous Sequential Circuits Logic Circuits- Review Logic Circuits 2 Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs

More information

Learning Outcomes. Unit 13. Sequential Logic BISTABLES, LATCHES, AND FLIP- FLOPS. I understand the difference between levelsensitive

Learning Outcomes. Unit 13. Sequential Logic BISTABLES, LATCHES, AND FLIP- FLOPS. I understand the difference between levelsensitive 1.1 1. Learning Outcomes Unit 1 I understand the difference between levelsensitive and edge-sensitive I understand how to create an edge-triggered FF from latches Sequential Logic onstructs 1. 1.4 Sequential

More information

Experiment 8 Introduction to Latches and Flip-Flops and registers

Experiment 8 Introduction to Latches and Flip-Flops and registers Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends

More information

Synchronous Digital Logic Systems. Review of Digital Logic. Philosophy. Combinational Logic. A Full Adder. Combinational Logic

Synchronous Digital Logic Systems. Review of Digital Logic. Philosophy. Combinational Logic. A Full Adder. Combinational Logic Synchronous igital Logic Systems Review of igital Logic Prof. Stephen. Edwards Raw materials: MOS transistors and wires on Is Wires are excellent conveyors of voltage Little leakage Fast, but not instantaneous

More information

Momentary Changes in Outputs. State Machine Signaling. Oscillatory Behavior. Hazards/Glitches. Types of Hazards. Static Hazards

Momentary Changes in Outputs. State Machine Signaling. Oscillatory Behavior. Hazards/Glitches. Types of Hazards. Static Hazards State Machine Signaling Momentary hanges in Outputs Timing ehavior Glitches/hazards and how to avoid them SM Partitioning What to do when the state machine doesn t fit! State Machine Signaling State Machine

More information

Analysis of Sequential Circuits

Analysis of Sequential Circuits NOTE: Explanation Refer lass Notes Digital ircuits(15ee23) Analysis of Sequential ircuits by Nagaraj Vannal, Asst.Professor, School of Electronics Engineering,.L.E. Technological University, Hubballi.

More information

Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

Counters

Counters Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,

More information

Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany

Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs

More information

Chapter 11 Latches and Flip-Flops

Chapter 11 Latches and Flip-Flops Chapter 11 Latches and Flip-Flops SKEE1223 igital Electronics Mun im/arif/izam FKE, Universiti Teknologi Malaysia ecember 8, 2015 Types of Logic Circuits Combinational logic: Output depends solely on the

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

Lecture 8: Sequential Logic

Lecture 8: Sequential Logic Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs

More information

Introduction to Microprocessor & Digital Logic

Introduction to Microprocessor & Digital Logic ME262 Introduction to Microprocessor & Digital Logic (Sequential Logic) Summer 2 Sequential Logic Definition The output(s) of a sequential circuit depends d on the current and past states of the inputs,

More information

Sequential Circuit Design: Part 1

Sequential Circuit Design: Part 1 Sequential ircuit esign: Part 1 esign of memory elements Static latches Pseudo-static latches ynamic latches Timing parameters Two-phase clocking locked inverters Krish hakrabarty 1 Sequential Logic FFs

More information

Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

Introduction. NAND Gate Latch.  Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1 2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The

More information

ECSE-4760 Real-Time Applications in Control & Communications EXPERIMENTS IN DIGITAL LOGIC DESIGN

ECSE-4760 Real-Time Applications in Control & Communications EXPERIMENTS IN DIGITAL LOGIC DESIGN Rensselaer Polytechnic Institute ESE-476 Real-Time pplications in ontrol & ommunications EXPERIMENTS IN IGITL LOGI ESIGN Number of Sessions 4 INTROUTION Over the past few decades the digital world has

More information

Outputs Combinational circuit. Next state. Fig. 4-1 Block Diagram of a Sequential Circuit

Outputs Combinational circuit. Next state. Fig. 4-1 Block Diagram of a Sequential Circuit 4- Inputs Outputs ombinational circuit Next state Storage elements Present state Fig. 4- Block Diagram of a Sequential ircuit 2 Prentice Hall, Inc. 4-2 (a) t pd (b) t pd 2 t pd (d) 2 t pd (c) t pd Fig.

More information

EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP

EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications

More information

Counter dan Register

Counter dan Register Counter dan Register Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory.

More information

Introduction to Sequential Logic Circuits (Class /16/12)

Introduction to Sequential Logic Circuits (Class /16/12) Introduction to Sequential ogic Circuits (Class 8.1 10/16/12) CSE 2441 Introduction to igital ogic Fall 2012 Instructor Bill Carroll, Professor of CSE Sequential circuit models Block diagram State diagrams

More information

Introduction to Sequential Circuits

Introduction to Sequential Circuits Introduction to Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Introduction to Sequential Circuits Synchronous

More information

Unit 11. Latches and Flip-Flops

Unit 11. Latches and Flip-Flops Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,

More information

Registers, Register Transfers and Counters Dr. Fethullah Karabiber

Registers, Register Transfers and Counters Dr. Fethullah Karabiber 36 OMPUTER HARWARE Registers, Register Transfers and ounters r. Fethullah Karabiber Overview 2 Registers, Microoperations and Implementations Registers and load enable Register transfer operations Microoperations

More information

Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops Sequential Circuits: Latches & Flip-Flops Overview Storage Elements Latches SR, JK, D, and T Characteristic Tables, Characteristic Equations, Eecution Tables, and State Diagrams Standard Symbols Flip-Flops

More information

Introduction to Digital Logic Missouri S&T University CPE 2210 Flip-Flops

Introduction to Digital Logic Missouri S&T University CPE 2210 Flip-Flops Introduction to igital Logic Missouri S&T University CPE 2210 Flip-Flops Egemen K. Çetinkaya Egemen K. Çetinkaya epartment of Electrical & Computer Engineering Missouri University of Science and Technology

More information

D Latch (Transparent Latch)

D Latch (Transparent Latch) D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done

More information

Flip-flops, like logic gates are defined by their truth table. Flip-flops are controlled by an external clock pulse. C

Flip-flops, like logic gates are defined by their truth table. Flip-flops are controlled by an external clock pulse. C P517/617 Lec10, P1 eview from last week: Flip-Flops: asic counting unit in computer counters shift registers memory Example: S flip-flop or eset-set flip-flop Flip-flops, like logic gates are defined by

More information

Rangkaian Sekuensial. Flip-flop

Rangkaian Sekuensial. Flip-flop Rangkaian Sekuensial Rangkaian Sekuensial Flip-flop Combinational versus Sequential Functions Logic functions are categorized as being either combinational (sometimes referred to as combinatorial) or sequential.

More information

Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic

Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic Chapter 5. Synchronous Sequential Logic 1 5.1 Introduction Electronic products: ability to send, receive, store, retrieve, and process information in binary format Dependence on past values of inputs Sequential

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of omputer Systems Sequential Logic Martha A. Kim olumbia University Spring 2016 1/1 2/1 Bistable Elements Equivalent circuits; right is more traditional. Two stable states: 0 1 1 0 3/1 S

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

Chapter 6 Registers and Counters

Chapter 6 Registers and Counters EEA051 - Digital Logic 數位邏輯 Chapter 6 Registers and Counters 吳俊興國立高雄大學資訊工程學系 January 2006 Chapter 6 Registers and Counters 6-1 Registers 6-2 Shift Registers 6-3 Ripple Counters 6-4 Synchronous Counters

More information

LATCHES & FLIP-FLOP. Chapter 7

LATCHES & FLIP-FLOP. Chapter 7 LATCHES & FLIP-FLOP Chapter 7 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely

More information

Sequential Logic Circuits

Sequential Logic Circuits Sequential Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory

More information

ASYNCHRONOUS COUNTER CIRCUITS

ASYNCHRONOUS COUNTER CIRCUITS ASYNCHRONOUS COUNTER CIRCUITS Asynchronous counters do not have a common clock that controls all the Hipflop stages. The control clock is input into the first stage, or the LSB stage of the counter. The

More information

CHAPTER1: Digital Logic Circuits

CHAPTER1: Digital Logic Circuits CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback

More information

Logic Design IS1200, spring 2015 Review Slides

Logic Design IS1200, spring 2015 Review Slides 2 I2, spring 25 Review lides ssociate Professor, KTH Royal Institute of Technology ssistant Research ngineer, University of alifornia, erkeley genda I lides version. I 3 umber ystems (/3) ecimal and inary

More information

Sri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering

Sri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering Sri Vidya College of Engineering And Technology Virudhunagar 626 005 Department of Electrical and Electronics Engineering Year/ Semester/ Class : II/ III/ EEE Academic Year: 2017-2018 Subject Code/ Name:

More information

Logic Design. Flip Flops, Registers and Counters

Logic Design. Flip Flops, Registers and Counters Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and

More information

Registers and Counters

Registers and Counters Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of

More information

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state

More information

EECS 270 Midterm Exam Spring 2011

EECS 270 Midterm Exam Spring 2011 EES 270 Midterm Exam Spring 2011 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points 2 /15 3 /10 4 /6 5 /12

More information

ALGORITHMS IN HW EECS150 ALGORITHMS IN HW. COMBINATIONAL vs. SEQUENTIAL. Sequential Circuits ALGORITHMS IN HW

ALGORITHMS IN HW EECS150 ALGORITHMS IN HW. COMBINATIONAL vs. SEQUENTIAL. Sequential Circuits ALGORITHMS IN HW LGOITHM HW EEC150 ection 2 Introduction to equential Logic Fall 2001 pproach #2: Combinational divide & conquer a[0] a[1] a[1022] a[1023] MX MX MX 512 + 256 + K+ 1 = 1023 blocks Each MX block has: 64 s;

More information

Sequential Logic and Clocked Circuits

Sequential Logic and Clocked Circuits Sequential Logic and Clocked Circuits Clock or Timing Device Input Variables State or Memory Element Combinational Logic Elements From combinational logic, we move on to sequential logic. Sequential logic

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 281: igital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative

More information

MC9211 Computer Organization

MC9211 Computer Organization MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 281: igital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative

More information

EE 109 Homework 6 State Machine Design Name: Score:

EE 109 Homework 6 State Machine Design Name: Score: EE 9 Homework 6 State Machine esign Name: Score: ue: See Blackboard Blackboard ONLY Submission. While the Blackboard submission may not require you to go through all the design steps (such as drawing out

More information

CHAPTER 6 COUNTERS & REGISTERS

CHAPTER 6 COUNTERS & REGISTERS CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register

More information

Outline. CPE/EE 422/522 Advanced Logic Design L03. Review: Clocked D Flip-Flop with Rising-edge Trigger. Sequential Networks

Outline. CPE/EE 422/522 Advanced Logic Design L03. Review: Clocked D Flip-Flop with Rising-edge Trigger. Sequential Networks Outline PE/EE 422/522 Advanced Logic Design L3 Electrical and omputer Engineering University of Alabama in Huntsville What we know ombinational Networks Analysis, Synthesis, Simplification, Buiing Blocks,

More information

Introduction. Serial In - Serial Out Shift Registers (SISO)

Introduction. Serial In - Serial Out Shift Registers (SISO) Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes

More information

COMP sequential logic 1 Jan. 25, 2016

COMP sequential logic 1 Jan. 25, 2016 OMP 273 5 - sequential logic 1 Jan. 25, 2016 Sequential ircuits All of the circuits that I have discussed up to now are combinational digital circuits. For these circuits, each output is a logical combination

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

More information

Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.

Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active. Flip-Flops Objectives The objectives of this lesson are to study: 1. Latches versus Flip-Flops 2. Master-Slave Flip-Flops 3. Timing Analysis of Master-Slave Flip-Flops 4. Different Types of Master-Slave

More information

CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

More information

EE292: Fundamentals of ECE

EE292: Fundamentals of ECE EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 23 121120 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Combinatorial Logic Sequential Logic 3 Combinatorial Logic Circuits

More information

! Two inverters form a static memory cell " Will hold value as long as it has power applied

! Two inverters form a static memory cell  Will hold value as long as it has power applied equential Logic! equential Circuits " imple circuits with feedback " Latches " Edge-triggered flip-flops! Timing Methodologies " Cascading flip-flops for proper operation " Clock skew! Basic egisters "

More information

Sequential Logic. Sequential Circuits. ! Timing Methodologies " Cascading flip-flops for proper operation " Clock skew

Sequential Logic. Sequential Circuits. ! Timing Methodologies  Cascading flip-flops for proper operation  Clock skew equential Logic! equential Circuits " imple circuits with feedback " Latches " Edge-triggered flip-flops! Timing Methodologies " Cascading flip-flops for proper operation " Clock skew! Basic egisters "

More information

CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

More information

Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers

Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and

More information

The word digital implies information in computers is represented by variables that take a limited number of discrete values.

The word digital implies information in computers is represented by variables that take a limited number of discrete values. Class Overview Cover hardware operation of digital computers. First, consider the various digital components used in the organization and design. Second, go through the necessary steps to design a basic

More information

Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements

Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #3 Flip Flop Storage

More information

Registers and Counters

Registers and Counters Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of

More information

CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M

CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M CSE-4523 Latches and Flip-flops Dr. Izadi NOR gate property: A B Z A B Z Cross coupled NOR gates: S M S R M R S M R S R S R M S S M R R S ' Gate R Gate S R S G R S R (t+) S G R Flip_flops:. S-R flip-flop

More information

Logic Design ( Part 3) Sequential Logic- Finite State Machines (Chapter 3)

Logic Design ( Part 3) Sequential Logic- Finite State Machines (Chapter 3) Logic esign ( Part ) Sequential Logic- Finite State Machines (Chapter ) Based on slides McGraw-Hill Additional material 00/00/006 Lewis/Martin Additional material 008 Roth Additional material 00 Taylor

More information