MPW Service Center for ICs, Photonics & MEMS Prototyping & Low Volume Production

Transcription

1 Circuits Multi-Projets From Layout to chips 2016 Annual Report Courtesy G2Elab MPW Service Center for ICs, Photonics & MEMS Prototyping & Low Volume Production 46, Avenue Félix Viallet Grenoble Cedex, France cmp@imag.fr

2 Table of contents Table of contents Editorial... 2 Generalities... 3 Operations performed for all projects... 4 Selection of processes... 4 Distribution and support of the design kits and design rules... 4 Application of the procedure flow chart... 4 Overview of the activities in Cooperation with other services... 5 Cooperative agreements... 5 Collaboration CMC CMP MOSIS... 5 CMP Distributors... 6 Integrated circuits manufacturing... 7 Main data in Analysis of the participation... 7 Design Kits, Libraries & support Design kits management and main data IC Libraries ams supported CAD tools STMicroelectronics supported CAD tools MEMS design kits Design kits support Annual meeting Annual users meeting Focus CMP Project on Die level bumping & assembly on substrate Flip Chip assembly on plastic substrates Flip Chip assembly on ceramic substrates Photonics Tutorial nm FD SOI RTL to GDS design flow Closer to CMP user communities: CMP increases its representation in international conferences and exhibitions Technology Overview Integrated circuits ams STMicroelectronics Photonic MPW Prototyping Micro Electro Mechanical Systems (MEMS) Prototyping ams MEMSCAP Micralyne Teledyne DALSA Standard Packaging Wire bond packaging process flow for MPW runs MEMS Packaging Wafer and die thinning Flip Chip Packaging ams wafer level bumping option Advanced packaging OPEN 3D Post Process Passive Silicon Interposer MPW run schedule Circuit Gallery Examples of IC's manufactured through CMP from end 2015 & to Contact information Staff members and their current responsabilities

3 Pg. 02 Editorial Editorial Dear CMP users, the 2016 edition of our annual report is in your hands to illustrate our past activities and introduce our coming year services. Similarly to last year, you will find in our report a general overview of CMP 2016 activity. You will also read more about several projects initiated and carried out by CMP team to develop new or complementary services and to improve the existing ones. The last parts of the report are dedicated to latest up to date CMP services coming with the gallery of circuits gathered from CMP users filling to communicate on their projects through our communication displays. In the activity report section, you will see that this year, about 25% of prototypes were produced on advanced SOI technologies, confirming the interest of the community for our 28nm FDSOI technology. Meanwhile, it is important to mention that this percentage could have been even higher if we did not face turnaround cycle time difficulties, specifically on that technology node. This is for me the opportunity to present, once more our sincere apologies from CMP as well as our partners, with respect to the delays in delivering prototypes in this technology. In the meantime, our services on ams technologies were delighted to manage significant amounts of projects, back to the great years , in terms of prototyping but also low volume productions for R&D purposes. Meanwhile, this year, we encountered a slight reduction in volume activity, mainly due to MPW cancellation or significant delays. Several new offers made available during 2016, and continued in 2017, are presented in the report. Especially, we are very happy to collaborate with CEA LETI and IRT Nanoelec toward a full service on silicon photonics compatible with most EDA tools and specialized photonics design tools, including packaging services with recognized subcontractors. Also, during this year, several specialized processes have been added to our service portfolio in partnership with ams. Cost effective and interesting optical or packaging oriented options and post processes are now open through CMP on ams processes thanks to a long term and very proactive relationship between ams and CMP. And more is coming in I also want to point out, in this CMP annual report Edito, the opportunity taken by CMP to ramp up its advanced packaging services, with more internal development and qualification efforts, toward cost attractive and technically accessible and reliable offers. CMP is gaining in technical expertise to support at best your requests and help you in your search for solutions. CMP also increased its representation activities with reinforced presence on conferences and exhibitions. With all these internal developments, we are targeting a higher satisfaction from our user community, which is the complementary need to our great technology offers was also the opportunity for CMP to open up its news web site, for a refreshed presentation of our activities and services, with a nicer, more reliable interface, compatible with almost any display. As it was the case in the previous web site, you can find a lot of technical information/data on our technologies portfolio, you have access to all necessary web pages to place a request or an order. The main effort has been placed on the web site architecture and the accessibility of the information you are looking for. Take a look to the project gallery and find out how we are promoting your work, publications and activities through our web site. Take this opportunity to outline and promote your design and research activities Circuits Multi Projets (CMP) Multi Project Circuits In conclusion, I hope you will enjoy reading this CMP annual report and that you will find interesting data for your activities. For 2017, let me wish that our relationship will bring us mutual satisfaction, and great projects and developments through CMP services. From layout to chips Jean Christophe CRÉBIER Director T.: Jean Christophe Crébier

4 Pg. 03 Generalities Generalities A large number of complex technological operations are required for integrated circuit fabrication, but circuits are cheap, due to the fact that most of those operations are repetitive and carried out for a very large amount of components. Each processed wafer of silicon is cut into hundreds of dices. For some of the slowest and costliest operations, boats of hundreds of wafers are processed together. That means that tens of thousands of circuits are fabricated simultaneously. By this high number, mass production industry cannot tolerate relatively low yields. For non collective operations, such as prototyping test and packaging, operations are highly automated, using mass production techniques. These very expensive techniques seem out of reach for research and educational centers for integrated circuit design. However the design of a circuit by researchers or students must be pursued to its conclusions, which means fabrication, but a research or education prototyping will only require a few chips and mass production is not necessary. In a similar manner, start up and companies low volume production needs are also looking for enablement facilities. The basic idea of a multi project chip is to collectively process circuits that are different and dissimilar. High fabrication costs can then be shared. To do so, a great number of elementary circuits are put side by side, to be reproduced on the wafer. The fabrication yield must be excellent at least constant since circuits cannot be tested before being send back to the designers. This good yield is obtained through industrial production processes. Using such industrial processes, CMP could open the service to industry as early as 1990, for prototyping as well as for low volume production. Low volume production is aimed at helping Small and Medium size Enterprises (SMEs) to get relatively small numbers of circuits (say a few hundred or a few thousand), that they would not obtain directly from manufacturers. A MPW service center like CMP is then interfacing the IC manufacturers and the SMEs to make possible the access to advanced technologies, even the most expensive ones. Finally two essential criteria driving CMP MPW offers must to be underlined: circuits are mostly manufactured through industrial lines and very mature and advanced processes. Some very original offers or services are offered through recognized technological institutions with the objective to make them available to the community at the earliest stage. Courtesy G2Elab, Grenoble, France From Layout to Chips Examples of fabricated circuits in 2016 are reported in the gallery pages of this report.

5 Pg. 04 Generalities Operations performed for all projects Selection of processes Processes made available have to be selected by anticipating the needs and wishes of Research and Industry communities. Furthermore, maintaining a portfolio of advanced technologies requires a continual adaptation. New advanced and/or niche/specialized technologies are regularly introduced every year. Meanwhile, mature and cost attractive technologies are also of interest for R&D purposes. After the selection of a new process all the procedures, interfaces and acces conditions have to be examined, in particular: - Which design rules could be used, and distributed, - Which standard cells are available, for what CAD tools; in some cases CMP will adapt a cell library to an existing CAD tool, - Which electrical measurements (PCM) will be done by the manufacturer and available to the users, - How circuits could be merged, scribed and packaged, - which regulations apply for this technology to send off the circuits. Finally a contract is signed between CMP and the manufacturer. Distribution and support of the design kits and design rules Most of the design kits are delivered by CMP free of charge with the requirement that the designed circuits are to be fabricated through CMP runs. To receive a design kit, the user fills in the appropriate form on the website. After acceptance, he signs the specific confidentiality agreements according to his request, and receives the design kit (normally within one or two months, depending on delays for export regulations). Transmission is done through Internet as much as possible. CMP contact: Sylvaine EYRAUD Design Kit and MPW User Relationship T.: Sylvaine.Eyraud@imag.fr Application of the procedure flow chart CMP complies with Procedure Flow Charts defined with foundry partners, and specifically, it shall ensure, before sending any Design Kit to a Customer, that: - a valid Design Kit Licence Agreement (DKLA) is in place between Manufacturers and CMP for the appropriate Customer, and the appropriate Technology; - a valid Confidentiality and License Agreement (CLA) is in place between the Customer and CMP for the appropriate Technology; - the audit passed regarding the VLAN security at the Customer side; - the obtention of Export License from the appropriate administration when applicable. CMP handles various version and types of design kits, corresponding to the different technologies for different CAD tools. Almost all of them are free of charge. The full procedure takes at least 3 weeks and up to 2 months. For more information on the procedure to be granted access to a confidential design kit, please consult our web site:

6 Pg. 05 Generalities Overview of the activities in 2016 A total of 202 projects were fabricated for 83 Institutions, Research Laboratories and Companies from 25 countries. The table below presents the turnaround times experienced through CMP on the most active technologies, based on data issued from 2015 and 2016 MPW. These turnaround times consider the time period required after the MPW service closing date for the data preparation between CMP and the customers and then between CMP and the manufacturer of the integrated circuits. It also includes the time for dicing and delivery worldwide of each project, without taking into account the packaging services and special requests for export licenses. For regular ceramic plus wire bonding packaging services, please add another 2 to 3 weeks lead time depending on package type and IC pads pitch. ams STMicroelectronics 0.35 µm CMOS weeks 180nm BCD8SP weeks 0.35 µm HV CMOS weeks 130nm CMOS weeks 0.35 µm SiGe BiCMOS weeks 65nm CMOS weeks 0.18 µm CMOS weeks 55nm BiCMOS weeks 28nm FDSOI weeks Including 1 to 2 weeks for data preparation and 1 to 2 weeks for wafer dicing, and prototype delivery Including 2 to 3 weeks for data preparation and 2 to 3 weeks for wafer dicing, and prototype delivery Hereafter are the technologies that were operated through CMP in 2016: ams STMicroelectronics 0.18 µm CMOS CA18A6 28 nm CMOS028 FDSOI 0.18 µm CMOS High Voltage H18A6 55 nm BiCMOS µm CMOS C35B4C3 65 nm CMOS065 CMOS 7LM 0.35 µm CMOS Opto C35B4O1 130 nm HCMOS9GP CMOS 6LM 0.35 µm CMOS RF C35B4M3 130 nm H9SOI FEM 0.35 µm SiGe BiCMOS S35D4M5 130 nm BiCMOS9MW SiGe BiCMOS 6LM 0.35 µm CMOS High Voltage H35B4D3 130 nm HCMOS9A High Voltage Cooperation with other services Cooperative agreements CMP has signed cooperative agreement with the following Organizations over the time: - CMC Canada - MOSIS USA - VDEC Japan - CIC Taiwan - IDEC Korea CMP contact: Isabelle AMIELH Chief Administrative Officer T.: Isabelle.Amielh@imag.fr Collaboration CMC CMP MOSIS Among these cooperations with other MPW services, three of the main ICs prototyping and low volume production services from USA (MOSIS), Canada (CMC) and France (CMP) started a partnership in order to exchange some of their services and to enlarge the portfolio of technologies proposed by each partner. In this way technologies from ams and STMicroelectronics were offered by CMP to MOSIS and CMC customers, technologies from IBM and TEZZARON were offered by MOSIS to CMP customers. Most of these cooperation services are stil ongoing and more recently TELEDYNE DALSA, and Micralyne were offered by CMC to CMP customers. Such partnerships are necessary to support escalating costs of very deep sub micron processes or the low demand of specialized processes.

7 Pg. 06 Generalities CMP Distributors - SiliConsortium Ltd. Japan - Sevya Multimedia Technologies India Examples of cooperation numbers between CMP and Universities around the world, over the last years Courtesy of University of Toronto, Ontario, Canada More information on this circuit in the gallery pages & CMP web site. CMP Contact: cmp@imag.fr T.:

8 Pg. 07 Integrated circuits manufacturing Integrated circuits manufacturing Main data in 2016 Main data concerning the circuits fabricated in 2016 are the following: circuits for Research (135), Education (15) and Industry (52) - 15 technologies in CMOS, BiCMOS, SiGe BiCMOS, SOI, CMOS High Voltage, CMOS RF and MEMS - 83 participating Institutions from 25 countries - 52 circuits fabricated for industrial purposes for 13 industrial companies or national research laboratories - 42 low volume projects for 21 Institutions from thirty pieces to thousands of pieces or few wafers. The circuits list and the list of Institutions participants (Appendix 1) are available on the Website. Analysis of the participation Distribution of circuits per technology and evolution In 2016, the part of CMOS (bulk or on SOI including High Voltage) IC projects is 80.7% of the total. Distribution of circuits per technology in 2016 The number of HV CMOS projects increased in 2016, showing the interest of the community for such technologies for power electronics and RF / analog / power amplification applications. Meawhile, SiGe technologies remain attractive for RF applications despite the introduction of very attractive CMOS / BiCMOS technologies optimized for RF. SOI technologies continue to represent a significant activity in volume, all related to the 28nm FDSOI and the 130nm H9SOI FEM. The prototype fabrications share in SOI technologies increased significaltly, from about 25% in 2015 to 30% in CMP contact: Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr

9 Pg. 08 Integrated circuits manufacturing Evolution of circuits per technology from 2013 to 2016 Distribution of circuits per foundry Distribution of circuits per foundry in 2016 Distribution of circuits per country and geographical area and per utilization Distribution of circuits per country from 2014 to 2016 In 2016, CMP faced a decrease in the number of circuits submitted in regular runs. In the other side, CMP received a large number of requests to re manufacture circuits which were already fabricated through CMP. CMP contact: Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Courtesy of Université catholique de Louvain, ICTEAM Institute, Louvain La Neuve, Belgium More information on this circuit in the gallery pages & CMP web site.

10 Pg. 09 Integrated circuits manufacturing Distribution of circuits per geographical area and evolution from 2012 to 2016 Some data In 2016 and with respect to 2015 and 2014 the amount of projects handled by CMP in France is slightly growing up to reach more than 1/3 of the total number of projects. Projects made through CMP in North America decreased again in 2016 like it has been the case in With a level of 40 projects per year in North America, this year is in the average level of activity for this region of the world. Similar comments can be formulated for the European and Asian regions. All in all, the main explanation comes with the fact that a significant amount of projects initially programmed in 2014 were finally delivered in 2015, making that year above average. Finally, 2016 is more or less a regular year, prolonging a sligth but real volume activity reduction. This tendency, which has started after the great period, bringing the CMP activity back to the level of the previous periods from 2001 to Distribution of circuits per utilization from 1996 to 2016

11 Pg. 10 Integrated circuits manufacturing The share of circuits distributed by CMP among Education, Industry and Research stabilizes after the great 2007/2009 years. Circuits for academic research In 2016, circuits for academic research represent 135 circuits (67%) coming from 22 countries. Circuits for industrial purpose 52 industrial purpose circuits, 41 from France and 11 from foreign countries, were fabricated for 13 industrial companies (see the list in Appendix 2 on the CMP website). This level of industrial participation represents 26% of the total number of circuits. Among industrial projects: 29 low volume productions circuits for 12 Institutions, from thirty pieces to thousands of pieces or wafers have been fabricated. See in Appendix 3 the list of low volume circuits on the CMP website. New Institutions 14 Institutions (out of 83 all in all) participated for the first time. All the Institutions having submitted circuits from 1981 are listed in Appendix 4, appendices are available on the CMP website Courtesy of TIMA, Grenoble, France More information on this circuit in the gallery pages & CMP web site. CMP Contact: cmp@imag.fr T.:

12 Pg. 11 Design Kits, Libraries & support Design kits management and main data Design Kits, Libraries & support CMP distributes the design rules for each technology and the standard cell libraries for each specific software tool (design kits). CMP handles 35 different design kits (corresponding to different technologies and different CAD tools), which are sent to customers upon signature of a Confidentiality and License Agreement. Design kits are sent free of charge. Over 1,100 customers, (academic centres and industrial companies) from 70 countries have already signed agreements and received design kits. In 2016, a total of 394 design kits were distributed, according to the geographical distribution below. These data can be compared to previous years. Design kit distribution over Figures below show the distribution of design kits per foundry and geographical areas over CMP contact: Number of new institutions which received ams Design Kits Sylvaine EYRAUD Design Kit and MPW User Relationship T.: Sylvaine.Eyraud@imag.fr

13 Pg. 12 Design Kits, Libraries & support Number of new Institutions which received STMicroelectronics Design Kits Globally the number of new Institutions which received design kits are: - 13 new Institutions for ams with a total of 479 Institutions - 23 new Institutions for STMicroelectronics with a total of 659 Institutions Worldwide Design Kit distribution in 2016: CMP contact: Sylvaine EYRAUD Design Kit and MPW User Relationship T.: Sylvaine.Eyraud@imag.fr CMP users mainly come from Europe (59%), North America (24%) and Asia (14%). Others customers come from India, South America and Austria.

14 Pg. 13 Design Kits, Libraries & support IC Libraries ams supported CAD tools Cadence Mentor Graphics Synopsys Schematic & Desing Entry Composer Electrical Simulation Spectre Hspice Ultrasim Eldo Design Compiler Tanner S Edit TSpice ADS Keysight Technologies Digital Simulation NC Sim ams Designer ModelSim QuestaSim Logic Synthesis RTL Compiler Layout & Verification Virtuoso Assura QRC Calibre P&R Hspice Design Compiler Tspice L Edit SPR DRC Encounter Digital Implementation (EDI) STMicroelectronics supported CAD tools IC Electrical Simulation Verification Parasitic extraction P&R CDB OA Spectre (CDS) Eldo (MGC) Hspice (SNPS) ADS (Keysight) Goldengate (Keysight) Calibre (MGC) PVS (CDS) StarRCXT (SNPS) Calibre (MGC) QRC (CDS) Encounter (CDS) ICC (SNPS) HCMOS9GP x x x x x x x x BiCMOS9 MW x x x x x x x x x x x x x HCMOS9A x x x x x x x x x x H9SOI FEM x x x x x x x x x CMOS065 x x x x x x x x x x x x BiCMOS55 x x x x x x x x x x CMOS028 FDSOI x x x x x x x x x x x x MEMS design kits CMP contact: Manufacturer Technology Design kit Software Version Fields of application ams Bulk Micromachining HIT Cadence Cadence IC Physical layout and Kit_ams_ /6.1.5 DRC Tanner L Edit Physical layout and DRC Teledyne Dalsa MIDIS MK1551 Coventor Catapult Physical layout, design (Designer) from entry and multiphysics CoventorWareTM analysis Cadence Virtuoso Layout Physical layout and Suite ver.ic6.1.5 DRC from Cadence ANSYS Multi physics analysis Memscap MUMPs Tanner L Edit Physical layout and DRC SoftMEMS MEMS Pro v7.0 Physical layout and DRC, multi physics analysis Cadence Cadence IC Physical layout and /6.1.5 DRC Christelle RABACHE MPW Runs and Design Kits support T.: Christelle.Rabache@imag. fr

15 Pg. 14 Design Kits, Libraries & support Design kits support CMP provides technical support on the design kits. Several support levels are addressed (e.g. installation issues, use of the technology files or libraries, design flow, etc.) To request support, users can create tickets through CMP Support Center. This interface between CMP and design kits users, dedicated to technical support, is available on CMP web site: More information is available on the corresponding flyer. This interface has been developped and implemented to improve the quality of the design kit technical support services. Today more thant 90% of the DK support services are carried out through this web interface. The interface has the following features: - Intuitive 2 tabs : open a new cket and ckets summary (you can check the tickets details when selecting one subject) - Easy and fast fill in the form, describe the issue and add screen snapshots, testcases, log files - Effective track the ckets and see all the elements about each issue on the same cket thread - Flexible open as many ckets as encountered issues and if needed the ckets can be reopen. The procedure to connect to CMP Support Center is described below: Ask for an account at cmp support@imag.fr with the subject Access request to CMP DK Support Center. CMP will create for you a personal support account, connect you to CMP DK Support Center using the link you received by after your account creation. Notifications by follow all the steps, the picture below illustrate the first page of the Support Center. CMP contact: Christelle RABACHE MPW Runs and Design Kits support T.: cmp support@imag.fr CMP will first try to find the answer and solution when already known. If not, CMP try to reproduce the issue, try to investigate and solve it. If no solution exists at CMP, then the problem is reported to the provider who will help to provide the solution. Tutorials, documentation and user s guides exist inside the design kits and design platforms. Some are coming from providers and others are made by CMP. These materials are useful for starting using the design kits, showing the different design flow steps and correct use of tech files and libraries.

16 Pg. 15 Annual meeting Annual meeting Annual users meeting The 2016 users' meeting, open to every person from academia or industry, using or interested in the CMP services, took place on February 4th in a new place in Paris: Institut de Physique du Globe de Paris (IPGP). The meeting was focused on the presentations of CMP MPW and packaging services together with the participation of our partners, especially with the following presentations: - B55 Technology Overview, Pascal CHEVALIER, STMicroelectronics - New platform for Photonic integrated circuit of CEA LETI MPW activity, Maryse FOURNIER, CEA LETI - Advanced packaging services, CPA STMicroelectronics 84 people attended the meeting coming from 54 Institutions: Academia: 56 (53 French, 3 Foreign), Industry: 28 (25 French, 3 Foreign). The list of participant is available in Appendix 5 on CMP website. User s meeting 2016 In 2017, the annual users meeting will take place on January 26th, at Institut de Physique du Globe de Paris (IPGP). In addition with a complete review of up to date CMP MPW and packaging services, The following topics will be discussed : - OxRAM memories: a disruptive technology for disruptive designs, Luca Perniola, CEA LETI - Hot topics at ams in 2017, Andreas Wild, ams - Photonic IC design using PhoeniX Software solutions, Luis Jorge, PhoeniX Software. Isabelle AMIELH Chief Administrative Officer T.: Isabelle.Amielh@imag.fr Chantal BÉNIS MOREL Communication /Conference Management T.: Chantal.Benis@imag.fr

17 Pg. 16 Focus Focus CMP Project on Die level bumping & assembly on substrate To answer new packaging request from its community, CMP is developping post processing services at wafer and die levels. Die level post processing gives us the opportunity to mitigate cost and confidentiality issues compared to wafer level post processing, especially when high confidentiality constraints are applied on some projects embedded at wafer scale. On the other side, this non collective service requires specific developments in order to qualify the offer. In some cases, CMP only receive bare die from MPW runs, therefore post processing is only accessible at die level. CMP has initiated a project for the evaluation of new die level flip chip packaging service at low cost access. The objective of this project, which is still undergoing, was to verify and evaluate the feasibility and the reliability of each design and process step of the Flip Chip assemblies at die level before to officially launch this service which would include: - Die level solder ball/stud bumps deposition on predefined pad ring - Predefined ceramic BGA/Plastic LGA Substrate supply - Flip Chip assembly process on predefined substrate - Access to pad landing layout for PCB integration In order to offer this service with an attractive cost, CMP would take in charge the non recurring engineering costs, leaving only the machine setup and process recurring fees to its customers as this is illustrated on the picture below. Substrates and process flow would be qualified and supplied as well. To do so, a few properties of the submitted circuits would be imposed: die size, padring layout & die thickness. Flip Chip project cost sharing Padring example Upon reservation, the designer will receive a GDS file containing the packaging IP including the scribe cell and a compatible padring corresponding to the selected technology: - The circuit must be designed within this layout to be compatible with the flip chip package - Those IP packages will be made available on any ams and STMicroelectronics MPW Two types of substrates are considered, plastic LGA and ceramic BGA. Each type is associated with a different assembly method, which are described below. Olivier GUILLER R&D Engineer 3D IC MPW Runs T.: olivier.guiller@imag.fr Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: lyubomir.kerachev@imag. fr Flip Chip assembly on plastic substrates After dicing, the dies undergo an Under Bump Metallization (UBM) deposition consisting of a Ni/Au stack, followed by solder balls deposition. The bumped dies will then be assembled on a plastic substrate (supplied by CMP) by mass reflow. An under fill is applied to the assembly followed by a molding. The assembly will be carried out by a qualified subcontractor.

18 Pg. 17 Focus Considered LGA packages: - LGA 56 I/Os optimized for ST designs; - LGA 84 I/Os optimized for ams designs. Flip Chip assembly on ceramic substrates After dicing, gold stud bumps are deposited on the pads. The bumped dies are then assembled on a ceramic substrate (supplied by CMP) by thermo compression with non conductive paste. The assembled package is then molded and solder balls are deposited on the BGA backside. All those steps will be carried out by a qualified subcontractor. Considered BGA packages: BGA 52 I/Os, BGA 68 I/Os, BGA 84 I/Os, BGA 100 I/Os & BGA 224I/Os Ongoing preliminary evaluation CMP is currently evaluating die level Flip Chip assembly process steps on plastic LGA packages for both ams and STMicroelectronics technologies. Two test dies with 56 and 84 staggered IO pads on two rows per side have been designed and fabricated. Some test dies have been packaged in wirebonding and are fully functional regarding their specifications. They are currently under investigation for a die level UBM and bumping processes. Evaluation of the Flip Chip assembly on ceramic BGA packages is planned for CMP users will be informed about the availability of the die level Flip Chip services. Courtesy of LETI Olivier GUILLER R&D Engineer 3D IC MPW Runs T.: olivier.guiller@imag.fr Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: lyubomir.kerachev@imag.fr Flip Chip test die in ST's 65nm CMOS Flip Chip test die in ams s.35µ CMOS

19 Pg. 18 Focus Photonics Photonics is a technology dedicated to the signal detection, generation, processing and data transfer. The signal is carried out by the light (photons) allowing high traffic capacity. High speed optical links are well known as optical fibers usually used in the Telecom, Datacom and the Computercom for data transfer at long and medium distances. Nowadays targeted applications are the board to board and the chip to chip communications since it is a high volume market. Among the main interests in using optical devices at shorter distances are the voltage isolation, the perturbation immunity of the signal, the high speed, precise and lossless data transfer. Building Photonic Integrated Circuits (PIC) allows merging the photonics and the electronics, and moving the optical communication to the chip. The reduction of the cost and the consumption as well as the integration of more functions in the optical devices are the main R&D challenges. Figure 1: Optical interconnects The silicon photonic devices are produced within standard silicon factory with standard silicon processing which makes the photonics technology compatible with the CMOS technology. Photonics Process Design Kits (PDK) containing component models, layout and Design Rules Manual (DRM) are already existing. These allow simulations of the complete circuit, design rules checking and tape out preparation in the same way as it is done in microelectronics. Therefore, the PDKs are built compatible with the designer s well known software tools such as Cadence, Mentor Graphics, PhoeniX Software, etc. Courtesy of CEA CMP contact: Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: lyubomir.kerachev@imag.fr Figure 2: Photonic PDK

20 Pg. 19 Focus Furthermore photonics technology can overcome the limits of Moore s law evolution that the microelectronics is currently reaching. To go to More than Moore direction, a particular care is taken regarding the 3D integration allowing photonic and electronic convergence. Packaging and integration processes are developed for the Silicon Photonic Integrated Circuits making possible the realization of fiber coupling and CMOS to Photonic die stacking. Figure 3: Co Design of Photonic IC and Packaging Image Courtesy of Tyndall Institute Photonic MPW prototyping is now available through CMP! In July 2016 IRT Nanoelec headed by CEA Leti and CMP announced the IC industry s first multi project wafer (MPW) process for fabricating silicon photonics devices on a 310nm silicon on insulator (SOI) platform. The MPW service also includes compatible IC MPW services and the first service for post process 3D integration on multi project wafers. Lateral GePIN diode courtesy of Cea Leti Lateral GePIN diode courtesy of Cea Leti Courtesy of Tyndall CMP contact: Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: lyubomir.kerachev@imag.fr

21 Pg. 20 Focus Tutorial 28nm FD SOI RTL to GDS design flow In the frame of the technical support, CMP started in 2015 the development of a complete tutorial to introduce the design methodology of a digital circuit in 28nm FDSOI technology. Thanks to a walkthrough user guide, the first version was detailing all the basic steps, from the RTL netlist to the GDS layout, of a standard digital flow. On summer 2016, a second version was delivered to all CMOS28FDSOI users: it now integrates several additional functionalities and supports last releases of the digital design tools. Schematic RTL netlist Simulation waveforms GDS layout This tutorial illustrates, as an example, the design of a synchronous and sequential realistic circuit. The digital implementation flow for this 28nm FDSOI technology is based on different CAD vendors tools: Cadence, Mentor Graphics and Synopsys. One can perform synthesis, place and route, simulations and finally launch DRC and LVS verifications. The whole tutorial was upgraded to be compatible with the PDK 2.5.f and the new Foundation TechnoKits from STMicroelectronics. The synthesis part was updated for Cadence Genus tool replacing RTL Compiler while the place and route script was fully reviewed for Cadence Innovus, which is the next generation of Encounter Digital Implementation tool. For this second version of the tutorial, several design aspects have been studied in order to improve the circuit example. The most important update concerns the body biasing methodology (lets speed or leakage optimizations in the circuit) that is now automated. To feed body biasing voltages in core cells, 2 supply pads are added, 2 additional power rings are created and specific filler cells are regularly implemented in the core. So that 4 different voltages are supplied in the design: 2 for usual VDD / GND and 2 for body biasing voltages (VDDS / GNDS). CMP contact: Christelle RABACHE MPW Runs and Design Kits support T.: Christelle.Rabache@imag. fr

22 Pg. 21 Focus VDDS GNDS Body bias voltages feeding core cells through fillers rows The IO ring was also redesigned in order to meet some technology recommendations: increase the number of supply pair VDDE/GNDE, addition of FILLCELL_REFASRC cell and connection of ASRC signals to fixed logic. As all scripts and testbenches are provided with the tutorial, designers can follow the suggested design flow and easily adapt it to their own project. A third tutorial version should be developed in 2017 to help the users in the migration from 10ML to 8 metal layers stack. It will probably also include details on LVS and DRC verifications. CMP contact: Christelle RABACHE MPW Runs and Design Kits support T.: Christelle.Rabache@imag. fr

23 Pg. 22 Focus Closer to CMP user communities: CMP increases its representation in international conferences and exhibitions Exhibiting puts CMP face to face with its community, in an interactive setting and provides a great opportunity to showcase new and existing products. - Some key benefits CMP intends to have with this active representation: - Promote the visibility of its services - Present innovations, promote service - Develop new marketing networks and enlarge the existing ones - Get and overview of trends and the competition - Face to face meeting with previous or new users This is why CMP exhibits in major conferences in Europe and US for more than 20 years. In 2016 CMP has presented its activities and services during the following events: - DESIGNCON, January 2016, Santa Clara USA - DATE, March 2016, Dresden Germany - JRE, 19 May 2016, Gif sur Yvette, France - DAC, June 2016, Austin USA - ESTC, September 2016, Grenoble France - ECOC, September 2016, Düsseldorf Germany - SEMICON Europa, October 2016, Grenoble France With the introduction of new areas in its activity (advanced packaging, Photonics, Smart Power), to broaden its visibility and meet potential new users, CMP targets other important events, in complementary areas such as: CMP contact: Isabelle AMIELH Chief Administrative Officer T.: Isabelle.Amielh@imag.fr - European Conference on Optical Communication (ECOC): Conference on optical communication - Electronics System Integration Technology (ESTC): European event in the field of microelectronics packaging and integration. - Electronic Components and Technology Conference (ECTC): Premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange - Power Conversion and Intelligent Motion (PCIM Europe): International leading exhibition for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management.

24 Pg. 23 Focus In consequence, CMP will exhibit or support the following conferences in 2017: - DESIGNCON (booth 406), 1 2 February, Santa Clara USA - DATE, March, Lausanne Switzerland - PCIM (booth 348), May, Nuremberg Germany - DTIP 29 May, 1st June, Bordeaux France (support) - ECTC (booth 517), 30 May 02 June, Lake Buena Vista USA - DAC (booth 320), June, Austin USA - ECOC (booth 199), September, Gothenburg Sweden - European MEMS Summit, September, Grenoble France - Expected exhibition in ASIA in the coming years. CMP wishes to reach and meet its user communities all around the world. Have a look at the upcoming shows if you re around, take out a little time and come visit us! CMP contact: Isabelle AMIELH Chief Administrative Officer T.: Isabelle.Amielh@imag.fr

25 Pg. 24 Technology Overview Integrated circuits Technology Overview ams CMP offers ams technologies since Based in Austria, ams is an analog IC company that develops and manufactures high performance semiconductors. ams products are aimed at applications which require extreme precision, accuracy, dynamic range, sensitivity, and ultra low power consumption. ams product range includes sensors, sensor interfaces, power management ICs and wireless ICs for customers in the consumer, industrial, medical, mobile communications and automotive markets µm CMOS 6LM and 0.18 µm High Voltage CMOS 6LM C18 process is the base technology for ams advanced 0.18µm process family. The Mixed Signal CMOS process C18 offers highest integration density up to 118kGates/mm² at up to 7 levels of metal, supply voltages from 1,8V to 5.0V and ESD protection cells with up to 8kV HBM level. H18 process provides leading edge 0.18μm High Voltage technology based on a proprietary scalable HV device architecture. Jointly developed with IBM, the 0.18µm High Voltage CMOS process is the 6th generation of continuously improved High Voltage CMOS technologies developed by ams. The H18 process currently provides HV operation with 20V and 50V devices, whereas an extension to 120V is in development. H18 process is manufactured in a state of the art 200mm fabrication process ensuring very low defect densities and high yields. With only 2 to 3 mask level adders to the CMOS base process H18 is perfectly suited to reduce cycle time and improve overall bill of materials. H18 also provides high levels of digital integration (118 Kgates/mm²) equivalent to standard low voltage CMOS. Courtesy of Federal University of Rio de Janeiro, Brazil Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr TECHNOLOGY: H18A6 IC 0.18µm H18A6 Process characteristics Met. layer(s): 6 metal layers / Thick Metal6. Capacitors: Single MiM / Dual MiM / High density. MiM Maximum die size: 2cm x 2cm. Standard cells: digital standard cells and IO pads analog standard cells and IO pads. Available I/O: I/O cell library with available for 1.8V/5V. High Voltage IO pads for 20V or 50V. Temp. range: 40 C. / +180 C. Supply voltage: 1.8V, 5.0V, 20V, 50V (max gate voltage 20V). HV Digital standard cells and IO. Libraries: CORELIB_HV: CORELIB for high voltage. IOLIB_HV : High Voltage digital IO pads library. Design kits 4.11, 3.78 DK font end/back end tools Cadence IC Cadence IC DK simulation tools Spectre, Hspice, Ultrasim, NC Sim, ams Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys) Price 1200 /mm2 if Area less or equal to 10mm [(Area 10) x 1100 ] if Area > 10mm2 (X+0.12)*(Y+0.12)mm2. Minimum charge is the price of 5.55 mm2 Fabrication schedule 1 13 Feb., 15 May, 14 Aug. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 1 to 2 weeks for data preparation and 1to 2 weeks for wafer dicing, and prototype delivery Examples of fabricated circuits in 2016 are reported in the gallery pages of this report. Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr 1 subject to modification, check on web site

26 Pg. 25 Technology Overview Vds Vgs 1.8V (3.5nm) 5.0V (12nm) 20V (52nm) LV fets LV fets in HV well HV asymmetric fets in HV symmetric fets HV wells (nfet in Substrate) 1.8V 5.0V 1.8V 5.0V 20V** 50V 20V 50V nfet* pfet* nfethvt pfethvt nfetm pfetm nfet* pfet* nfethvt pfethvt nfetim pfetim nfeti20t pfet20t nfet20mh nfeti25m pfet25m nfeti20h pfet20h Nfeti50t Pfet50t nfeti50m pfet50m nfeti50h pfet50h nfet20hs pfet20hs nfet50hs pfet50hs * RF layout available **25V Vds for nfeti25m, pfeti25m Benefits: High performance HV CMOS matching BCD performance and Several voltage regimes on one chip enables optimized area µm CMOS DLP/4LM 3.3V/5V This process is used for digital, analog and mixed applications but also for hight frequency applications. 0.35µm CMOS technology offers four metal layers, digital standard cells and bulk micromachining. The bulk micromachining post process allows MEMS integrated togehter with electronic components. TECHNOLOGY: C35B4C3 IC 0.35µm C35B4C3 Process characteristics Met. layer(s): 4 Poly layer(s): 2, high resistive poly. Maximum die size: 2cm x 2cm. DLP Usable cells: about 300 digital cells. Available I/O: I/O cell library with digital pads is available 3.3V, 3V/5V, 5V with internal level shifters. Temp. range: 40 C. / +125 C. Supply voltage: 5V or 3.3V Design kits 4.10,3.80 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre, Hspice, Ultrasim, NC Sim, ams Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys) Price 650 /mm2 if Area less or equal to 10mm [(Ar ea 10) x 550 ] if Area > 10mm2 (X+0.12)*(Y+0.12)mm2 Minimum charge is the price of 3.43 mm2 Fabrication schedule 2 30 Jan., 18 Apr., 01 Aug., 25 Sept., 13 Nov. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 1 to 2 weeks for data preparation and 1 to 2 weeks for wafer dicing, and prototype delivery Courtesy of CEA Irfu, Gif Sur Yvette, France Examples of fabricated circuits in 2016 are reported in the gallery pages of this report. Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr 2 subject to modification, check on web site

27 Pg. 26 Technology Overview 0.35µm C35B4M3 CMOS DLP/4LM ThickM4 & MIM Based on the 0.35 CMOS standard process. There is a planarization and anti reflective coating that allows better optical features. This process comes with P Epi wafers for lowering current leakage in the diode (lower dark current). Applications: Photo sensors, APS, CMOS Camera TECHNOLOGY: C35B4M3 IC 0.35µm RF C35B4M3 Process characteristics Poly layer(s): 2, high resistive poly. Maximum die size: 2cm x 2cm. Usable cells: about 300 digital cells. Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters. Temp. range: 40 C. / +125 C. Supply voltage: 5V or 3.3V. Design kits 4.10, 3.80 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre, Hspice, Ultrasim, NC Sim, ams Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys) Price 950 /mm2 if Area less or equal to 10mm [(Area 10) x 850 ] if Area > 10mm2 (X+0.12)*(Y+0.12)mm2 Minimum charge is the price of 4.49 mm2 Fabrication schedule 3 27 Feb., 06 Jun., 11 Sept., 11 Dec. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 1 to 2 weeks for data preparation and 1 to 2 weeks for wafer dicing, and prototype delivery Thick Metal and MIM available in C35B4M3 CMOS RF Process cross section A35C15_3 QNL2_CMOS Courtesy of The University of Sydney More information on this circuit in the gallery pages of CMP web site µm Opto Based on the CMOS process C35B4C3, the process offers additional options of epitaxial wafers and anti relective layer. This is available both for C35B4O1 and C35B4OA. The only difference between them is the use of a deep etching in C35B4OA making more efficient the optical absorbtion. Applications: Photo sensors, APS, CMOS Camera Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr 3 subject to modification, check on web site

28 Pg. 27 Technology Overview TECHNOLOGY: C35B4O1 IC 0.35µm ARC C35B4O1 Process characteristics This 0.35 CMOS Opto process is offered in each 0.35 CMOS run (C35B4C3). This is a ARC (Anti Reflective Coating) option. Anti Reflective Coating (ARC) allows a higher photosensitivity than C35B4C3. P Epi wafers for lowering current leakage in the diode (lower dark current). The C35B4O1 is with 4 layers metal available for prototyping and low volume production. Met. layer(s): 4. Poly layer(s): 2.Maximum die size: 2cm x 2cm. DLP Usable cells: about 300 digital cells. Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters. Temp. range: 40 C. / +125 C. Supply voltage: 5V or 3.3V. Design kits 4.10, 3.80 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre, Hspice, Ultrasim, NC Sim, ams Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys) Price 700 /mm2 if Area less or equal to 10mm [(Area 10) x 600 ] if Area > 10mm2 (X+0.12)*(Y+0.12)mm2 Minimum charge is the price of 3.43 mm2 Fabrication schedule 4 30 Jan., 18 Apr., 01 Aug., 25 Sept., 13 Nov. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 1 to 2 weeks for data preparation and 1 to 2 weeks for wafer dicing, and prototype delivery TECHNOLOGY: C35B4OA IC 0.35µm BARC C35B4OA Process characteristics This 0.35 CMOS Opto option is offered in each 0.35 CMOS run (C35B4C3), this is a BARC (Bottom Anti Reflective Coating) option. Botton Anti Reflective Coating (BARC) allows a higher sensitivity than ARC. P Epi wafers for lowering current leakage in the diode (lower dark current). The C35B4OA is with 4 metal layers available for prototyping and low volume production. Met. layer(s): 4 Poly layer(s): 2 Maximum die size: 2cm x 2cm DLP Usable cells: about 300 digital cells Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters Temp. range: 40 C. / +125 C. Supply voltage: 5V or 3.3V. Design kits 4.10, 3.80 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre, Hspice, Ultrasim, NC Sim, ams Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys) Price 650 /mm2 if Area less or equal to 10mm [(Area 10) x 550 ] if Area > 10mm2 + fixed fee 6900.(X+0.12)*(Y+0.12)mm2 Minimum charge is the price of 3.43 mm2 Fabrication schedule 5 30 Jan., 18 Apr., 01 Aug., 25 Sept., 13 Nov. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 1 to 2 weeks for data preparation and 1 to 2 weeks for wafer dicing, and prototype delivery A35V15_2INL_APIX_TOP Courtesy of Inst. des Nanotechnologies de Lyon, INSA, France More information on this circuit in the gallery pages of CMP web site. Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr CMOS OPTO Process cross section 4 subject to modification, check on web site 5 subject to modification, check on web site Cross section of a photo diode (BARC process option)

29 Pg. 28 Technology Overview 0.35 µm H35B4D3 CMOS DLP/4LM High Voltage This process is optimized for complex mixed signal circuits up to 120V operating conditions. It comes with different MOS devices supporting different voltages, all in same substrate : 3.3V, 5V, 20V, 50V, and 120V. Analog and digital low voltage parts from C35B4C3 can be embedded in this process. TECHNOLOGY: H35B4D3 IC 0.35µm H35B4D3 Process characteristics Met. layer(s): 4 Thick Metal 4 Poly layer(s): 2, high resistive poly Maximum die size: 2cm x 2cm Usable cells: about 300 digital cells Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters Floating digital pads available with 3.3V Temp. range: 40 C. / +125 C Supply voltage: 5V, 3.3V, 20V, 50V, Max operating voltage 120V (max gate voltage 5V, 20V). Design kits 4.10, 3.80 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre, Hspice, Ultrasim, NC Sim, ams Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys) Price 850 /mm2 if Area less or equal to 10mm [(Area 10) x 750 ] if Area > 10mm2 (X+0.12)*(Y+0.12)mm2 Minimum charge is the price of 7.65 mm2 Fabrication schedule 6 13 Feb., 28 Apr., 14 Aug., 30 Oct. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 1 to 2 weeks for data preparation and 1 to 2 weeks for wafer dicing, and prototype delivery Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr Isolate 3.3V/5V NMOS50V PMOS50V 0.35 µm C35B4E3 CMOS DLP/4LM EEPROM / Flash IPs EEPROM or Flash are available on request (see table hereafter). They come with simulation files and abstract view for P&R (layout block replacement done at ams together with a design review). TECHNOLOGY: C35B4E3 IC 0.35µm C35B4E3 Process characteristics Embedded Flash. Met. layer(s): 4 Poly layer(s): 2 Maximum die size: 2cm x 2cm Usable cells: about 300 digital cells Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters Temp. range: 40 C. / +125 C Supply voltage: 5V or 3.3V. Design kits 4.10, 3.80 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre, Hspice, Ultrasim, NC Sim, ams Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys) Price Available upon request with additional fees Fabrication schedule 7 Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 1 to 2 weeks for data preparation and 1 to 2 weeks for wafer dicing, and prototype delivery 6 subject to modification, check on web site 7 subject to modification, check on web site

30 Pg. 29 Technology Overview All Embedded EEPROM / Flash IPs available through CMP service Read Write Process Block Size Organization Endurance Supply Supply H35 64x8 bit EEPROM 1.8 3,6V 1.8 3,6 V 125 C H35 (midox only) 125 C 128x8 bit EEPROM V V H35 1Kx8 bit EEPROM V V 125 C H35, hightemp 150 C 1Kx8 bit EEPROM V V H35, hightemp 150 C 2Kx8 bit EEPROM V V H35 4Kx16 bit EEPROM V V 125 C Data Retention > C > C > C C C > C Size 0.36mm² 0.54mm² 0.73mm² 0.94mm² 1.20mm² 1.55mm² 0.35 µm S35D4M5 SiGe BiCMOS DLP/4LM BiCMOS process is optimized for high frequencies up to several Giga Hertz. The applications cover circuits for mobile communication to high speed networks. These advanced processes offer highspeed bipolar transistors with excellent analog performance, such as high fmax and low noise, complementary MOS transistors, very low parasitic linear capacitors, linear resistors and spiral inductors. TECHNOLOGY: S35D4M5 IC 0.35µm S35D4M5 Process characteristics SiGe BiCMOS 0.35 S35D4M5 from ams Met. layer(s): 4, thick metal MIM capacitor Poly layer(s): 2, high resistive poly Maximum die size: 2cm x 2cm Usable cells: about 300 digital cells Available I/O: I/O cell library with digital pads is available 3V, 3V/5V, 5V with internal level shifters Temp. range: 40 C. / +125 C; Supply voltage: 5V or 3.3V. Design kits 4.10, 3.80 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre, Hspice, Ultrasim, NC Sim, ams Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys) Price 950 /mm2 if Area less or equal to 10mm [(Area 10) x 850 ] if Area > 10mm2 (X+0.12)*(Y+0.12)mm2 Minimum charge is the price of 4.49 mm2 Fabrication schedule 8 27 Feb., 06 Jun., 11 Sept., 11 Dec. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 1 to 2 weeks for data preparation and 1 to 2 weeks for wafer dicing, and prototype delivery Courtesy of APC AstroParticules & Cosmologie, Paris, France Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr SiGe Process cross section Examples of fabricated circuits in 2016 are reported in the gallery pages of this report. 8 subject to modification, check on web site

31 Pg. 30 Technology Overview STMicroelectronics STMicroelectronics is one of the world s largest semiconductor companies. Offering one of the industry s broadest product portfolios, ST serves customers across the spectrum of electronics applications with innovative semiconductor solutions by leveraging its vast array of technologies, design expertise and combination of intellectual property portfolio, strategic partnerships and manufacturing strength. CMP has been offering STMicroelectronics technologies since nm FDSOI 8ML Several process steps and masking levels are removed from the 28nm bulk process. This compensates the extra cost of the SOI substrate wafers. FD SOI has lower channel leakage current. Carriers are efficiently confined from source to drain: the buried oxide prevent these carriers to spread into bulk. The process comes with NMOS and PMOS devices including body bias voltage scaling from 0V to +2V that helps decreases minimum circuit operating voltage. Standard cells libraries are characterized over the range from 300mV to 1.2V. Transistors can be ideally controlled through independent bias voltages. These body bias techniques allow dynamically modulating the transistor threshold voltage. Dynamic voltage and frequency scaling (DVFS) techniques can be applied more efficiently than alternative processes, therefore achieving high performance at conventional voltages.the process 28nm fully depleted silicon on insulator from STMicroelectronics has the following features: TECHNOLOGY: CMOS28FDSOI Process characteristics IC 28nm CMOS28FDSOI Gate length : 28nm drawn poly length Triple well Fully Depleted SOI devices, with ultrathin BOX and Ground Plane Dual Vt MOS transistors (LVT, RVT) Dual gate oxide (1.0V for core and 1.8V for IO) Dual damascene copper for interconnect 8 metal layers for interconnect 0.1um metal pitch Power supplies supported: 1.8V, 1.0V Embedded memory (Single port RAM/ROM/Double Port RAM ) 2.7.a Design kits DK font end/back end tools Cadence IC DK simulation tools Spectre (Cadence), Eldo (Mentor Graphics), AFS (Mentor Graphics), Hspice (Synopsys), ADS Momentum (Keysight), GoldenGate (Keysight) Price /mm /block > Each block is 2x2mm2 (including scribes: effective design surface: 1.88 x 1.88mm2) Special price for CNRS Institutions: 9850 /mm2 Minimum charge is the price of 1.25 mm2.(x+0.12)*(y+0.12) mm2 Fabrication schedule 9 30 Jan., 15 Apr., 15 Sept., 4 Dec. Packaging All packages provided by CMP Typical Turnaround time 28 to 38 weeks (from GDS2 tape to packaged parts) Including 2 to 3 weeks for data preparation and 2 to 3 weeks for wafer dicing, and prototype delivery Note: 10 metal layers (10ML) process flavor with MiM capacitor option are availabe for the 2 first MPW runs in Courtesy of Lund University, Sweden Jean François PAILLOTIN MPW run Manager STMicroelectronics T.: Jean Francois.Paillotin@imag.fr Olivier GUILLER R&D Engineer 3D IC MPW runs T.: olivier.guiller@imag.fr Kit support contact: cmp support@imag.fr More information: An Introduction to FDSOI: Examples of fabricated circuits in 2016 are reported in the gallery pages of this report. 9 subject to modification, check on web site

32 Pg. 31 Technology Overview 55nm BiCMOS SiGe 8 LM The BiCMOS55 technology of STMicroelectronics is well adapted for applications that are needing RF performance for analog part and high performance in digital part. Bipolar SiGe transistors offer gain and high speed performances for analog devices: - F t = 320GHz, f max = 370GHz CMOS 55nm transistors enable high speed and high density for digital devices: kgates/mm² for high speed gates kgates/mm² for high density gates Examples of analog/rf applications: Automotive radar (24/77GHz) LAN RF transceivers (60GHz) Point to point radio (V Band/E Band) Transmitters in THz frequencies Vector modulators (60GHz) cross section (courtesy of STMicroelectronics) The process offers 8 copper layers for connections and an aluminum capping layer on pads. The 5 thin layers (M1 to M5X) are dedicated to high density connections, the 2 medium thickness layers (M6Z and M7Z) are dedicated to supply and the thick layer is dedicated to RF signals. 3D views inductors (courtesy of STMicroelectronics) Courtesy of Saarland University Saarbrucken, Germany The thick metal8 layer is well adapted for inductors and for transmission lines. Analog applications are improved by high precision MIM capacitors, thin film resistors (TFR, should be available for CMP runs in 2016) and SiGe bipolar transistors. Jean François PAILLOTIN MPW run Manager/ STMicroelectronics T.: Jean Francois.Paillotin@imag.fr Romain VERLY MPW runs/stmicroelectronics 130, 65nm & 55nm T.: Romain.Verly@imag.fr Kit support contact: cmpsupport@imag.fr high speed SiGe HBT transistor (courtesy of STMicroelectronics) Examples of fabricated circuits in 2016 are reported in the gallery pages of this report.

33 Pg. 32 Technology Overview TECHNOLOGY: BiCMOS055 IC 55nm BiCMOS055 Process characteristics CMOS Gate length: 55nm drawn poly length Deep Nwell and Deep Trench Isolation Dual Core Oxide (for 1.2V and for 2.5V) Power supplies 1.2V and 2.5V for core and IO. 2.5V Drift NMOS and PMOS Dual or triple Vt.Low Power and General Purpose MOS transistor offering 8 layers Cu metal stack Ultra Thick Cu Top Metal (2.8 micron) Bipolar SiGe C NPN transistors: High Speed NPN with Ft=320GHz Medium Voltage NPN with Ft=180GHz, and High Voltage NPN Low k inter level dielectric MiM capacitors & Fringe MoM capacitors Millimiter wave inductor Design kits 2.4 DK font end/back end tools Cadence IC DK simulation tools Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), GoldenGate (Keysight) Price 7900 Euro/mm2 if Area less or equal to 4mm Euro/block Each block is 2x2mm2 (including scribes: effective design dimension: 1,88x1,88mm2) Minimum charge is the price of 1.25 mm2.(x+0.12)*(y+0.12) mm2 Fabrication schedule Mar., 22 Jun., 19 Oct. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 2 to 3 weeks for data preparation and 2 to 3 weeks for wafer dicing, and prototype delivery 65nm LPGP (Low Power and General Purpose) The CMOS65LPGP technology has been introduced as general purpose and low power process to address 1.0V and 1.2V applications with 1.2V, 1.8V, 2.5V and 3.3V capable I/Os. The design kit has a large bench of fully characterized devices. The RF kit includes inductors, varactors and MiM capacitors. Courtesy of TELECOM Bretagne, Brest, France Jean François PAILLOTIN MPW run Manager/ STMicroelectronics T.: Jean Francois.Paillotin@imag.fr Romain VERLY MPW runs/stmicroelectronics 130, 65nm & 55nm T.: Romain.Verly@imag.fr Kit support contact: cmpsupport@imag.fr TECHNOLOGY: CMOS065 IC 65nm CMOS065 Process characteristics Gate length : 65nm drawn poly length Dual or triple Vt MOS transistors Dual or triple gate oxide Dedicated process flavors for high performance or low power Dual damascene copper for interconnect Low k (k = 2.9) dielectric 6 or 7 metal layers dor interconnect 0.20um metallization pitch Analog / RF capabilities. Various power supplies supported : 2.5V, 1.2V, 1V Triple standard cell libraries (more than 800kgates/mm2). Design kits DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS Momentum (Keysight), GoldenGate (Keysight) Price 6500 /mm2 if Area less or equal to 5mm [(Area 5) x 5200 ] if 5mm2 < Area < 15mm2 Minimum charge is the price of 1.25 mm2.(x+0.12)*(y+0.12)mm2 Contact CMP for a price quotation when Area is larger Fabrication schedule Mar., 08 Jun., 27 Oct. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 2 to 3 weeks for data preparation and 2 to 3 weeks for wafer dicing, and prototype delivery Examples of fabricated circuits in 2016 in the gallery pages of this report 10 subject to modification, check on web site 11 subject to modification, check on web site

34 Pg. 33 Technology Overview 130nm technology General opening CMP offers a wide range of technology in the 130nm node. The first technology HCMOS9GP is the core 130nm technology for General Purpose, three others technologies are derived: - BiCMOS9MW SiGe 6LM - HCMOS9 SOI FEM - HCMOS9A With an average of four runs in 2014 for each technology, 38 circuits have been fabricated. Hereafter, the presentations of each 130nm technologies: HCMOS9GP The HCMOS9GP technology is the main process for the 130 nm node. It has been introduced as a general purpose process to address 1.2V applications with 1.8V or 2.5V capable I/O s. The Design Kit provides a large bench of fully characterized devices, with standard Core cells and IO cells. Below, these information and characteristics are available on our web site: The design kit is provided with fully characterized devices: - General purpose NMOS and PMOS - Unsilicided P+ Poly resistors - Junction diode - N+Poly and P+Poly capacitors - Interdigited Metal Fringe capacitor (MOM). Romain VERLY MPW runs/stmicroelectronics 130, 65nm & 55nm T.: Romain.Verly@imag.fr Jean François PAILLOTIN MPW run Manager/ STMicroelectronics T.: Jean Francois.Paillotin@imag.fr Kit support contact: cmpsupport@imag.fr TECHNOLOGY: HCMOS9GP IC 130nm HCMOS9GP Process characteristics Gate length: 130nm Triple well Power supply 1.2V Multiple Vt transistor offering (Low Leakage, High Speed) Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV. Isat (for 2 families above): 1.2V: 1.2V: 240/310uA/mic. 6 metal layers in standard.low k inter level dielectric MIM capacitances. 2.5V transistors option is also available. WARNING: the 3.3V transistors option and the Ultra Low Leakage option are no longer available. Design kits 9.2 DK font end/back end tools Cadence IC _USR6 DK simulation tools Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys) Price 2500 /mm2 if Area less or equal to 5mm [(Area 5) x 2200 ] if 5mm2 < Area < 15mm2 Minimum charge is the price of 1.25 mm2 (X+0.12)*(Y+0.12)mm2 Contact CMP for a price quotation when Area is larger. Fabrication schedule Feb., 12 Jul., 22 Nov. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 2 to 3 weeks for data preparation and 2 to 3 weeks for wafer dicing, and prototype delivery BiCMOS9MW The BiCMOS9MW technology was defined by using the 130 nm HCMOS9 as base process and adds additional levels, in front end and back end. It has been introduced to address millimeterwave applications (Frequencies up to 77 GHz), wireless communication (around 60GHz for WLAN), and optical communications systems. Characteristics are available on our web site. 12 subject to modification, check on web site

35 Pg. 34 Technology Overview TECHNOLOGY: BiCMOS9MW IC 130nm BiCMOS9MW Process characteristics CMOS Gate length: 130nm (drawn), 130nm (effective) Triple well.power supply 1.2V Multiple Vt transistor offering (Low Leakage, High Speed) Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV Isat (for 2 families above): 1.2V: 1.2V: 240/310uA/mic Bipolar SiGe transistors: High Speed NPN, Medium VoltageNPN Typical beta (for 2 families above): 1000/1000 Typical Ft (for 2 families above): 230/150GHz 6 metal layers in standard. Low k inter level dielectric. MIM capacitances. 2.5V transistors option is also available. Design kits 2.7 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS GoldenGate (Keysight) Price 3100 /mm2 if Area less or equal to 5mm [(Area 5) x 2600 ] if 5mm2 < Area < 15mm2 Minimum charge is the price of 1.25 mm2.(x+0.12)*(y+0.12)mm2 Contact CMP for a price quotation when Area is larger Fabrication schedule Feb., 12 Jul., 22 Nov. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 2 to 3 weeks for data preparation and 2 to 3 weeks for wafer dicing, and prototype delivery H9 SOI FEM In 2015, the technology H9 SOI FEM comes to replace the previous SOI technology with STMicroelectronics. H9 SOI FEM is built on the same solid basis of the previous standard H9SOI technology and with it shares the robustness, the capability to address all FEM (stand for Front End Module) applications (RF Switches, PA, LNA) and the expertise in RF SOI process. Nevertheless, H9 SOI FEM technology includes several improvements such as cost driven application, performance improvement and a better manufacturing capacity. Below, this information and characteristics are available on our web site: Romain VERLY MPW runs/stmicroelectronics 130, 65nm & 55nm T.: Romain.Verly@imag.fr TECHNOLOGY: H9SOI FEM IC 130nm H9SOI FEM Process characteristics Gate length: 130nm 200mm SOI wafers with high resistive substrate 2.5V Body Contacted CMOS & Floating Body CMOS 5.0V NLDMOS & PLDMOS 1.2V High Speed 130nm CMOSmeta High Linearity MIM capacitor (2fF/mm2) 4 metal layer (thick upper Cu layer 4µm). Design kits 14.1 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre (Cadence), Eldo (Mentor Graphics),ADS GoldenGate (Keysight) Price 2400 /mm2 if Area less or equal to 5mm [(Area 5) x 2000 ] if 5mm2 < Area < 15mm2 Minimum charge is the price of 1.25 mm2 (X+0.12)*(Y+0.12)mm2 Contact CMP for a price quotation when Area is larger Fabrication schedule Feb., 06 Jul., 14 Nov. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 2 to 3 weeks for data preparation and 2 to 3 weeks for wafer dicing, and prototype delivery Jean François PAILLOTIN MPW run Manager/ STMicroelectronics T.: Jean Francois.Paillotin@imag.fr Kit support contact: cmpsupport@imag.fr 13 subject to modification, check on web site 14 subject to modification, check on web site

36 Pg. 35 Technology Overview The design kit is provided with fully characterized devices: MOS Transistors (Floating & Body Contacted) Switches Antenna Tuning PA DCDC 2.5V GO2 Body Contacted CMOS x x x x x 2.5V GO2 Floating Body CMOS x x x x x Hx Filters 2.5V GO2 BC/FB RF NMOS (RonCoff) x x 1.2V GO1 High Speed CMOS (BC & FB) x MIM2 Capacitance x x x x x Capacitors MOM RF Capacitance x x x x x N+ Poly/NWELL 6 ff/um² x x High Voltage NLDEMOS_HP (Ft 36GHz, BVds 13V) x x Transistors PLDEMOS_HP (Ft 19GHz, BVds 8V) x Inductances Family High Current/ High Q Pcells x x x Silicided N+ Poly 10 ohms/sq x Resistors Diodes Unsilicided P+ Poly 320 ohms/sq High value poly resistor RHipo 1Kohms/sq (option) Lateral P+/Nwell non gated diodes (ESD) N+/Pwell non gated diode (Bandgap) x x x x x x x P1 perimeter P2 perimeter LNA P3 perimeter HCMOS9A In 2014, CMP opens access to a new STMicroelectronics technology on the 130nm node based on the HCMOS9GP DRM. This technology targets the mixed digital analog design with energy management features. Below, this information and characteristics are available on our web site: Romain VERLY MPW runs/stmicroelectronics 130, 65nm & 55nm T.: Romain.Verly@imag.fr Jean François PAILLOTIN MPW run Manager/ STMicroelectronics T.: Jean Francois.Paillotin@imag.fr Kit support contact: cmpsupport@imag.fr TECHNOLOGY: HCMOS9A IC 130nm HCMOS9A Process characteristics Gate lenght: 130nm (drawn), 130nm (effective) Triple Well Power supply: 1. 2V for Digital, 4.6V for Analog application Multiple Vt transistor offering (Low Power, Analog) Threshold voltages (for 2 families above): VTN = 700/697mV, VTP = 590/626mV Isat (for 2 families above): TN: 280/658uA/um TP: 104/333uA/um 4 metal layers in standard Fluorinated SiO2 Inter Metal dielectrics Bipolar Transistors NPN Typical beta: 90 Ft Vbc=0: 2,4GHz 2 specific implant levels: NDRIFT & PDRIFT MIM 5fF/µm2 capacitor Double gate oxide for analog features Design kits 10.7 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys) Price 2200 /mm2 if Area less or equal to 5mm [(Area 5) x 1900 ] if 5mm2 < Area < 15mm2 Minimum charge is the price of 1.25 mm2 (X+0.12)*(Y+0.12)mm2 Contact CMP for a price quotation when Area is larger Fabrication schedule Nov. Packaging All packages provided by CMP Typical Turnaround time weeks (from GDS2 tape to packaged parts) Including 2 to 3 weeks for data preparation and 2 to 3 weeks for wafer dicing, and prototype delivery The design kit is provided with fully characterized devices: HV MOS - N+ Poly/ 8.5 nm - N&P 8.5 nm Gate Oxide 20 V Drift MOS Extra masks : NDRIFT & PDRIFT - N&P 8.5nm Gate oxide 10V Drift MOS Bipolar Transistors - NPN Bipolar N+/ Pdrift/ NISO Extra mask : PDRIFT 15 subject to modification, check on web site

37 Pg. 36 Technology Overview - PNP Capacitor - N+ Poly/ 8.5 nm Gate Oxide/ Nwell GO2 - MOM Capacitor - Plate capacitor - MIM5 Capacitor BCD8SP ST Microelectronics «Smart Power» BCD8SP technology combines high power transistors with low power digital and analog devices on a single chip. This technology is available through CMP. Typical applications include Power Management for Mobile devices, Printer, Hard disk driver power combo, Industrial power conversion devices or motor driver. BCD in Electronic System Partitioning, Courtesy of ST Microelectronics TECHNOLOGY: BCD8SP IC 0.18µm BCD8SP Process characteristics Temperature range: 40 C to +175 C.0.18 µm Bipolar CMOS DMOS 4 metal layers (2 top metal options : Al or CuRDL) 1.8V 5V: digital & analog 10V 42V: power MOS Up to 48V devices and rail Design kits 2.0.a DK font end/back end tools Cadence IC DK simulation tools Spectre (Cadence), Eldo (Mentor Graphics) Price 2800 /mm2 if Area less or equal to 5mm [(Area 5) x 2300 ] if 5mm2 < Area < 15mm2 Minimum charge is the price of 3.00 mm2 (X+0.12)*(Y+0.12)mm2 Contact CMP for a price quotation when Area is larger, [(Area 5) * 2100 Euro] if 5mm2 < Area < 15mm2 Contact CMP for a price quotation when Area is larger Fabrication schedule Mar., 11 Sept. Packaging All packages provided by CMP Typical Turnaround time 18 weeks Including 2 to 3 weeks for data preparation and 2 to 3 weeks for wafer dicing, and prototype delivery Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: Kholdoun TORKI Technical Director T.: Analog + Digital + Power & HV on one chip : Courtesy of STMicroelectronics Kit support contact: cmp support@imag.fr 16 subject to modification, check on web site

38 Pg. 37 Technology Overview Photonic MPW Prototyping In addition to ICs and MEMS, CMP provides Photonic MPW services for prototyping and low volume production. Si310 PHMP2M This MPW capability on 310nm SOI platform is offering best performance for grating couplers, multilevel option for silicon patterning that allows the design of various passive and high speed active devices as silicon electro optic modulators and germanium photo detectors and still coupled with thermal tuning capability as metal heaters. Two AlCu levels are available for more optimal routing which is also compatible for backend treatment as Under Bump Metallization. TECHNOLOGY: Si310 PHMP2M Process characteristics Photonic MPW Prototyping Si310 PHMP2M 200mm SOI platform SOI substrate HR BOX 800nm / Si 310nm Tungsten plugs 2 metal layers Passive structures (mask layers DUV 193nm) Critical dimension on mask 120nm : 300nm/165nm, Optional slab 65nm (Deep Rib), 1D & 2D Grating couplers, Waveguides, bends Active devices: Lateral Ge PIN Photodiode, MZ and RR Modulators, Multimode interferometers, TiN Metal heater Design kits 1.3 DK font end/back end tools Cadence IC 6.1.5, Mentor Graphics Pyxis , Phoenix Software (under development) DK simulation tools Eldo Price 3200 /block > Each block is 2x1mm2 or 1x2mm2 Minimum charge is the price of 2 blocs or 4mm2 if Area less or equal to 20mm /block > Each block is 2x1mm2 or 1x2mm2 Minimum charge is if Area more than 20mm2 Fabrication schedule Mar., 11 Sept. Packaging All packages provided by CMP Typical Turnaround time 32 weeks (from GDS2 tape to packaged parts) Si310 PHMP2M process cross section courtesy of Leti Cea 1 refer to the price list 2 subject to modification, check on web site Courtesy of Leti Cea Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: Courtesy of Tyndall Institute Kholdoun TORKI Technical Director T.: Kit support contact: cmp support@imag.fr 17 subject to modification, check on web site

39 Pg. 38 Technology Overview Micro Electro Mechanical Systems (MEMS) Prototyping In addition to ICs, CMP is providing several types of MEMS technologies for prototyping and low volume production: Integrated bulk micromachining technologies and specific surface micromachining technologies. ams 0.35 µm Bulk Micromachining This technology is based on standard CMOS or BiCMOS process allowing integration of MEMS sensor and front end electronic on the same die for better signal to noise ratio. Suspended passive devices or structures can be made with this technology. Applications include thermal inertial sensors and infrared sensors. TECHNOLOGY: Frontside Bulk Micromachining Process characteristics MEMS Bulk Micromachining Frontside Bulk Micromachining ams 0.35µm processes. Process cross section. Thick Metal module instead of Metal 4 module and with MIM capacitor module Poly layer(s): 2, high resistive poly Maximum die size: 2cm x 2cm DLP Usable cells: about 300 digital cells Available I/O: I/O cell library with digital pads is available 3.3V, 3V/5V, 5V with internal level shifters Temp. range: 40 C. / +125 C Supply voltage: 5V or 3.3V Die size: Minimum charge of 3 mm² Design kits 4.10, 3.80 DK font end/back end tools Cadence IC Cadence IC _USR6 DK simulation tools Spectre, Hspice, Ultrasim, NC Sim, ams Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys) Price 650 /mm2 if area is less or equal to 10mm [(Area 10) x 550 ] if area > 10mm2 Fabrication schedule 18 Packaging All packages provided by CMP Typical Turnaround time 14 weeks (from GDS2 tape to packaged parts) Front side bulk micromachining cross section Bulk micromachining Backside, courtesy Tima Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr TECHNOLOGY: Backside Bulk Micromachining Process characteristics Design kits DK font end/back end tools DK simulation tools Price Fabrication schedule 19 Packaging Typical Turnaround time MEMS Bulk Micromachining Backside Bulk Micromachining ams 0.35µm processes 4LM + Post Process On chip suspended membrane with piezoresistors. Contact CMP All packages provided by CMP 18 subject to modification, check on web site 19 subject to modification, check on web site

40 Pg. 39 Technology Overview MEMSCAP Created in 1997, MEMSCAP provides standard and custom innovative MEMS_based solutions in market segments such as aerospace, medical/biomedical and telecommunications. Available through CMP since 1998, the Multi User MEMS Processes (MUMPs) is a Multi Project Wafer program offering customers cost effective access to MEMS prototyping and low volume production through different processes: PolyMUMPs, SOIMUMPs and PiezoMUMPs. PolyMUMPs By removing the sacrificial layers, suspended structures can be made. Applications of PolyMUMPs include acoustic sensors (microphone), accelerometers, microfluidic devices and display technology. TECHNOLOGY: PolyMUMPs Process characteristics MEMS Specific MEMS technologies PolyMUMPs Fixed die size: 1cm x 1cm Polysilicon/gold.Surface micromachining Design kits 1, MEMS Pro v7.0 DK font end/back end tools Cadence IC Cadence IC DK simulation tools Price Fabrication schedule 20 Packaging Typical Turnaround time $3,700 Price for Educational Institutions and Research Laboratories $4,600 Price for Industrial Companies Additional prices for Subdicing and Release: Subdicing: $220per cut lane and per 15 chips HF Release: $870 flat rate for up to 60 die/subdie Su 05 Jan., 29 Mar., 29 Sept. All packages provided by CMP 10 weeks (from GDS2 tape to packaged parts) PolyMUMPs SEM cross section (Courtesy of MEMSCAP) Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr SOIMUMPs Both sides of the SOI wafer can be patterned and etched up to the oxide layer through Deep Reactive Ion Etching (DRIE) allowing for through holes structures and optical path. A shadow mask metal process is used to provide coarse metal structures such as bonding pads, electrical connections and optical mirror surfaces. A second metal layer can be used for bond pads and connectivity. The 2µm feature size and structural layer thickness (10/15 µm) allow for gyroscope applications, whereas the through hole capability and mirror surfaces can be used to design optical and display technology devices. TECHNOLOGY: SOIMUMPs Process characteristics MEMS Specific MEMS technologies SOIMUMPs Fixed die size: 0,9cm x 0,9cm SOIMUMPS + piezoelectric layer Design kits 1, MEMS Pro v7.0 DK font end/back end tools Cadence IC Cadence IC DK simulation tools Price Fabrication schedule 21 Packaging Typical Turnaround time 20 subject to modification, check on web site 21 subject to modification, check on web site $3,700 Price for Educational Institutions and Research Laboratories $4,600 Price for Industrial Companies. Additional prices for Subdicing and Release: Subdicing: $220per cut lane and per 15 chips HF Release: $870 flat rate for up to 60 die/subdie 02 Mar., 31 May, 30 Aug. All packages provided by CMP 10 weeks (from GDS2 tape to packaged parts)

41 Pg. 40 Technology Overview Cross section showing Reactive Ion Etching (Courtesy of MEMSCAP) Cross section of RIE etching PiezoMUMPs PiezoMUMPs is the most recent technology available through the MUMPs offer and was introduced in Based on a SOIMUMPs process (10 µm silicon thickness) it adds a 0.5 µm Aluminum Nitride piezoelectric layer. Active piezoelectric devices can be made with this process and allow the development of energy harvesting applications, ultrasonic transducers, acoustic sensors or actuators. TECHNOLOGY: PiezoMUMPs Process characteristics MEMS Specific MEMS technologies PiezoMUMPs Fixed die size: 0,9cm x 0,9cm Deep Reactive Ion Etching on Silicon on Insulator Design kits 1; MEMS Pro v7.0 DK font end/back end tools Cadence IC Cadence IC DK simulation tools Price Fabrication schedule 22 Packaging Typical Turnaround time $3,700 Price for Educational Institutions and Research Laboratories $4,600 Price for Industrial Companies For 15 identical chips, 1cm x 1cm (fixed size) Contact CMP for multiple location prices 12 Jan., 17 May, 07 Sept. All packages provided by CMP 10 weeks (from GDS2 tape to packaged parts) PiezoMUMPs cross section and devices courtesy of MEMSCAP Courtesy of MEMSCAP Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr 22 subject to modification, check on web site

42 Pg. 41 Technology Overview Micralyne MicraGEM Si TM MicraGEM Si TM is offered to CMP user community thanks to an agreement and partnership with CMC. MicraGEM Si TM technology based on a Silicon on insulator (SOI) MEMS process features two thick SOI structure layers and gold metallization on the top surface, enabling the design of vertical comb drive actutators along with optically flat silicon surface. Target applications include variable optical attenuators (VOA) and wavelength selective switch (WSS) modules as well as resonators and bio sensors. Horizontal comb drives can also be created for use in inertial sensors. TECHNOLOGY: MicraGEM Si TM Process characteristics Design kits DK font end/back end tools DK simulation tools Price Fabrication schedule 23 Packaging Typical Turnaround time MEMS Micralyne MicraGEM SiTM MicraGEM Si MicraGEM Si TM technology based on a Silicon on insulator (SOI) MEMS process features two thick SOI structure layers and gold metallization on the top surface, enabling the design of vertical comb drive actutators along with optically flat silicon surface Die size: Available in sizes 4mmx4mm, 4mmx8mm, 8mmx8mm Read more: ( platforms/micragem si/) Fixed size: Price for Educational Institutions and Research Labs $4,800 (4mm x 4mm).$7,200 (4mm x 8mm) $12,000 (8mm x 8mm) Price for Industrial Companies $6,000 (4mm x 4mm).$8,000 (4mm x 8mm).$12,650 (8mm x 8mm). 10 Mar. All packages provided by CMP 15 weeks (from GDS2 tape to packaged parts) SEM Micrograph of the VOA Chip Base_Mirror_handle_ISO Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr Base_Mirror_Metal_front 23 subject to modification, check on web site Base_Mirror_Metal_ISO

43 Pg. 42 Technology Overview Teledyne DALSA MIDIS MEMS technology is offered to CMP user community thanks to an agreement and partnership with CMC. Teledyne DALSA is an international leader in high performance digital imaging and semiconductors. MEMS Integrated Design for Inertial Sensors (MIDIS ) The MEMS Integrated Design for Inertial Sensors (MIDIS ) platform available through CMP and CMC is designed to provide a standard process for manufacturing accelerometers and gyroscopes and integrating them into an Inertial Measurement Unit (IMU) for consumer (mobile), automotive, and sports/health applications The MIDIS technology platform is based on efficient wafer level bonding to minimize overall die size. Getter free controlled high vacuum sealing allows for high Q factor for gyroscopes (Q>20000) along with optimal air damping for accelerometers. Comb height control allows out of plane sensing. Applications also include resonators. Through Silicon Vias enable compact design ready for co packaging. TECHNOLOGY: MIDIS TM Process characteristics Design kits DK font end/back end tools DK simulation tools Price Fabrication schedule 24 Packaging Typical Turnaround time MEMS TDSI MIDIS TM MIDIS MEMS Integrated Design for Inertial Sensors (MIDIS TM) 1cm Die size: From 16mm² to 64mm² The MIDIS TM Platform is being offered as Multi Project Wafer (MPW) service through CMC Microsystems. MK15S1 V1P3 Conventor Catapult (Designer) from CoventorWAreTM Cadence IC ANSYS Contact CMP 10 Mar. All packages provided by CMP Typical: 15 weeks (from GDS2 tape to packaged parts) SEMI MIDISTM cross section and MIDISTM cross section Courtesy of Teledyne DALSA Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Kit support contact: cmp support@imag.fr 24 subject to modification, check on web site

44 Pg. 43 Technology Overview Standard Packaging Packaging is an important issue not to be neglected for the complete succes of a prototype production and implementation. The first step before starting a design is to select a package solution and technology with respect to project constraints. Eventually, a standard package is needed and must selected. In such a case, pad ring has to match with cavity of the selected package to optimize the whole interconnection. If the pad ring is not correct you will have to buy a dedicated package, this is time consuming and price can be significantly higher than price of silicon. General assembly rules and common errors are available on the web site. Wire bond packaging process flow for MPW runs CMP offers a complete assembly service based on a wide range of ceramic and plastic packages for prototyping and low volume production. Packaging guidelines Prototypes packaging is a hard issue and yield can t be guaranteed. The pad ring of the circuit have to match with the selected package to optimize the number of good samples. When you request bonding of additional circuits after runs you have to provide us with 5 additional dies for setup of the bonding machine. These dies can be damaged by setup. At least the following simple rules have to be followed for prototypes in ceramic packages. They are not strong enough for low volume production: - Bonding pads have to be connected to the side of the package that is facing. - Use a homogenous spacing for pads with the first pad and the last pad near corners. - Use the biggest width of bonding pad compatible with the number of pad in a side. - All bonding pads should have the same size and are perfectly aligned along circuit edges. - Bonding pad structure has to be strong enough to avoid stretch off when bonding wires. - No bonding pad in corners. - Avoid long wires. Check with us for wires longer than 4500µm. - Angles of wires with the circuit edge have to be between 45 and A bonding wire can t cross another bonding wire (this generates a shortcut). A: the best configurations. B, C: good configurations when the number of pads is smaller. D: dummy pads are correctly inserted. E: pads are concentrated in the middle of the circuit s side. F: dummy pads are concentrated on top (long wires and acute angles). G: too many pads, pads in the corner, the 2 first pads and the 2 last pads are not connected to the package side that is facing. H: pads are not aligned. Jean François PAILLOTIN MPW Runs Manager/ STMicroelectronics T.: Jean Francois.Paillotin@imag.fr Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr The diameter of wires used for a circuit depend on size of the smallest pad of the circuit and on type of bonding (ball bonding or wedge bonding). Some factors that are reducing yield: Long wire (shorts with neighbouring wires or with package cavity). Small pads (thin diameter for wires, risk to stretch wires off pads). Acute angles between wire and circuit edge (< 45, shorts). Pads not perfectly aligned along the circuit edge (shorts). Pads incorrectly distributed in a side of the circuit (shorts). Bad bonding pad structure (pad destroyed by bonding). Bonding pads in corners (generation of crack on die). Big circuit ratio, length/width > 1.8 (long wires + acute angles).

45 Pg. 44 Technology Overview Available standard package types and associated services - A 200 NRE is applied by project for each additional bonding diagram. - A 200 service fee is applied for a new packaging request of a previously processed project. - An additional service fee of 300 is applied for packaging requests of IC not fabricated by CMP. Minimum ordering: 5 packages per bonding diagram have to be ordered. Depending on IC pad size, additional set up fees are invoiced: - for 40µm to 50µm pads : for 51µm to 60µm pads : for 61µm to 75µm pads : for pads largger than 76µm no set up fees except for CQFPs and for QFNs packages: 200 Additional bonding wires can be charged. Price is quoted on a case per case basis for circuits with long wires. For small volume packaging service, please contact us for a specific quotation. Types & associated services Relevant features Price per unit Small Outline (SOIC) Ceramic SOIC8: 67,90 SOIC16: 69,90 SOIC20: 80,60 SOIC24: 83,80 SOIC28: 87,50 C Leaded Chip Carriers (CLCC) Ceramic CLCC16: 41,30 CLCC20: 43,10 CLCC28: 44,60 CLCC32: 47,60 CLCC44: 54,00 CLCC48: 58,40 CLCC68: 76,90 CLCC84: 75,30 J Leaded Chip Carriers (JLCC) Ceramic/Plastic JLCC28: 67,90 JLCC44: 73,00 JLCC52: 80,60 Dual in line (DIL) Ceramic DIL8: 31,90 DIL14: 33,10 DIL16: 34,40 DIL18: 53,80 DIL20: 36,90 CerQuad Flat Pack (CQFP) Ceramic Up to 256 I/Os. Available options for pins: Z: gull wing J: Jleaded F: Flat Default option is pins bent in gull wing. Pin Grid Arrays (PGA) Ceramic Up to 352 pins PGA68: 69,90 PGA84: 80,60 PGA100: 95,30 PGA120: 106,60 PGA144: 115,50 JLCC68: 83,80 JLCC84: 97,10 DIL24: 49,50 DIL28: 53,60 DIL40: 58,60 DIL48: 63,50 CQFP20J: 55,30 CQFP120Z: 123,10 CQFP44ZJF: 74,30 CQFP128Z: 125,00 CQFP64ZJF: 90,30 CQFP144Z: 134,10 CQFP68JF: 87,80 CQFP160Z: 142,10 CQFP80Z: 90,30 CQFP208Z: 178,40 CQFP84J: 91,50 CQFP240Z: 248,80 CQFP100ZF: 113,10 CQFP256Z: 261,30 PGA160: 126,90 PGA180: 138,50 PGA208: 187,90 PGA224: 223,40 PGA256: 244,90 Thin Quad Flat Pad (TQFP) Plastic open cavity 25 samples minimum. Theses packages need thinned dies, lids must be sealed. TQFP32: 54,60 TQFP44: 62,30 TQFP52: 69,30 TQFP64: 77,50 Quad Flat Non Leaded (Open Cavity QFN) Plastic open cavity Thermal performance, low inductance, high frequency. Theses packages need thinned dies. Plastic Open Cavity Packages Plastic Allows a smooth transfer between ceramic and plastic pakage (QFN, QFP, PLCC, PGA, BGA) QFN12: 45,80 QFN16: 45,80 QFN24: 58,40 QFN28: 58,40 QFN32: 68,60 QFN36: 72,40 QFN40: 73,00 Upon request QFN44: 75,50 QFN48: 77,50 QFN52: 79,40 QFN56: 82,50 QFN64: 94,00 QFN80: 105,40 Optical resin, Chip On Board (COB), Thermal solutions, Metallic package & Hermetic package Upon request Jean François PAILLOTIN MPW Runs Manager/ STMicroelectronics T.: Jean Francois.Paillotin@imag.fr Azedine MANAA MPW Run Engineer ams & MEMS T.: Azedine.Manaa@imag.fr Wafer level thinning ams 0.35 µm (8 ): standard thinning to 530µm ams 0.35 µm (8 ): thinning to 250 µm on Free of charge request STMicroelectronics 130 nm (8 ): standard thinning to 375µm Die level thinning Down to 150 µm (absolute limit 100µm) Area<1mm 2 : 10 /die 1mm 2 <Area<5mm 2 : 13 /die 5mm 2 <Area<10mm 2 : 16 /die 10mm 2 <Area<15mm 2 : 20 /die 15mm 2 < Area contact CMP. DRIE dicing Option of thinning to 50µm. Clean borders of the chips, a better precision than conventional dicing. Upon request

46 Pg. 45 Technology Overview MEMS Packaging Several solutions are available for MEMS packaging: Optical resin/transparent Lids/Chip On Board (COB)/Thermal solutions/metallic package/hermetic package. Wafer and die thinning Wafer level thinning ams 0.35 µm (8 ): standard thinning to 530µm ams 0.35 µm (8 ): thinning to 250 µm on request STMicroelectronics 130 nm (8 ): standard thinning to 375µm STMicroelectronics 65 nm (12 ): standard thinning to 250µm STMicroelectronics 28 nm (12 ): standard thinning to 250µm With this solution, wafer s backside is smooth. Die level thinning Down to 150 µm (absolute limit 100µm) Backside picture With this solution, circuits backside is a bit rough with no issue for packaging. Flip Chip Packaging In 2016, CMP has been working toward offering Flip Chip packaging solutions to provide our designer community with an assembly and interconnect alternative to the classical wire bond packaging on dies produced through MPW runs. Compared to Wire Bond packaging, Flip Chip interconnects offer several advantages: decreased footprint, lower interconnect impedance allowing higher signal speed and better heat dissipation. Our offers have been developed with the objectives to be technically reliable and simple to implement but also economically affordable. Those new packaging opportunities, as well as our current development are described below. For more information on CMP flip chip offers, please contact CMP Packaging engineer. Furthermore, new announcements are yet to come during 2017 concerning flip chip capabilities on CMP MPW runs, stay tuned for more information. ams wafer level bumping option In partnership with ams, CMP introduces a new bumping option available on any ams MPW run. This option allows the deposition of an array of solder balls at wafer level, with an I/O pitch that is compatible with traditional printed circuit board (PCB) assembly processes. For mechanical reasons solder balls are usually evenly distributed over the whole chip surface and electrically connected to the IC s CMOS pads by means of a redistribution layer (RDL) included in the option. Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: lyubomir.kerachev@imag.fr ams Wafer level bumping option is supported within ams design kit (hit kit) upon request. It is available on any CMP MPW runs for a flat fee of 6200 per design (for 25 chips delivered). Olivier GUILLER R&D Engineer 3D IC MPW Runs T.: olivier.guiller@imag.fr

47 Pg. 46 Technology Overview Advanced packaging OPEN 3D Post Process CMP, in partnership with CEA Leti in the frame of the IRT Nanoelec, offers a set of post processes, at wafer level, allowing various types of 3D assemblies. Those post processes are carried out after standard MPW runs on a selected subset of technologies. The opportunities are to integrate 3D interconnections to chips processed through CMP, in order to enable flip chip on organic or ceramic substrates as well as Die to Die or Die to Interposer assemblies. CMP also supports the assembly process itself, at die to substrate, die to dieand die to wafer levels thanks to qualified subcontractors. CMP provides a set of add on and tutorials to help the designers in their choices and designs. Two types of post processes are made available, including different options: - Front side: 3D interconnections (Bumps, µ Bumps or UBM). - Back side: Wafer thinning, TSV (via last) and RDL, 3D interconnections (Bumps). Post process options must be chosen according to the required assembly, an example is given below: Example of a Die to Die, Face to face assembly with bottom die backside processing In this example, micro bumps have been fabricated on the top die front side. They are landing on bottom die Under Bump Metallization (UBM) that has been fabricated on its front side, allowing a fine pitch interconnection between the two dies. Furthermore, bottom die back side has been thinned so the first metal level of the BEOL stack can be connected thanks to Through Silicon Vias (TSV) and a copper deposition, acting as a backside Redistribution Layer (RDL) as well. Finally, bumps has been fabricated on top of this RDL, allowing an interconnection with the outer world (PCB, BGA, organic or ceramic substrate, package ) with a looser pitch than µ Bumps. Post processes made available after MPW runs gives CMP users the opportunity to have access to advanced packaging techniques on compatible nodes. For more information on the available types of assemblies and their application area, please consult the 3D Post process application examples section. OPEN 3D post processing is available upon request, please contact us to introduce your 3D project and evaluate opportunities for CMP to fullfill your needs. For more specific information on OPEN 3D modules (size, pitch, thickness ), please refer to the table below as well as additional information on CMP website. Courtesy of Cea Leti Bumps Micro Bumps UBM TSV LAST Backside RDL Cu/SnAg ; ø65 µm ; 120 µm min pitch ; ~60 70 µm thickness Cu/SnAg ; ø25 µm ; 50 µm min pitch ; ~20 µm thickness TiNiAu ; 25 µm min width; 50 µm min pitch ; 1 µm thickness Ø60 µm x 120 µm depth ; 120 µm min pitch Cu ; 20 µm min width ; 40 µm min pitch ; 4 8 µm Thickness Olivier GUILLER R&D Engineer 3D IC MPW Runs T.: olivier.guiller@imag.fr Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: lyubomir.kerachev@imag.fr Post process application examples Leti OPEN 3D post processes allow the manufacturing of 3D modules on top of various technologies. Thanks to this, numerous multidie architectures are made possible. The next section introduces several structures illustrated with possible corresponding applications. However, please keep in mind that this is not an exhaustive list, other mixes of those 3D modules are possible to fulfill specific requirements.

48 Pg. 47 Technology Overview Single die bumping for flip chip packaging Beside the footprint reduction, the main advantage of manufacturing 3D interconnections (such as bumps) on a die is to reduce the overall impedance of the system compared to a classical wirebonding solution, a critical parameter for power driven and high speed applications. Furthermore, TSV integration allows photon sensing and micromachining applications. Bumped die for face to face packaging Bumped die for Back to face packaging Die to die integration Die to die integrations allow the combination of two technologies with different fabrication processes, thus opening the door to a wide range of applications (CPU Memory, Analog Digital, Power device Logic, Logic Photonic, Sensor Logic ). In comparison with a System in Package (SiP) solution, the fine pitch and high number of I/Os offered by the µ bumps interconnections allows a drastic increase of the inter dies bandwidth and a lower power consumption. Face to face assembly, bumped bottom die Back to face assembly, wire bonded bottom die 2.5D integration on silicon interposer The silicon interposer allows side by side assembly of multiple heterogeneous dies. Potential application includes: Logic die / Analog die / Power devices / Photonic / [ ] co integration in silicon package, Multiprocessor, Network on Chip (NoC) Beside, since the top dies and the interposer shares the same CTE, the latest act as a mechanical stress buffer between top dies BEOL stack and an underneath organic substrate (for a back side processed silicon interposer). Courtesy of Cea Leti Olivier GUILLER R&D Engineer 3D IC MPW Runs T.: olivier.guiller@imag.fr Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: lyubomir.kerachev@imag.fr Both Back to face and Face to face assembly on wire bonded silicon interposer 3D post processed chips design, verification and manufacturing flow Post processed wafers, from which are extracted ICs, results from the combination of two technologies which requires special considerations during design, verification and fabrication. The goal of this section is to describe how ICs, dedicated to advanced packaging, are processed each step of the way. 3D post process design tools In order to facilitate design of ICs undergoing a 3D post process, CMP and LETI have co developed a 3D Kit allowing the implementation of additional layers required for 3D modules manufacturing. This Kit works as an add on applied to the original foundry DK, it contains: - Open 3D post process technology integration to Cadence, alongside the original technology. - A library of several ready to use 3D modules (Bumps, µ bumps, TSV )

49 Pg. 48 Technology Overview - A calibre die level DRC Deck, checking the design conformity to Open 3D Design Rules Manual. This 3D kit, alongside the Open 3D DRM, allows designers to easily integrate 3D modules to their designs. In addition to the 3D Kit, a calibre assembly level DRC Deck (3DSTACK) checks the additional rules specific to silicon on silicon assemblies (such as the verification of electrical connections between dies). The development of a custom assembly level DRC is required for every 3D projects, and is part of CMP service to help the designer on their 3D projects. Be aware that this Assembly level DRC is not distributed to CMP users, but they have access to DRC results and comments. CMP Verification flow Upon receipt of the GDSII containing information for both technologies from the designer, CMP treatment of 3D circuits is slightly different from classical ones in the way that both processes compliance are verified. Furthermore, for silicon on silicon assembly only, an additional verification step is carried out to check the whole assembly at once. The following graph illustrates the verification flow of a die to die assembly. Example of a verification flow for a die to die assembly Courtesy of Cea Leti Manufacturing flow example 3D Post processed dies involve two different foundries. The following graph illustrates this process for bumps manufacturing on an ST processed wafer. The wafers are first processed on a 65 nm node at STMicroelectronics. Once the process is complete, wafers are sent to CEA LETI cleanroom where they will undergo bumps fabrication process. Wafers are then diced, sent back to CMP before they are shipped to the customer with a manufacture report companion. Olivier GUILLER R&D Engineer 3D IC MPW Runs T.: olivier.guiller@imag.fr Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: lyubomir.kerachev@imag.fr Example of the manufacturing flow for a post processed ST CMOS065 die

50 Pg. 49 Technology Overview Passive Silicon Interposer CMP, in partnership with ams, offers a 2.5D integration solution through specific MPW runs for silicon interposer prototyping and production, allowing side by side integration of heterogeneous dies with higher interconnection densities than organic substrates, thus promoting package footprint reduction, increased inter die bandwidth and decreased power consumption. This interposer offer is based on ams C35B4M3 0,35µ metal stack (including 4 metal levels for routing, with a thick metal top), upon which a post process is performed by our packaging subcontractor in order to produce a front side Under Bump Metallization (or UBM) consisting of a Ni/Pd/Au stack. For more information on technical characteristics, please refer to the ams C35B4M3 0,35µ technology overview. The resulting interposer is ready to support flip chip dies and is compatible with CMP OPEN 3D microbumps post process offer (with a 50 µm min pitch). The interposer includes Wire bonding pads to allow its connection to a PCB (as chip on board) or a compatible package. Two options are now available for Silicon interposer prototyping: - Passive Interposer: Only the backend is processed, for high density routing application and passive components integration (inductor, metal resistors, MIM capacitor ). Passive interposer runs are now available for a reduced cost. - Active Interposer: Active layers are available for CMOS integration as well as Poly poly capacitors and Poly resistors, allowing the implementation of a wider range of functions to the interposer. Access to this passive silicon interposer offer is based upon a formal DK request as well as juridic and partners approval through our web interface. Interposer run offer is available at any time. Olivier GUILLER R&D Engineer 3D IC MPW Runs T.: olivier.guiller@imag.fr Lyubomir KERACHEV R&D Engineer/Adv. Packaging & MPW Runs T.: lyubomir.kerachev@imag.fr

51 Pg. 50 MPW run schedule MPW run schedule25 Multiproject wafer (MPW) fabrication runs scheduled: ams Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec C18A µm CMOS H18A µm HV CMOS C35B4C µm CMOS C35B4O µm CMOS Opto C35B4OA 0.35 µm CMOS Opto C35B4M µm CMOS Thick M H35B4D µm HV CMOS S35D4M µm SiGe STMicroelectronics Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec CMOS28FDSOI 28 nm SOI 10ML CMOS28FDSOI 28 nm SOI 8ML BiCMOS nm BiCMOS CMOS nm CMOS HCMOS9GP 130 nm CMOS HCMOS9A 130 nm HV CMOS 2 BiCMOS9MW 130 nm SiGe H9SOI FEM 130 nm SOI BCD8SP 160 nm BCD IRT Nanoelec/LETI CEA Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Photonic MPW Prototyping Si310 PHMP2M MEMSCAP Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec MUMPS 2.0 µm polymumps MUMPS 3.0 µm PiezoMUMPS MUMPS 3.0 µm SOIMUMPS Micralyne Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec MicraGEM Si TM 10 Teledyne DALSA Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec MIDIS 10 Notes: - All MPW runs are subject to modification metal layers (10ML) process flavor with MiM capacitor are standard options on the 2 first MPW runs in These options are still available for the following MPW but, specific quotation will apply. Please contact us. - MPW runs compatible with Open 3D wafer level post processing. 25 Subject to modification, check on web site

52 Pg. 51 Circuit Gallery Circuit Gallery Examples of IC's manufactured through CMP from end 2015 & to 2016 Title: IC for FM MEMS Gyroscopes Inst.: Politecnico di Milano Run & Topcell name: A35C16_1ICARUS01 Title: SleepTalker: a ULV a IR UWB Transmitter SoC in 28nm FDSOI achieving 14pJ/bit at 27Mb/s Inst.: Université catholique de Louvain, ICTEAM Institute Run & Topcell name: S28I15_1S_TALKER Publication(s): P. Minotti, G. Mussi, S. Dellea, C. Comi, V. Zega, S. Facchinetti, A. Tocchio, A. Bonfanti, A. L. Lacaita and G. Langfelder, "A 160 μa, 8 mdps/ Hz Frequency Modulated MEMS Gyroscopes", (accepted for publication in) 2017 IEEE International Symposium on InP. Minotti, G. Mussi, S. Dellea, C. Comi, V. Zega, S. Facchinetti, A. Tocchio, A. Bonfanti, A. L. Lacaita and G. Langfelder, "A 160 μa, 8 mdps/ Hz Frequency Modulated MEMS Gyroscopes", (accepted for publication in) 2017 IEEE International Symposium on In Contact(s): Andrea Bonfanti, Paolo Minotti, Giorgio Mussi, Giacomo Langfelder, andrea.bonfanti@polimi.it, paolo.minotti@polimi.it, giorgio.mussi@polimi.it, giacomo.langfelder@polimi.it Title: awaxe_v1 Inst.: APC AstroParticule & Cosmologie Run & Topcell name: A35S16_1awaXe_v1 Publication(s): G. de Streel, F. Stas, T. Gurné, F. Durant, C. Frenkel and D. Bol, SleepTalker: a 28nm FDSOI ULV a IR UWB Transmitter SoC achieving 14pJ/bit at 27Mb/s with Adaptive FBB based Channel Selection and Programmable Pulse Shape, in Proc. IEEE Symp. VLG. de Streel, F. Stas, T. Gurné, F. Durant, C. Frenkel and D. Bol, SleepTalker: a 28nm FDSOI ULV a IR UWB Transmitter SoC achieving 14pJ/bit at 27Mb/s with Adaptive FBB based Channel Selection and Programmable Pulse Shape, in Proc. IEEE Symp. VL Contact(s): David Bol, david.bol@uclouvain.be Title: 65nm Analog CMOS Encoded Neural Network Inst.: TELECOM Bretagne Run & Topcell name: S65C15_3Chip_ENN_Mono Chantal BÉNIS MOREL Communication /Conference Management T.: Chantal.Benis@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Contact(s): Cyril BEILLIMAZ, Fabrice VOISIN, Si CHEN, Damien PRELE, cyril.beillimaz@apc.in2p3.fr, voisin@apc.in2p3.fr, sichen@apc.in2p3.fr, damien.prele@apc.in2p3.fr Contact(s): Cyril Lahuec, Cyril.Lahuec@telecombretagne.eu

53 Pg. 52 Circuit Gallery Title: SQMUX128_evo Inst.: APC AstroParticules & Cosmologie Run & Topcell name: A35S16_1SQMUX128_evo Title: PADS UFRJ Inst.: Federal University of Rio de Janeiro Run & Topcell name: A18V16_4CHIP Contact(s): Fabrice Voisin, Damien Prele, Title: low jitter low spurs All digital phase locked loop Inst.: Lund University, Electrical and Information Technology Run & Topcell name: S65C15_2eitjun15b Contact(s): Antonio Petraglia, Title: Low Frequency 5 b Delta Sigma Modulator with Improved DEM Algorithm Inst.: Lund University, Electrical and Information Technology Run & Topcell name: S65C15_2eitjun15c Contact(s): Ahmed Mahmoud, stefan.molund@eit.lth.se Title: 100 GS/s 6 bit 50 GHz Dual Core Flash ADC Inst.: Chair of Electronics and Circuits, Saarland University Run & Topcell name: S55S15_1AD100 Contact(s): Pietro Andreani, ietro.andreani@eit.lth.se Chantal BÉNIS MOREL Communication /Conference Management T.: Chantal.Benis@imag.fr Contact(s): Philipp RITTER, p.ritter@mx.uni saarland.de Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr

54 Pg. 53 Circuit Gallery Title: A Dynamic Voltage Accuracy Frequency Scalable Convolutional Neural Network Processor in 28nm FDSOI. Inst.: KU Leuven Run & Topcell name: S28I16_1cnn_chip Title: ASTRE: Front End ASIC for the readout of TPC or Silicon detectors Inst.: CEA / IRFU / SEDI Run & Topcell name: A35C16_2ASTRE Publication(s): B. Moons, R. Uytterhoeven, W. Dehaene, M. Verhelst, "ENVISION: a 0.3 to 10 TOPS/W subwordparallel, computational accuracy voltage frequencyscalable convolutional neural network processor in 28nm FDSOI", ISSCC dig. of tech. papers, 2017.B. Moons, R. Uytterhoeven, W. Dehaene, M. Verhelst, "ENVISION: a 0.3 to 10 TOPS/W subword parallel, computational accuracy voltage frequency scalable convolutional neural network processor in 28nm FDSOI", ISSCC dig. of tech. papers, Contact(s): Bert Moons, Marian Verhelst, bert.moons@esat.kuleuven.be; marian.verhelst@esat.kuleuven.be Title: A 128x8 massive MIMO precoder and detector. Inst.: Lund University, Department of Electrical and Information Technology Run & Topcell name: S28l15_2eitmay15a_massiveMIMO Publication(s): AGET, the GET front end ASIC, for the readout of the Time Projection Chambers used in nuclear physic experiments, Anvar, S; Baron, P.; Blank, B.; Chavas, J.; Delagnes, E.; Druillole, F.; Hellmuth, P.; Nalpas, L.; Pedroza, J.L.; Pibernat, J.; Pollacco, E.AGET, the GET front end ASIC, for the readout of the Time Projection Chambers used in nuclear physic experiments, Anvar, S; Baron, P.; Blank, B.; Chavas, J.; Delagnes, E.; Druillole, F.; Hellmuth, P.; Nalpas, L.; Pedroza, J.L.; Pibernat, J.; Pollacco, E. Contact(s): Pascal Baron, pascal.baron@cea.fr Title: Readout electronics for Time and Energy measurements in medicla imaging Inst.: LPC Clermont Ferrand, CNRS/IN2P3 Run & Topcell name: A35C16_1xtract Contact(s): Laurent ROYER, royer@clermont.in2p3.fr C Chantal BÉNIS MOREL Communication /Conference Management T.: Chantal.Benis@imag.fr Kholdoun TORKI Technical Director T.: Kholdoun.Torki@imag.fr Publication(s): ISSCC 2016 "A 60pJ/b 300Mb/s Massive MIMO Precoder Detector in 28nm FD SOI"ISSCC 2016 "A 60pJ/b 300Mb/s Massive MIMO Precoder Detector in 28nm FD SOI" Contact(s): Stefan Molund, stefan.molund@eit.lth.se

55 Pg. 54 Contact information Contact information Staff members and their current responsabilities. Contact details of staff members: Isabelle AMIELH Chief Administrative Officer Tel Isabelle.Amielh@imag.fr Patricia CHASSAT Secretariat & Shipments Tel Patricia.Chassat@imag.fr Sylvaine EYRAUD Design Kit & MPW User Relationship Tel Sylvaine.Eyraud@imag.fr Olivier GUILLER R&D Engineer 3D IC MPW Runs Tel Olivier.Guiller@imag.fr Azedine MANAA MPW Run Engineer ams & MEMS Tel Azedine.Manaa@imag.fr Joëlle PARRAU Accountant Tel Joelle.Parrau@imag.fr Kholdoun TORKI Technical Director Tel Kholdoun.Torki@imag.fr Chantal BÉNIS MOREL Communications Tel Chantal.Benis@imag.fr Jean Christophe CRÉBIER Director Tel Jean Christophe.Crebier@imag.fr Mikael GUY Web developer Tel mikael.guy@imag.fr Lyubomir KERACHEV R&D Engineer Adv. packaging & MPW Runs Tel Lyubomir.Kerachev@imag.fr Jean François PAILLOTIN MPW Run Manager: STMicroelectronics Tel Jean Francois.Paillotin@imag.fr Christelle RABACHE Design Kit Support and MPW Run Engineer Tel Christelle.Rabache@imag.fr Romain VERLY MPW Run Assistant Tel Romain.Verly@imag.fr Grenoble view