Unit 4. Sequential Systems
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1 Unit 4. equential ystems Contents Basic Concepts Latches and flip-flops egisters Counters Bibliography igital fundamentals. Thomas Floyd. Prentice-Hall. igital esign. M. Morris Mano. Prentice-Hall Introduction to igital Logic esign. ohn P. Hayes. Addison-Wesley
2 Basic concepts equential circuit. Circuit in which the outputs in a concrete instant are function of the inputs in that instant and the state of the circuit, i.e., they store information Therefore a sequential system is formed by two different blocks: a combinational system to process information and a memory system to store it. ENTAA istema combinacional ALIA istema de memoria (biestables) Generally, feedback circuits are present in sequential systems. 2
3 Latches and flip-flops (I) Information is stored in binary, and the basic memory elements are latches and flip-flops which store just one bit of information. They are elementary logical circuits that can remain in one of the two possible states (=0 or =1) and switch among them depending on the triggering inputs. There are many types, but the general scheme is: Entradas de disparo Estado alidas 3
4 Latches and flip-flops (I) (II) Classification: epending on triggering method: - -K T epending on triggering synchronization: ynchronous. witching among states occurs in synchrony with a clock signal Asynchronous. witching among states can occurs in any moment; it just depend on the triggering inputs. epending on the form of the triggering signal: Level-triggered. Triggering and change of state occurs when a low or high level is detected in the inputs. Edge-triggered (synchronous flip-flops): Triggering and change of state occurs just when the clock changes from low to high (rising edge) or from high to low (falling edge). 4
5 Latches and flip-flops (I) (III) - NO Tabla de excitación t t t t I ==1: is not determined. Not valid input 5
6 Latches and flip-flops (I) (IV) -NAN Tabla de excitación t t t I t ==0: is not determined. Not valid input 6
7 Latches and flip-flops (I) (V) - synchronous Level-triggered 7
8 Latches and flip-flops (I) (VI) - synchronous with asynchronous inputs CL and P CL P Tabla de excitación Pr Cl t X X X X X X X X X X t X 8
9 Latches and flip-flops (I) (VII) - Master-lave It solves timing problems that can give rise to wrong outputs by reducing the switching moment of the flip-flop to transitions of the clock (rising or falling edges) Example: falling edge MAETO ECLAVO ' > 9
10 Latches and flip-flops (I) (VIII) Asynchronous -K Flip-flop Like -, but removing undetermined situations using feedback ~ y K ~. K Tabla de excitación t K t t t t K K 10
11 Latches and flip-flops (I) (IX) ynchronous -K Flip-flop Level-triggered K K Edge-triggered K MAETO ECLAVO K > K ' 11
12 Latches and flip-flops (I) (X) T flip-flop T T > > K Tabla de excitación T t t+1 0 t 1 t 12
13 Latches and flip-flops (I) (XI) latch (level-triggered) Tabla de excitación t t+1 X 0 t 1 flip-flop (edge-triggered) > Tabla de excitación t t+1 > 13
14 egisters (I) egister: Circuit that can store binary information, generally a word (n bits: 4, 8, 16, 32, 64 ). It is formed by flip-flops connected by different ways depending on the type: Basic types: toring registers hift registers Counters 14
15 egisters (II) toring egister: it works like a small memory; just stores bits. Operations: read and write epending on the triggering: Latches Flip-flops E 3 E 2 E 1 E MB... LB 15
16 egisters (III) hift register. Besides storing information, it can shift it by moving bits between connected flip-flops or latches Types (depending on input-output) erial Input - erial Output ENTAA E ATO EIE / n bits ALIA E ATO EIE erial Input - Parallel output ENTAA E ATO EIE /P n bits ALIA E ATO PAALELO Parallel Input - erial Output ENTAA E ATO PAALELO P/ n bits ALIA E ATO EIE Parallel Input - Parallel output ENTAA E ATO PAALELO P/P n bits ALIA E ATO PAALELO 16
17 egisters (IV) Types (depending on shifting): Open ight shift E Left shift E ing ight shift E Left shift E 17
18 egisters (V) hift register with serial input serial output E E 18
19 egisters (VI) hift register with serial input parallel output ALIA PAALELO ENTAA EIE E E
20 egisters (VII) hift register with parallel input serial output ENTAA PAALELO E 0 E 1 E 2 E 3 Control (/L) P P P P ALIA EIE 20
21 egisters (VIII) hift register with parallel input - parallel output CONTOL E 0 E 1 E 2 E 3 ENTAA EIE
22 egisters (IX) Universal shift register C1 C0 Operation 0 0 Keeps the state. No op 0 1 ight shift 1 0 Left shift 1 1 Load A B C C 1 C 0 I LI 22 A B C
23 Counters (I) Circuit that counts and remembers the number of pulses it receives from an external signal or clock It is formed by a chain of flip-flops whose n outputs represent the count in binary Classifications: ynchronism: Asynchronous / synchronous Counting way: Up / own Maximum count: Binary / N-modulus 23
24 Counters (II) Asynchronous up binary counter A B C '1' K '1' K '1' K '1' K f A f/2 B f/4 C f/ f/
25 Counters (III) Asynchronous down binary counter A B C '1' '1' '1' '1' K K K K f A f/2 B f/4 C f/ f/16 25
26 Counters (IV) ynchronous up binary counter A B C '1' K K K K 26
27 Counters (V) 10-modulus counter N (Up, Asynchronous) C B A Puesta a cero del contador etección del 10 A B C '1' K '1' K '1' K '1' K 27
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