ENGR 303 Introduction to Logic Design Lecture 10. Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

Transcription

1 ENG 33 Introduction to Logic esign Lecture r. Chuck Brown Engineering and Computer Information cience Folsom Lake College

2 Outline for Todays Lecture equential Circuits Latches egisters Flip-Flops ENG 33 <2>

3 equential Circuits Outputs of sequential logic depend on current and prior input values it has memory. ome definitions: tate: all the information about a circuit necessary to explain its future behavior Latches and flip-flops: state elements that store one bit of state ynchronous sequential circuits: combinational logic followed by a bank of flip-flops ENG 33 <3>

4 equential Circuits Give sequence to events Have memory (short-term) Use feedback from output to input to store information ENG 33 <4>

5 tate Elements The state of a circuit influences its future behavior tate elements store state Bistable circuit Latch Latch Flip-flop ENG 33 <5>

6 Bistable Circuit Fundamental building block of other state elements Two outputs:, No inputs I2 I I I2 ENG 33 <6>

7 Bistable Circuit Analysis Consider the two possible cases: = : then =, = (consistent) I I2 = : then =, = (consistent) I I2 tores bit of state in the state variable, (or ) But there are no inputs to control the state ENG 33 <7>

8 (et/eset) Latch Latch N N2 Consider the four possible cases: =, = =, = =, = =, = ENG 33 <8>

9 Latch Analysis =, = : then = and = N N2 =, = : then = and = N N2 ENG 33 <9>

10 Latch Analysis =, = : then = and = et the output N N2 =, = : then = and = eset the output N N2 ENG 33 <>

11 Latch Analysis =, = : prev = prev = then = prev N N N2 N2 =, = : then =, = N N2 ENG 33 <>

12 Latch Analysis =, = : prev = prev = then = prev Memory! N N N2 N2 =, = : then =, = Invalid tate NOT ENG 33 N N2 <2>

13 Latch ymbol stands for et/eset Latch tores one bit of state () Control what value is being stored with, inputs et: Make the output ( =, =, = ) eset: Make the output ( =, =, = ) Latch ymbol ENG 33 <3>

14 Latch Two inputs:, : controls when the output changes (the data input): controls what the output changes to Function When =, passes through to (transparent) When =, holds its previous value (opaque) Avoids invalid case when NOT ENG 33 Latch ymbol <4>

15 Latch Internal Circuit X ENG 33 <5>

16 Latch Internal Circuit X X prev prev Verilog module latch (input clk, d, output reg q); (clk, d) if (clk) q <= d; endmodule ENG 33 <6>

17 Flip-Flop Inputs:, Function amples on rising edge of When rises from to, passes through to Otherwise, holds its previous value changes only on rising edge of Called edge-triggered Activated on the clock edge ENG 33 Flip-Flop ymbols Verilog module flop (input clk, d, output reg q); (posedge clk) q <= d; endmodule <7>

18 Flip-Flop Internal Circuit Two back-to-back latches (L and L2) controlled by complementary clocks When = L is transparent L2 is opaque passes through to N When = L2 is transparent L is opaque N passes through to L N L2 Thus, on the edge of the clock (when rises from ) passes through to ENG 33 <8>

19 Latch vs. Flip-Flop (latch) (flop) ENG 33 <9>

20 Latch vs. Flip-Flop (latch) (flop) ENG 33 <2>

21 egisters 3: 4 4 3: 2 2 Verilog module register (input clk, input [3:] d, output reg [3:] q); (posedge clk) q <= d; endmodule 3 3 ENG 33 <2>

22 Enabled Flip-Flops Inputs:,, EN The enable input (EN) controls when new data () is stored Function EN = : passes through to on the clock edge EN = : the flip-flop retains its previous state EN Internal Circuit ymbol EN Verilog module flopenr (input clk, reset, en, input [3:] d, output reg [3:] q); // asynchronous reset (posedge clk, posedge reset) if (reset) q <= 4 b; else if (en) q <= d; endmodule ENG 33 <22>

23 esettable Flip-Flops Inputs:,, eset Function: eset = : is forced to eset = : flip-flop behaves as ordinary flip-flop ymbols eset r Verilog module flopenr (input clk, reset, en, input [3:] d, output reg [3:] q); // asynchronous reset (posedge clk, posedge reset) if (reset) q <= 4 b; else if (en) q <= d; endmodule ENG 33 <23>

24 esettable Flip-Flops Two types: ynchronous: resets at the clock edge only Asynchronous: resets immediately when eset = Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop ynchronously resettable flip-flop? ENG 33 <24>

25 esettable Flip-Flops Two types: ynchronous: resets at the clock edge only Asynchronous: resets immediately when eset = Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop ynchronously resettable flip-flop? Internal Circuit eset ENG 33 <25>

26 ettable Flip-Flops Inputs:,, et Function: et = : is set to et = : the flip-flop behaves as ordinary flip-flop ymbols et s ENG 33 <26>