LEC-23: Scan Testing and JTAG

Transcription

1 LEC-23 Preliminries 294 LEC-23: Sn Testing n JTAG Leture Notes Setions: Universit of Wterloo Dept of Eletril n Computer Engineering E&CE 427 Digitl Sstems Engineering 2002-Winter Sheule wk wk-05 wk-06 wk-07 wk-08 wk-09 wk-10 wk-11 wk-12 wk-13 VHDL Design n Optimition Funtionl Vlition Performne Anlsis, Preition, n Optimition Design Wrpup IRS n Holi (No Leture or Tutoril) Timing Anlsis Power Anlsis n Reution Power Reution; Fults Fult Detetion; Built-In Self Test (BIST) Sn Testing (JTAG); Review Purpose n List of Conepts The purpose of this leture is to onnet the theor of ing n bilit to the urrent tehniques of sn ing n the IEEE Stnr (k JTAG). sn ing sn hin ing proeure time to run bounr sn ing JTAG IEEE 1149 length of time to o sn hrwre to o sn ing

2 LEC-23: 6.5 SCAN TESTING IN GENERAL (SMITH 14.6) Sn Testing in Generl (Smith 14.6) Struture n Behviour of Sn Testing t_in(3) et_in(3) nother #0 t_in(2) t_in(1) et_in(2) et_in(1) nother #1 nother sn hin 0 sn hin 1 et nother t_in(0) et_in(0) Norml Ciruit Ciruit with Sn Chins Ae Sn Chins Ciruitr in Norml n Sn Moe Norml Moe Sn Moe Sn in Opertion nother sn hin 0 sn hin 0 Ciruit with sn hins et nother previous results0 urrent vetor0 previous results1 urrent vetor1 urrent results0 next vetor0 urrent results1 next vetor1 Behviour of sn ing

3 LEC-23: Sn Chins Sn in Opertion with Exmple Ciruit b b Ciruit Ciruit with sn r b b Strt Loing Test Vetor (Lo ) Lo b b Lo Lo

4 LEC-23: Sn Chins Run Test Vetor Test Vlues Propgte ( +) Flop-In Result, Strt (Un)loing Test Vetor ( +, + ) Continue (Un)loing Test Vetor ζ ζ ψ ψ ζ ζ ζ ( +, + ) Finish (Un)loing Test Vetor Run Next Test Vetor ( +, + )

5 LEC-23: 6.6 BOUNDARY SCAN Summr of Sn Testing Aing sn r 1. Registers roun to be e re groupe into sn hins 2. Reple eh flop with mux + flop 3. Flops n muxes wire together into sn hins 4. Eh sn hin is onnete to eite I/O pins for loing n unloing vetors Running vetors 1. Put sn hin in sn moe 2. Lo in vetor (one element of vetor per lok le) 3. Put sn hin in norml moe 4. Run for one lok le lo result of into flops 5. Unlo results of urrent vetor while simultneousl loing in next vetor (one element of vetor per lok le) Exmple: Time to Test Chip A 800MH hip hs sn hins of length 20,000 bits, 18,000 bits, 21,000 bits, 22,000 bits, n two of 15,000 bits. 500,000 vetors re use for eh sn hin. The s re run t 80% of full spee. Question: Clulte the totl time. Answer: We n lo n unlo ll of the sn hins t the sme time, so time will be limite b the longest (22,000 bits). For the first vetor, we hve to lo it in, run the for one lok le, then unlo the result. Loing the seon vetor is one while unloing the first. 6.6 Bounr Sn TimeTot ClokPerio MxLengthVe NumVes MxLengthVe ses Bounr sn originte s tehnique to wires on printe bors (PCBs). Gol ws to reple be-of-nils stle ing with tehnique tht woul work for high-ensit PCBs (lots of smll wires lose together) Now use to both bors n hip internls. Use both on bounries (I/O pins) n internl flops. Stnrie b IEEE (1149) n previousl b JTAG:

6 LEC-23: Bounr Sn Histor require signls (Sn Pins: TDI, TDO, TCK, TMS) 1 optionl signl (Sn Pin: TRST) protool to onnet to er n other s stte mhine to rive r on hip Bounr Sn Desription Lnguge (BSDL): struturl lnguge use to esribe whih fetures of JTAG supports JTAG r now ommonl built-into FPGAs n ASICS, or prt of ell-librr. Rrel is JTAG ustom-built s prt of lrger prt. So, ou ll probbl be hoosing n using JTAG s, not onstruting new ones. Using JTAG r is usull one b giving esription of our printe bor (PCB) n the JTAG omponents on eh hip (in BSDL) to genertion softwre. The softwre then genertes sequene of JTAG ommns n t tht n be use to the wires on the bor for opens n shorts Bounr Sn Histor 1985 JETAG: Joint Europen Test Ation Group 1986 JTAG (North Amerin ompnies joine) 1990 JTAG 2.0 forme bsis for IEEE 1491 Test ess port n bounr sn rhiteture Sn Pins TDI t input: input vetor to hip TDO t output: output result of TCK lok: lok signl tht runs on TMS moe selet: ontrols sn stte mhine TRST reset (optionl): resets the sn stte mhine hip BSR hip sn registers TDI ontrol BR TDO norml input pins norml output pins Instrution Deoer IR IRC IRC TDI TCK TMS ontrol TDO TCK TMS IDCODE TAP Controller

7 LEC-23: TAP Controller Sn Registers n Cells Bsi Builing Bloks TDR Test t register The bounr sn registers on hip DR Fig 14.2 Dt register ell Often use s Bounr sn ell () JTAG Components Fig 14.8 Top level igrm BSR Fig 14.5 Bounr sn register A hin of bounr sn ells (s) Fig 14.2 Bounr sn ell Connets externl input n sn signl to internl. Ats s wire between externl input n internl in norml moe. BR Fig 14.3 Bpss-register ell Allows iret onnetion from TDI to TDO. Ats s wire when exeuting BY- PASS instrution. IDCODE Devie ientifition register t register to hol mnufturer s nme n hip ientifier. Use in IDCODE instrution. IR ell Fig 14.4 Instrution register ell Cells re ombine together s shift register to form n instrution register (IR) IR Fig 14.6 Instrution register Two or more IR ells in row. Hols t tht is shifte in on TDI, sens this t in prllel to instrution eoer. IDeoe Tble 14.4 Instrution eoer Res instrution store in instrution register (IR) n sens ontrol signls to bpss register (BR) n bounr sn register (BSR) Fig 14.7 TAP Controller Stte mhine tht, together with instrution eoer, ontrols the sn r Sn Instrutions This the set of require instrutions, other instrutions re optionl. EXTEST Test bor-level interonnet. Drive output pins of hip with hr-oe vetor. Smple results on inputs. SAMPLE Smple result t PRELOAD Lo vetor BYPASS Diretl onnet TDI to TDO. This is use when severl hips re is hine together to skip loing t into some hips. IDCODE Output mnufturer n prt number TAP Controller The TAP ontroller is require to hve 16 sttes n obe the stte mhine shown in Fig 14.7.

8 LEC-23: Other esriptions of JTAG/IEEE Other esriptions of JTAG/IEEE Texs Instruments introutor seminr on IEEE Texs Instruments intermeite seminr on IEEE Sun mirosparc-iiep sn-ing oumenttion Intelliteh JTAG overview: Atel s JTAG esription: Desription of JTAG support on Motorol Colfile miroproessor: Summr n Conlusions on Testing Fults Fults re mnufturing efets. Common ourenes re opens (wire is broken) n shorts (two wires re onnete together). When working with fults, we work with wire segments, not signls. In the below, there re 8 ifferent wire segments (L1 L8). Eh wire segment orrespons to logill istint fult lotion. All phsil fults on segment ffet the sme set of signls, so the re groupe together into logil fult. If signl hs fnout of 1, then there is one wire segment. A signl with fnout of n, where n 1, hs n 1 wire segments one for the soure signl n one for eh gte of fnout. L1 For signl b in the here, the fnout is 2, so there re three wire segments (L2, L4, n L5). Although there re mn ifferent b behviours tht fults n le to, the simple moel of single-stuk-tfults hs proven ver pble of fining rel fults in rel s. single ssume tht t most wire segment in hs fult. stuk-t-0 (s@0) ssume tht the fult behviour is tht the segment is hrwire to 0. stuk-t-1 (s@1) ssume tht the fult behviour is tht the segment is hrwire to Testing Fults re etete b stimulting s (rel, mnufture, not simultion!) with -vetors n heking tht rel gives orret output. Stnr prtie in ing is to s for single stuk-t fults. Mthemtis n empiril eviene emonstrte tht ing for single stuk-t fults will lso etet mn other tpes of fults n will often etet multiple fults. Some fults re unetetble. Unetetble stuk-t fults re lote in reunnt prts of. These reunnt prts re e to prevent timing hrs. As suh, stuk-t fult in reunnt r will not ffet the ste stte behviour of the, but oul llow timing glithes to our. b L2 L3 L4 L5 L6 L7 L8

9 LEC-23: Testing 302 If hs 100% single stuk-t fult overge with suite of vetors, then eh stuk-t fult in the n be etete b one or more vetors in the suite. This lso mens tht the hs no unetetble fults, n hene, no reunnt r. It is possible tht hieving 100% overge for single stuk t fults will llow efetive hips to pss if the hve fults tht re not stuk-t-1 or stuk-t-0, or if the hve multiple fults. I think, but hven t seen proof, tht hieving 100% single stuk-t overge will etet ll ombintions of multiple stuk-t fults. But, if ou o not hieve 100% overge, then stuk-t fult tht ou ren t ing for n msk (hie) fult tht ou re ing for. There re two ws to generte vetors n hek result: built-in s n sn ing. Both require: generte vetors overie norml tpth to sen -vetors, rther thn norml inputs, s inputs to flops ompre outputs of flops to expete result Sn Testing In sn ing, the genertion n heking re one off-hip. This hs the vntge of flexibilit n reue on-hip hrwre, but inreses the length of time require to run. We wnt to iniviull rive n re ever flop in the. Even without using n I/O pins for ing purposes, hips re lre I/O boun, so sn-ing must be ver frugl in its use of pins. Flops re onnete together in sn hin with one input pin n one output pin. If the length (number of flops) of sn hin is n, then it tkes 2n 1 lok les to run single : n lok les to sn in the vetor, 1 lok le to exeute the vetor, n n les to sn out the results. One the results re snne out, the n be ompre to the expete results for orretl working. If we run 2 or more s (n hips generll re subjete to hunres of thousns of s), then we spee things up b snning in the next vetor while we sn out the previous result. SnLength = number of flip flops in sn hin NumVetors = number of vetors in suite TimeSn = number of lok les to run suite = NumVetors SnLength 1 SnLength To fin vetor tht will etet fult: 1. buil Boolen eqution (or Krnugh mp) of orret 2. buil Boolen eqution (or Krnugh mp) of fult 3. ompre equtions (or Krnugh mps), regions of ifferene represent vetors tht will etet fult Beuse it tkes so muh time to perform sn, reuing the number of vetors tht re neee is ver importnt. fult1 omintes fult2 is efine s: n vetor tht will etet fult1 will lso etet fult2. Summr of Tehnique to Fin n Orer Test Vetors: 1. ientif ll possible fults 2. gte ollpsing 3. noe ollpsing 4. intelligent ollpsing

10 LEC-23: Testing fult omintion 6. etermine require vetors 7. hoose miniml set of vetors to etet remining fults 8. orer vetors bse on number of fults etete (NOTE: when iterting through this step, nee to tke into ount fults etete b erlier vetors) Built-In Self Test (BIST) With built-in self, the s itself. Both vetor genertion n heking re one using liner feebk shift registers (LFSRs). The figure below shows n LFSR tht genertes ll possible 3-bit vetors exept 000. (An n bit LFSR tht genertes 2 n 1 ifferent vetors is lle mximl-length LFSR.) Assume tht reset initilies the to 111. The sequene tht is generte is: 111, 011, 001, 100, 010, 101, 110. This sequene is repete, so the number fter 110 is 111. Eh liner feebk shift register hs hrteristi polnomil, tht orrespons to the behviour of the signl tht is the input to the first flip-flop in the shift register. The exponents in the polnomil orrespon to the el x 0 is the input to the shift register, x 1 is the output of the first flip-flop, x 2 is the output of the seon, et. The oeffiient is 1 if there s feebk tp from the output of the flop. Cheking is one b builing one signture nler for eh signl e. The returns true if the signl genertes the orret sequene of outputs for the vetors. Doing this with omplete ur woul require storing 2 n bits of informtion for eh output for with n inputs. This woul be s expensive s the originl. So, BIST uses mthemtis similr to error orretion/etetion to pproximte whether the outputs re orret. This tehnique is lle signture nlsis n originte with Hewlett-Pkr in the 1970s. The heking is one with n LFSR, similr to the BIST genertion. The heking is esigne to output 1 t the en of the sequene of 2 n 1 results if the sequene of results mthes the orret. We oul o this with n LFSR of 2 n 1 flops, but s si before, this woul be t lest s expensive s upliting the originl. The heking LFSR is esigne similrl to hshing funtion or prit heking. If it returns 0, then we know tht there is fult in the. If it returns 1, then there is probbl not fult in the, but we n t s for sure. There is treoff between the ur of the nler n it s re. The more urte it is, the more flip flops re require. q2 q1 q0 The LFSR here reognies the sequene 1, 0, 1, 1, 1, 0, 0: output from It oul be use, in onjuntion with the mximl-length LFSR bove, to etet fults in tht, when stimulte with the sequene with the sequene 111, 011, 001, 100, 010, 101, 110; outputs the sequene 1, 0, 1, 1, 1, 0, 0. q2

11 LEC-23: Sn vs Self Test Sn vs Self Test Sn less hrwre slower well efine overge vetors re es to moif Self Test more hrwre fster ill efine overge vetors re hr to moif