No feedback between inputs and outputs combinational What is charge sharing?

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1 EEC 1 Lab dickrp/eecs1/ Teacher: Office: Phone: Cellphone: 17-G EEC dickrp@eecs.umich.edu HW engineers GI: Can assume first stage is like an inverter, then experiment. Myung-Chul Kim mckima@umich.edu A few simulation ru are fine. Not expecting exhaustive search. Capacitance of first gate? Can assume that γ = 1. If not clear, discussion list today so Mr. Kim and I know to make more suggestio. Typical Current raw 1 sec Heartbeat beats per sample W engineers ampling and adio Tramission 9-1 ma 9 Current (ma) 7 adio eceive for Mesh Maintenance - ma Heartbeat 1 - ma Low Power leep. -. ma 1 erive and explain. Time (seconds) 1 CMO IBM E9 Power deity (Watts/cm) 1 Prescott Jayhawk(dual) Bipolar T-ex Mckinley quadro Fujitsu VP IBM GP IBM 9 IBM Y NTT IBM Z9 Fujitsu M-7 Pentium IBM Y7 Pulsar IBM 9 Vacuum IBM IBM Y CC Cyber IBM 1 IBM 1 Fujitsu M IBM 19 IBM 7 IBM Y Apache Merced Pentium II(IP) Year of announcement eview Combinational vs. sequential logic No feedback between inputs and outputs combinational What is charge sharing? Outputs a function of the current inputs, only Why are there two different expressio for the voltage to which Vout settles? Feedback sequential Is leakage a significant factor in charge sharing? How can it be prevented? flip flops clock What is volatile memory? What is non-volatile memory? What is static memory? plain old combinational logic q What is dynamic memory? erive and explain. equential logic Flip-flop introduction Outputs depend on current state and (maybe) current inputs Next state depends on current state and input tores, and outputs, a value. For implementable machines, there are a finite number of states ynchronous Puts a special clock signal in charge of timing. Allows output to change in respoe to clock traition. More on this later. tate changes upon clock event (traition) occurs Timing and sequential circuits Asynchronous tate changes upon inputs change, subject to circuit delays 7 Introduction to sequential elements Feedback and memory Feedback and memory. Memory. Latches. Feedback or physical state are the root of memory. Can compose a simple loop from inverters. However, there is no way to switch the value. 9

2 Bistability TG and NOT-based memory Can break feedback path to load new value However, potential for timing problems 11 One-bit volatile cell eset/set latch Can break feedback path to load new value. How can this be made more efficient? esize traistors, remove traistors, use state? 1 1 eset/set timing latch state diagram eset Hold et eset et ace Utable state Utable state output= input= Clocking terms Gated latch Input Clock Clock ising edge, falling edge, high level, low level, period etup time: Minimum time before clocking event by which input must be stable (T U ) Hold time: Minimum time after clocking event for which input must remain stable (T H ) Window: From setup time to hold time ENB 17 1

3 Gated latch Memory element properties ENB Type Inputs sampled Outputs valid Unclocked latch Always LFT Level-seitive latch Clock high LFT (TU to TH) around falling clock edge Edge-triggered flip-flop Clock low-to-high traition elay from rising edge (TU to TH) around rising clock edge 19 Timing for edge and level-seitive latches Active high traparent Active low traparent Positive (rising) edge Negative (falling) edge edge level Latch timing specificatio Latch timing specificatio Example, negative (falling) edge-triggered flip-flop timing diagram Minimum clock width, T W Usually period / Low to high propegation delay, P LH High to low propegation delay, P HL Worst-case and typical T w C» 7 1 C» 1» 7 1» 1 7 FF timing specificatio FF timing specificatio Example, positive (rising) edge-triggered flip-flop timing diagram Minimum clock width, T W Usually period / Low to high propagation delay, P LH High to low propagation delay, P HL T w 1 7

4 latch states Falling edge-triggered + + Notes utable Use two stages of latches When clock is high First stage samples input w.o. changing second stage econd stage holds value When clock goes low First stage holds value and sets or resets second stage econd stage tramits first stage + = One of the most commonly used flip-flops Edge triggered timing clocked latch Positive edge t riggered FF torage element in narrow width clocked systems. angerous. Fundamental building block of many flip-flop types. Negative edge t riggered FF 1 Toggle (T) flip-flops Minimizes input wiring. imple to use. Common choice for basic memory elements in sequential circuits. tate changes each clock tick Useful for building counters Can be implemented with other flip-flops with XO feedback Asynchronous inputs chmitt triggers How can a circuit with numerous distributed edge-triggered flip-flops be put into a known state? Could devise some sequence of input events to bring the machine into a known state. Complicated. low. Not necessarily possible, given trap states. Can also use sequential elements with additional asynchronous reset and/or set inputs. A A traition B B 7

5 eason for gradual traition ebouncing A logic stage is an C network Whenever a traition occurs, capacitance is driven through resistance Coider the implementation of a CMO inverter Mechanical switches bounce! What happe if multiple pulses? Multiple state traitio Need to clean up signal 9 ebouncing Latch and flip-flop equatio V chmidt trig. C = + + = 1 T + = T -1.e- -.e-.e+.e- 1.e- 1.e- T (s) 1 Upcoming topics assignment equential circuits. Theoretical foundatio for sizing. November, Monday: Lab. November, Tuesday: ead ectio 1.1 in J. abaey, A. Chandrakasan, and B. Nikolic. : A esign Perspective. Prentice-Hall, second edition,. November, Tuesday: ead ectio 1. in J. abaey, A. Chandrakasan, and B. Nikolic. : A esign Perspective. Prentice-Hall, second edition,. pecial topic: ubthreshold circuit applicatio Megan and Tyler.