Emerging Memory Technologies

Transcription

1 Report No. FI-NVM-EMT-1209 By: Josef Willer, Gregory Wong December 2009

2 2009 Forward Insights. All Rights Reserved. Reproduction and distribution of this publication in any form in whole or in part without prior written permission is prohibited. The information contained herein has been obtained from sources believed to be reliable. Forward Insights does not guarantee the accuracy, validity, completeness or adequacy of such information. Forward Insights will not be liable for any damages or injuries arising from the use of such information including, without limitation, errors, omissions or inadequacies in the information contained herein or for the interpretation thereof. The opinions expressed herein are subject to change without notice. Forward Insights December 2009 ii

3 Contents Emerging Memory Technologies CONTENTS...III LIST OF FIGURES... VII LIST OF TABLES... IX INTRODUCTION EXECUTIVE SUMMARY MAINSTREAM MEMORY TECHNOLOGIES Introduction The Memory Hierarchy SRAM Concept Scaling Challenges Scaling Options DRAM Concept Technology Evolution Scaling Challenges Scaling Options NOR Flash Concept Technology Evolution Scaling Challenges Scaling Options NAND Flash Concept Technology Evolution Scaling Challenges Scaling Options NROM Concept Technology Evolution Scaling Challenges Scaling Options Summary EMERGING MEMORY TECHNOLOGIES Floating Body Cell Forward Insights December 2009 iii

4 Phase Change Memory MRAM Spin-Torque MRAM Racetrack Memory FRAM RRAM Programmable Metallization Cell Nanocrystal Memory Carbon Nanotubes Memristor Probe Storage D Integrated High Density Arrays D OTP Memory D Reprogrammable Memory Concept Vertical SONOS NAND OUTLOOK Charge Trap Flash (SONOS NAND) Floating Body Cell Memory FRAM MRAM PMC Silicon Nanocrystal Memory ST-MRAM Phase Change Memory RRAM Stackable NAND Stackable Cross Point Memory (3D Memory) COMPANIES DS Adesto Technologies AMD Avalanche Technology Axon Technologies Corporation BAE Systems Forward Insights December 2009 iv

5 Contour Semiconductor Crocus Technology Cypress Semiconductor Elpida Everspin Technologies Freescale Semiconductor Fujitsu Grandis Hitachi Honeywell HP Hynix IBM ITRI IMEC Infinite Memories Innovative Silicon Intel Corp Macronix International MagSil Matsushita Micron Technology Nanosys Nantero NEC Numonyx NuPGA NVE NXP Semiconductors Oki Ovonyx QS Semiconductor Ramtron Rohm Forward Insights December 2009 v

6 Samsung Electronics SanDisk Schiltron Corp Solvay Solexis Spansion Spin Transfer Technologies Spingate Technology STMicroelectronics Symetrix TDK Texas Instruments Thin Film Electronics ASA Toshiba Corp Tower Semiconductor T-RAM Semiconductor TSMC UMC Unity Semiconductor Corp ZettaCore REFERENCES ABOUT THE AUTHORS ABOUT FORWARD INSIGHTS Services Contact Forward Insights December 2009 vi

7 List of Figures Emerging Memory Technologies Figure 1. Memory Hierarchy Figure 2. SRAM Cell Layout Figure 3. 3D SRAM Technology Figure 4. DRAM Cell Figure 5. DRAM Cell Transistor Evolution Figure 6. DRAM Capacitor Evolution Figure 7. DRAM Cell Capacitor Trend Figure 8. Buried Wordline Figure 9. NOR Flash Architecture Figure 10. NOR Flash Program, Erase, Read Figure 11. NOR Flash Technology Evolution Figure 12. Drain Bias Margin Figure 13. 3D NOR Flash Cell Figure 14. Virtual Ground NOR Flash Figure 15. NAND Flash Cell Concept Figure 16. NAND Flash Architecture Figure 17. NAND Cell String Figure 18. NAND Flash Program, Erase, Read Figure 19. NAND Flash Technology Evolution Figure 20. NAND Flash Memory Gap Fill Figure 21. Cross-talk and Coupling Ratio Figure 23. Inter-cell Interference Trend Figure 25. SONOS NAND Figure 26. FinFET Figure 28. NROM Virtual Ground Array Figure 29. NROM Program, Erase, Read Figure 30. NROM Technology Evolution Figure 31. Bit Disturb ( Second Bit Effect ) Figure 32. FinFET, 3D NROM Figure 33 Bit Size Trend Figure 34. Device Characteristics Figure 35. NAND vs. NOR Figure 36. Floating Body Cell Figure 37. Zero Capacitor RAM (Z-RAM) Figure 38. Transistor-addressed PCRAM Figure 40. Numonyx 128Mb PCM Figure 41. PCRAM Scaling: Recent Progress Figure 43. MTJ MRAM Operation Figure 45. SEM cross section of CMOS chip with back end of line MTJ MRAM Figure 46. Cross section micrograph of 4Mb MRAM product Figure 48. Magnetic Racetrack Memory a 3D shift register Figure 49. FRAM Hysteresis Loop and its Operation Figure 50. FRAM Issues Figure 51. FRAM: A Non-volatile RAM Figure 52. RRAM: Recent Status Figure 53. Stackable RRAM Figure 54. Conductive Bridging Mechanism Figure 55. CBRAM Figure 58. Silicon Nanocrystal Process Figure 60. NRAM Forward Insights December 2009 vii

8 Figure 61. Memristor Figure 62. Nanocrossbar circuits at 17nm half-pitch by nano-imprint Figure 63. Probe storage concept: cantilever /MEMs tips store and read data in parallel in recording medium Figure 64. Millipede demonstrator with 4096 tips in 6.4 x 6.4 mm2 array using 10nm indentations Figure 65. Probe Storage Writing Figure 66. Probe Storage Reading Figure 67. High Density Arrays Figure 68. Matrix 3D OTP ROM Figure 69. Cross Point Memory Figure 71. 3D Memory Evolution Figure 72. Vertically Arranged Folded SONOS NAND Strings of BitCost Scalable Technology Figure 73. Density Trend Figure 74. Commercialization Prospects Forward Insights December 2009 viii

9 List of Tables Table 1. Memory Comparison Table 2. Memory Matrix Table 3. Company Matrix Forward Insights December 2009 ix