Analog High Voltage ASIC Design Techniques

Size: px

Start display at page:

Download "Analog High Voltage ASIC Design Techniques"

Gavin Dean
6 years ago
Views:

1 ASIC Technology Symposium 2009 Analog High Voltage ASIC Design Techniques Otto Manck January 20th 2009 Israel Air Force Center, 15 Jabotinski St. Hertzelia

2 Topics Introduction Laws and rules of microelectronics NRE and device costs 0.18µm High Voltage Technologies State of the Art Package Technologies WLCSP, Wafer Level Chip Size Package Stacked Die Packages Special HV Technologies (600V) Open Discussion 2

3 Introduction Moore s Law all 3 years 4 x more components on the same silicon area constant price of unit area silicon is achieved by always smaller line width/geometries e.g , 0.250, 0.180, 0.130, 0.090, 0.065, 0.045, µm and results in always lower chip costs at same functionality always more functionality at the same silicon area What is the state of the art in 2009, in term of performance and costs, with respect to ASIC design? 3

4 Introduction Basic Properties of Microelectronic Scenery I 2. Return of Invest The investment in a new fabrication line has to be earned inside the first 3 years of production. but 2. The cost of a new line grows exponentially with decreasing line width Therefore, under the requirements of constant costs of unit area 3. The output/throughput of a line in terms of silicon area has to grow exponentially achieved by increasing wafer diameter but, last not least 4. The increased silicon area has to be sold 4

5 Introduction Basic properties of Microelectronic Scenery II 2. Mass applications have to make the money Standard devices like memories (in 2008 only 17% of the market) CPU s (better, standard SoC s) ASSP s of consumer telecommunication chip card market (in Billion mobiles ) The bandwagon theory: One has to take advantage from these drivers for special niche applications, called ASIC s 5

6 Introduction (My) ASIC problem/definition (mostly) minor quantities (mostly) restricted development costs/nre s How to find solutions inside reasonable NRE s using the (worldwide offered) technological possibilities so that the result is remarkable better than solutions based on ASSP s/fpga s 6

7 Introduction ASIC problem/definition II The main candidates for improvement IC cost BoM of standard devices against integrated SoC Asic physical size state of the art of packaging technologies (WLCSP) reliability/qualification e.g. 20 years of guaranteed life time unachieved physical performance, e.g. minimum power minimum noise excellent timing (very fast, very accurate etc) Best answer: all properties together 7

8 Introduction ASIC problem/definition III The application areas industrial and automotive need very different requirements compared to consumer, communications and computer with respect to lifetime of the IC (e.g. 10 to 20 years) power consumption/cooling (compared to computers) high voltages ESD/EMC requirements life time of a line Is there a chance for special technologies? Answer: Yes, because of automotive as bandwagon 8

9 ASIC design The mask problem I Any fabrication line with all its options is characterized by a number of masks, e.g. nr. of masks basic CMOS transistors 8 1 supply voltage each metal layer 2 e.g. 5 layers 10 any additional supply 2 4 non volatile OTP 02 Flash 5 SRAM 2 (metallization and via s) (at least 2 voltages) (sometimes) 9

10 ASIC design The mask problem II The different process options are characterized by typically mask levels, CMOS Standard (incl. 5 metal layers, + HV, + NV) 3. Silicon prize Wafer processing results in approx. 50 $ per mask layer (independent from line width, higher equipment cost compensated by higher silicon output) strong tendency to use the smallest possible line width 8. Mask costs Prize proportional to the write time, inside of one generation of lithography machines proportional to no. of structures exponential increase with decreasing line width 10

11 ASIC design Chip prize (bare silicon, yield to be expected > 90 %, not tested, 20 mask layers) minimum prize typical 3 /mm² ( 6 wafer, mm², ~ 400 $ 8 wafer, mm², ~ 800 $) These prizes are achieved today for higher quantities > 1000 Wafers/year. They correspond to the real operating cost of a line, i.e. energy and materials/pure nitrogen gases new lines are offered to much higher prizes With amortization of the invest, any factor is possible (until 3) 11

12 ASIC design Production costs per unit area silicon ( /mm²)) 12

13 ASIC design Mask cost I Technology Full mask set $ $ $ $ Layer No Actual costs of a full mask set (Typical prizes of different manufacturer, time period 2007 and 2008) 13

14 ASIC design Mask cost II First time right Any normal run includes 2 shots a first one nearly 100% running and (after detailled qualification) a second one for the final product. To avoid two times the full mask set, the foundry offers MPW run MLM run (Merged Layers Masks) ( Multi project wafer runs, started in an 1 to 3 month interval at fixed dates). Restricted in maximum silicon area, many customer share the expenses of a full mask set. Typical delivered quantity: 20 to 100 untested chips in a package Prize between and $, area dependent, line width > µm 4 mask layers are integrated in one reticle resulting in ¼ of recticle number and cost. The lithography engine needs correspondingly 4 times more exposure time. In summary only 50 % of NRE (mask) cost 50 % higher wafer prize, but to produced chips 14

15 ASIC design Mask cost III In Summary: The mask costs restrict most of ASIC projects (of lower quantities) to mature technologies (where already the basic steps of amortization are over) Corresponding to Moore s law, all 4 years a shift to the next smaller technology may occur rsp. becomes necessary. In 2009, µm represents this corner technology Typical data (XFAB: XH018 HV, 30 masks) MPW $ (10 mm², 45 samples) MLM $ (Wafer prize $) Full mask set $ (Wafer from 2500 $ to 1300 $, quantity dependent) What can be realized in such a technology? 15

16 ASIC design 16

17 ASIC design 17

18 ASIC design 18

19 High Voltage Technology 19

20 High Voltage Technology 20

21 ASIC design 21

22 Silicon Technology What can be realized in XH018KH111? (0.18µm LP3MOS, DEPL, NVM, HVMOS, 30 masks) The 1 $ device: + 3 mm² analog (input amplifier, 12 Bit ADC, output driver) 3 mm² digital 3 mm² memory (16 kbytes SRAM, 64 kbytes OTP/Flash, add. EEPROM) 9 mm² core area 6 mm² I/O pads 14 mm² total area (300 kgates logic, any 32 Bit CPU, any digital interface) multiplied by 0.05$/mm²: 0.70 $ per good die (Test and package may result in additional 0.60 $) 22

23 Silicon Technology XH018HV 23

24 Silicon Technology The 0.18 µm process the most flexible line ever offered in silicon history allows mixed signal, high voltage, bipolar, non volatile together with optical pindiodes and MEMS elements Flash, OTP and specific EEPROM cells available (becomes a) standard for every foundry ideal for actor/sensor SoC s, connected by a field bus interface With this process, the foundry business becomes independent from the short lifetime/production cycles of the computer/consumer/multi media business. Driven by automotive applications, IC s stay alive for years and a production lifetime in a similar range are visible. 24

25 Silicon Technology 25

26 Silicon Technology 26

27 Packaging Technology Main idea If Moore s law became possible by production of some 1000 dies in parallel, why not introduce similar ideas into the packaging process. Therefore eliminate serial steps (e.g. bonding by Flip Chip Technologies) organize the fabrication so that the well known parallel lithography builds the base of a process step reduce the pad pitch (the distance between two pins of the package) as far as possible (in accordance with the necessary progress of the PCB technology) The result are the well known BGA and QFN packages. The singulation is shifted to the last process step done by a cheap sawing machine. Corresponding to the iron rule of silicon the die price is given by the silicon area the price of a package becomes now a strong function of package size, not by reduced material consumption but by dividing the costs of a process step by the number of produced packages. 27

28 Silicon Technology 28

29 Silicon Technology 29

30 Silicon Technology 30

31 Silicon Technology 31

32 Silicon Technology 32

33 Silicon Technology 33

34 Silicon Technology 34

35 Silicon Technology 35

36 Silicon Technology 36

37 Packaging Technology Summary I: Packaging technology is dominated by the invention of new abbreviations, here perhaps the actual 4 most important one s QFN quad flat no leads BGA ball grid array and WLCSP wafer level chip scale package FCCSP flip chip chip scale package (Any packaging company tries to introduce its own abbreviations) The prize pressure of the consumer products introduces parallel (wafer level) processing into the packaging scenery. Cheap devices are the result, available also at lower annual quantities 37

38 Packaging Technology 38

39 Packaging Technology 39

40 Silicon Technology 40

41 Silicon Technology 41

42 Silicon Technology 42

43 Silicon Technology 43

44 Silicon Technology 44

45 Packaging Technology Summary II: Some prizes (no guaranty) BGA with more than 256 pins, 2 x 2 cm² between 1 and 2 $ QFN 4 x 4 mm², 24 pins 0.05 $ stacked die package always cheaper than the sum of corresponding discrete packages bumping of a wafer typical 100 $ NRE cost of a package between and $ in many cases 45

46 High VoltageTechnology General remarks/rules I The term High voltage looks very flexible, ranging from V Integrated technologies rsp. transistors are available until 600 V Always competition (in terms of BoM) between on chip integration and discrete solutions Below some voltages ( < 100 V) typically one chip solutions Above 100 V, special HV technologies with (stacked chip) package integration High currents only with discrete transistors 46

47 High VoltageTechnology General remarks/rules II Integration of HV silicon on chip until V, currents less 1 A on package LV ASIC + HV ASIC, stacked, using a special HV process (e.g. SOI 600 V) on package LV ASIC + bare standard dies (e,g, special high voltage, high current transistors) different packages Decision e.g. inside the triangle cheapest solution, best performance, smallest size 47

48 High VoltageTechnology General remarks/rules III Power limit under standard condition (natural air cooling, typical air/pcb ratio) 1 W and 1 cm² package area 40 C T over ambient Severe limitation for any modern package (Cooling area has to be extended to the PCB using large copper layers) 48

49 High Voltage Technology Integrated technologies XFAB XDH10 650V 1.0 µm Trench Insulated BCD process 49

50 High Voltage Technology SOI wafer preparation 50

51 High Voltage Technology (V)DMOS (vertical doubled diffused MOS transistor) basic structure ID ID 51

52 High Voltage Technology 52

53 Layout DMOS 40V: Metal 2 Layout: Pitch 13µm LayerLegend: CrossSection: 53

54 High Voltage Technology Three basic break through effects in a MOS structure have to be considered 1. Avalanche effect in pn junction Between two collisions, electron/holes are accelerated by the electrical field so that their energy is higher than the band gap energy to generate a new electron/hole pair. The typical field strength is 1.5 x 105 V/cm. 2. Break through of the Gate Oxid Depending on oxid thickness electrons can tunnel the gate at sufficient high voltages. The effect is used for charge storage in the floating gate for EEPROM but destroys the oxid irreversible at higher currents voltages 3. Punch through The increasing space charge region around the drain region starts to reach the space charge region around source. The channel is no longer blocking in the switch off state. 1) and 3) are non destructive, 2) has to be avoided in any case 1) and 3) depend on the space charge around a pnjunction Solution of Poisson s equation 54

55 High Voltage Transistors, Properties and Layout Ron Resistance of DMOS Transistor RON Resistor (between drain and source) 55

56 High Voltage / Break Through Mechanisms Figure 2.2: Break trough voltage and width of a planar pn junction for typical doping concentrations (of the lower doped 56

57 High Voltage Transistors, Properties and Layout 57

58 High Voltage Technology The silicon limit or the 1dim. pn junction (behaviour) Increasing the breakthrough voltage is only possible by. lowering the (low side) doping concentration (and correspondingly). increasing the width of the space charge region Therefore. the ONresistance (i.e the part dominated by the drain/epi region) is increased.. To maintain the same ONResistance, the transistor width (=area) has to be increased correspondingly Increasing the performance of a power transistor means that silicon area, switching capacitance and costs grow more than linear: the so called silicon limit 58

59 High Voltage Technology Overcoming the silicon limit or the 2dim. pn junction (behaviour) n doped region p+ Na p n p n p doped region p N A = ND n++ 59

60 High Voltage Technology Overcoming the silicon limit 2dim. stripe structure 1dim. pnjunction E Distribution of field strength E x x The stripe structure discharges the space charge region already at relatively low voltages allowing higher blocking voltages allowing much higher doping levels (and lower Onresistance) 60

61 High Voltage Technology CoolMOS data sheet (Infineon) 61

62 High Voltage Technology CoolMOS dat sheet 62

63 High Voltage Technology HV Summary I: Planar technologies available until 650 V and 1 A Above discrete vertical devices Package integration of LV and HV chip Interesting cost, performance and size optimized solutions possible 63

64 High Voltage Technology HV Summary II: The silicon technology needs new killer application The modern HVIC s can directly connected to 240 V Ideal for building/house application The number of chips / human being can be multiplied in comparison to the consumption based on telecommunication and computer/games 64

65 Smart Wire Darwin 65

66 Deep Sub Micron ASICs SmartWire Darwin Industrial Bus Controller Stacked Die Application TSMC 0.25 / XFAB 0.6, industrial non volatile complex mixed signal structure, 250K pure logic gates LV die (0.25um non volatile) RS485 Phy 12 Bit ADC Integrated Voltage Regulator 32k, 2M and 40M Internal Oscillator ESD protection 4k x 16 bit SRAM direct connection to bus cable 16 bit CPU system 16k x16 bit Flash Flash 16k x 16 HV die (0.6um SOI) voltage regulators 16 bit CPU host interface 485+ daisy chain cfg SWD protocol machine uc peripherals SRAM 4k x 16 analog peripherals optional application CPU sensors & actors Temperature range C 66

67 Technologies Following lines have been used during the last two years Elmos 0.8 μm Mixed Signal Automotive Elmos 0.5 μm Mixed Signal Automotive Elmos 0.35 μm Mixed Signal Automotive XFAB 0.6 µm (SOI) Mixed Signal Industrial XFAB 0.6 µm Mixed Signal Industrial XFAB 0.35 μm Mixed Signal Industrial HHNEC 0.35 μm Medical and Industrial ST 0.35 μm Medical TSMC 0.25 μm Automotive non volatile TSMC 0.18 μm Industrial UMC 0.18 μm Research Atmel 0.15 μm Consumer non volatile Freescale 0.25µm SmartMOS Status: February

68 Technologies Projects in 0.18 µm Standard mixed signal lines TSMC 0.18 μm Industrial UMC 0.18 μm Research Combined 0.18µm line (HV, non volatile) 3 PDK are installed XFAB TSMC Fujitsu 2 Projects under development industrial (Fan motor control) housing (Intelligent wire connector) 68

69 End of Presentation Thank you for your attention! Open Discussion 69

70 Confidential 70

24. Scaling, Economics, SOI Technology

24. Scaling, Economics, SOI Technology Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 December 4, 2017 ECE Department, University