THE UNIVERSITY OF TRINIDAD & TOBAGO

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1 THE UNIVERSITY OF TRINI & TOGO FINL SSESSMENT/EXMINTIONS PRIL/MY 2014 ourse ode and Title: igital Systems and Logic esign Programme: Sc omputer Engineering ate and Time: Wednesday 23 rd. pril, 2014 uration: 1:00pm 4:00pm PLESE RE LL INSTRUTIONS REFULLY EFORE YOU EGIN THIS EXMINTION Instructions to andidates 1. This paper has six (6) pages and seven (7) questions. 2. You are required to answer any FIVE (5) questions. 3. Marks for individual parts are shown in square brackets. 4. egin each answer on a new page. 5. Please return the question script with your answer script. Key Examination Protocol 1. Students please note that academic dishonesty (or cheating) includes but is not limited to plagiarism, collusion, falsification, replication, taking unauthorised notes or devices into an examination, obtaining an unauthorised copy of the examination paper, communicating or trying to communicate with another candidate during the examination, and being a party to impersonation in relation to an examination. 2. The above mentioned and any other actions which compromise the integrity of the academic evaluation process will be fully investigated and addressed in accordance with UTT s academic regulations. 3. Please be reminded that speaking without the Invigilator s permission is NOT allowed. Page 1 of 6

2 1a) Write the oolean expression for the function represented by the circuit in Figure Q1. [6] F Figure Q1: Logic diagram for function F b) Simplify the function from (a) and implement the simplified function using XOR and N gates only. [10] c) What is the advantage of the circuit drawn in (b) over that shown in (a)? [2] d) an you identify any disadvantages? [2] 2a) Explain the general operation of a decoder circuit. [5] b) Hence, design a -to-decimal decoder. onsider the unused combinations of the code to be don t care conditions. Show all your working. The code conversion table is provided in ttachment 2-1. [15] Page 2 of 6

3 3. majority circuit is a combinational circuit whose output is equal to 1 if the input variables have more 1s than 0s. The output is 0 otherwise. a) Explain the difference between combinational and sequential logic. [6] b) esign a three-input majority circuit by i) reating the truth table for the circuit. [4] ii) Finding the oolean equations. [6] iii) rawing the logic diagram. [4] 4. Figure Q4 below illustrates the binary multiplication of two two-bit numbers. Figure Q4: inary multiplication of two two-bit numbers a) In a manner similar to Figure Q4, show how two four-bit binary numbers are multiplied. [8] b) Hence, draw the logic circuit that will achieve the multiplication of the two fourbit binary numbers. [12] 5. For the state diagram shown in Figure Q5, a) erive the corresponding state table. [4] b) etermine the characteristic equations using flip-flops. [9] c) raw the resulting logic diagram. [5] d) Hence, identify the function of the circuit. [2] Page 3 of 6

4 Figure Q5: State diagram 6. evelop a synchronous 2-bit up/down binary counter using JK flip-flops. The counter should count up when the control input is 1 and count down when the control input is 0. 7a) Explain i) The general principle of operation of shift registers ii) Their importance in digital circuits [3] [2] b) i) raw the logic circuit for a 3-bit Serial In Serial Out shift register. [6] ii) Explain the operation of the circuit drawn in b(i). [4] iii) Using the template provided in ttachment 7-1, show the state of each flip-flop and the output of the shift register at the indicated clock cycles. ssume that the input data stream is 010 and that all flip-flops are initially clear. The first one has been done for you. Note that the [5] flip-flops in Figure Q7 are represented as a generic block. Page 4 of 6

5 TTHMENTS ttachment 2-1 ode conversion table Page 5 of 6

6 ttachment 7-1 Flip-flop status with clock cycles ata input Initially LER 1 st. data bit = fter LK1 2 nd. data bit = 1 fter LK2 3 rd. data bit = 0 fter LK3 fter LK4 fter LK5 fter LK6 Page 6 of 6