Packaging trends for advanced Cmos technology nodes

Transcription

1 Packaging trends for advanced Cmos technology nodes Michel Garnier Packaging & Test Manufacturing Corporate Packaging & Automation STMicroelectronics Advanced Packaging Session, Semicon Russia 6th June 2013

2 Content 2 STMicroelectronics presentation General presentation R&D STM Packaging Platforms covered at ST Packaging development for Advanced Cmos technologies Business segments Main requests Cu pillar for FC packages Cu RDL for WLPs Conclusions

3 Who we are 3 A global semiconductor leader The largest European semiconductor company 2012 revenues of $8.49B (1) Approx. 48,000 employees worldwide (1) Approx. 11,500 (1) people working in R&D 12 manufacturing sites Listed on New York Stock Exchange, Euronext Paris and Borsa Italiana, Milano (1) Including ST-Ericsson, a 50:50 joint venture with Ericsson

4 Product Segments 4 ST-Ericsson* 50:50 JV with Ericsson Sense & Power and Automotive Products (SPA) Embedded Processing Solutions (EPS) Analog, MEMS & Sensors (AMS) Automotive Product Group (APG) Industrial & Power Discrete (IPD) Digital Convergence Group (DCG) Imaging, BiCMOS ASIC & Silicon Photonics (IBP) Microcontroller, Memory & Secure MCU (MMS) Wireless (WPS) *Exit to be completed by 3Q 2013

5 Where you find us 5 Our MEMS & Sensors are augmenting the consumer experience Our digital consumer products are powering the augmented digital lifestyle Our automotive products are making driving safer, greener and more entertaining Our Microcontrollers are everywhere making everything smarter and more secure Our smart power products are making more of our energy resources

6 Packaging Production & R&D Shenzhen - China Longgang - China Calamba Philippines Muar - Malaysia Toa Payoh - Singapore Kirkop - Malta Bouskoura - Morocco Corporate Packaging & Automation France / Italy / Malta / Singapore / Philippines / China Central PTM Singapore Toa Payoh Approximately employees located in 6 manufacturing locations 6 R&D centers ( CPA ) Over 400 different packages

7 BGA (Ball Grid Array) Platform Development & Advanced Packaging R&D CPA Grenoble, France Assembly Process R&D Copper wire dev. For low k wafers Flip-Chip dev. For low k wafers 3D TSV assembly (ST & Leti) Low k/ Ultra Low k Packaging solutions Package Design & BGA Substrate Technology New Product / Packaging Project Management Package Electrical Modeling & Measurement Assembly Design Rules Management 3D Advanced Packaging Wafer Level Solutions 7

8 Ceramic, BGA (Ball Grid Array) & Advanced Packaging Prototyping CPA Grenoble, France Best in class cycle time with Fab/EWS/Package test proximity Laminate & ceramic packages 12 inches wafer size capability SIP capability including SMD & FC 3D TSV assembly 1000m² clean room facilities Thin 50um Wire 36um pitch Fine Pitch Flip-Chip 80um 0.3mm BGA ball pitch Now open for external customers

9 BGA/ 2D & 3D Packaging Ecosystem 9 Presentation Title Package Dev/ customized solution Front-End R&D Group Engineering Packaging R&D FEBE compatibility First protos Internal BGA Manufacturing Flexibility OSATs BGA Manufacturing Grenoble Crolles cluster 6/6/2013

10 Content 10 STMicroelectronics presentation General presentation R&D STM Packaging Platforms covered at ST Packaging development for Advanced Cmos technologies Business segments Main requests Cu pillar for FC packages Cu RDL for WLPs Conclusions

11 «Moore s Law»: Miniaturization Baseline CMOS: CPU, Memory, Logic Packaging is a differentiation factor for new products Technology Competitive Advantage 11 «More than Moore»: Diversification Analog / RF Passives HV Power Sensors, Actuators Biochips 130nm SiP 90nm 65nm 45nm 32nm 22nm SoC Information processing Digital Content System-on-chip Interacting with people & environment Non-digital content System-in-package Beyond CMOS: Quantum Computing, Molecular Electronics, Spintronics VLSI PLATFORM Packaging is key enabler for both More Moore & More than Moore

12 Packaging Technology R&D 12 Sense MEMS and microphones (LGAs), Optical modules and Imagers towards BSI Power & BCD High dissipation, miniaturized packages (PSSO, QFNs) Digital with advanced CMOS Integration and miniaturization based on BGAs. Towards Flip Chip &WLP

13 LEAD FRAME based package Packaging technology roadmap DRIVING FORCES: Size, Integration, Pin Count, Power, Cost 13 Up to 100 pins PowerSO,PSSO High power System in Package (SIP) Hi-QUAD > 100 pins Medium power, Cost effective TQFPs-EP QFN > 100 pins QFP Medium power, Small size,(sip) Tapeless QFN-mr

14 Package footprint reduction (example) 14 Package footprint etqfp20x20 1 etqfp 20x I/O - 47% etq 20X20 QFN-mr 9X9 0.5 Ep-TQFP 14X I/O with Power bars & ground ring 180 connections - 68% 0.25 QFN-mr 9x9 124 I/O with power bars 180 connections Power Bar Ground Ring

15 Power Discrete Packaging Roadmap (Evolution vs. PFLAT, DSC, Hi Temp, Advanced D.A & Interconnection) H2Pak H.C. 2,3,6,7 L PFLAT Dual Side Cooling Thin wafers new process ClipPAK PFLAT 2x2 PolarPAK I2packFP SO-8 RIBBON DPak H.C. 2,3 L PFLAT 5x5 & 5x6 HV Hi Temp (SiC) Advanced Interconnections (GaN compatible) Bond / Mold Less SO-8 CLIP PSO-10 RIBBON Chip on Chip TO220/D2PAK Cold by pass PowerFLAT 5x6 Ribbon & Clip with 1,2 Islands PowerFLAT8x8 HV PSO-36 TO247 LGG Automotive OctaPack PFLAT AUTO Wettable Flanks Advanced Die Attach PFLAT 3.3x3.3

16 16 Presentation Title 06/06/2013

17 Content 17 STMicroelectronics presentation General presentation R&D STM Packaging Platforms covered at ST Packaging development for Advanced Cmos technologies Business segments Main requests Cu pillar for FC packages Cu RDL for WLPs Conclusions

18 Packaging Technology R&D 18 Sense MEMS and microphones (LGAs), Optical modules and Imagers towards BSI Power & BCD High dissipation, miniaturized packages (PSSO, QFNs) Digital with advanced CMOS Integration and miniaturization based on BGAs. Towards Flip Chip &WLP

19 Business segments (1/2) 19 Source: Prismark Consumer/ Portables: Mobiles/ smartphones Tablets Laptops, computers Portable gaming TV, Set Top boxes, displays, smart home

20 Automotive Safety Infotainment Business segments (2/2) Networking Imaging Imaging Signal Processor (smartphones, gaming) Microcontrollers General Purpose MCUs Secured MCUs

21 Percent of IC Package Value Add 100% Packaging Growth Trends in Value IC PACKAGE VALUE TREND Kc bp package value 21 90% Wire Bond (Leadframe/Module) 80% 70% 60% Wire Bond (BGA/CSP) 50% 40% Flip Chip DCA 30% 20% Flip Chip Package 10% 0% 3D TSV $6Bn 10% CAAGR $25Bn 6% CAAGR $59Bn Source: Prismark

22 BGA package STMicrolectronics (*) 22 Configuration Package type Description Pictures Single BGA PBGA 27² & 35² WB, molded PBGA FBGA 14² to 40² xfbga 2² to 23² xfbga 2² to 23² xfbga 2² to 23² POP 12² & 14² FC, not molded WB, molded FC, molded SIP, FC, WB, SMD,molded WB, molded FCBGA Matrix BGA POP 12² & 14² FC, not molded or molded (*): protos: all available in Grenoble pilot line, production: internal or external

23 Copper Pillars Packaging Roadmap Digital products From Wirebond to Flip Chip (Solder and Cu Pillar) and to 3D packaging Up to Wire Bonding BGA PBGA Solder Flip Chip BGA Fan In WLP FCBGA Cu Pillar Flip Chip BGA Fan Out WLP FCBGA Emerging technolog 3D ies Advanced Packaging PoP BGA Std SIP PoP PoP Fan Out WLP 3D,TSV, Si interposer STACK BGA FLIP CHIP FC CuP WLCSP

24 BGA - Thickness challenge 24 TFBGA 1.2mm VFBGA 1.0mm WFBGA 0.8mm UFBGA 0.65mm Available for production (*) (*): internal or external Presentation Title 06/06/2013

25 Packaging challenges 25 Needs for density, miniaturization, Integration Power management Cost

26 Wafer Level Fan-In Fan-Out Flip-Chip Copper Pillar Flip-Chip Solder Bump Copper Wire bond Packaging road map Digital Cmos Cmos040 Cmos032 Cmos028 Cmos020 Cmos014 Cmos040 Cmos032 Cmos028 Cmos020 Cmos014 3D,TSV, Si interposer Cmos040 Fan-In Cmos040 & above Fan-Out Cmos 028 Fan-Out Cmos020 Fan-Out Cmos014 Fan-Out

27 Flip underfill Flip - chip Packaging design & Simulation 27 Electrical Thermal 3D structure extraction Mechanical Convection & Radiation Conduction Convection & Radiation Mold compound Substrate barre1_i_barre1 V001 V003 barre1_sink 1 8 L001 R L003 R Cu plane Die flag Die Die Crack Thermal via Flip Chip Solder resist C001 F001 F003 5 C001_002 V002 V004 9 L R L R barre2_i_barre2 barre2_sink F002 5 C002 F004 Underfill Delam Underfill Crack

28 Packaging Materials 28 Packages Materials in packaging play key roles in Performance Power consumption and dissipation Price 2 major materials in any packages: Carriers: Leadframes / Substrates Interconnects: wires, bumps, RDL The right choice of materials for an optimized 3Ps Interactions with die and carriers

29 Packaging Materials 29 Packages Interconnections Carriers

30 30 Interconnection today in production Wire bonding process is still the predominant Why? Mature infrastructure Conservative business segments long product life time Mature design tools Huge technical improvements during last 20 years 90 s 10 s Bonding speed (w/s) 4-5 Up to 20 # I/O per device < Min Au wire diameter 32um 15um Min bond pad pitch >200um 40um Wire bonder price >120 k$ <70k$ Despite its weak overall performance vs flip-chip UPH Electrical performances

31 The move to Cu wire in packaging 31 STMicroelectronics drive into Cu wire Contributing to Price Performance Power Consumption Reduced carbon impact vs gold

32 Leading in Copper 32 Addressing the challenges of various technologies In high volume production 2009 : Length of gold wire converted to copper can circle the earth! 2012 : Length of gold wire converted to copper can reach the moon! Achieved!

33 Cu for Wirebonding 33 Advantages Drawbacks 1. Low cost 1. Hardness 2. Good electrical property 2. Sensitive to oxidation 3. Good thermal conductivity 3. Sensitive to corrosion 4. Compatible with thermo-sonic bonding process 5. Low Inter Metallic growth Fusion Temperature C Boiling Temperature 2562 C Electrical Conductivity S.m -1 Thermal Conductivity 401W.m -1.K -1 Thermal Capacity 380J.Kg -1.K -1

34 Cu Wires types 34 2 major kinds of copper wire - Bare Cu (4N), - Pd coated (4N-CuPd) Gold Pure copper CuPd Au Bare Cu CuPd Cost Electrical conductivity Thermal conductivity Hardness Oxidation Workability Reliability (Humid) Reliability (hot temperature) BSOB bonding (die to die)

35 Cu Wires types 35 2 major kinds of copper wire - Bare Cu (4N), - Pd coated (4N-CuPd) Gold Pure copper CuPd Pitch>50µm, opening>50µm Pitch =50µm, opening =44µm Pitch <50µm, opening<44µm Die to die bonding, pitch>50 Die to die bonding, pitch<50 Bare Cu 0.8mils 0.7mils x CuPd 0.6mils x Bare Cu wire: CuPd wire: preferred in mass production for dedicated line used for aggressive pitch and high line conversions rate

36 Cu Wire: Equipments & Toolings Wire bonding equipments Copper kit to create neutral environment to avoid ball oxidation. 36 Cu FAB formed in air Cu FAB formed in N 2 H 2 Forming gas ratio (95% N 2 ), proper gas flow rate needed for spherical ball shape Wire bonder selections depending on application complexity (BPP, BPO, looping) Wire bonding Capillaries Capillary life time to improve with harder ceramic and special tip treatments

37 Billions of parts produced in Cu Wire Wide variety of Packages & Applications 37 Industrial Consumer Wireless Computers & Peripherals Automotive 12,000 2,000 10,000 1,500 8,000 M units produced in Cu wire / year Cumulated M units produced 6,0001,000 in Cu wire Cumulated M Units produced in Cu wire 2,500 SMD Flat Diodes Hi-Quad By Package: BGA BGA Hi-Quad Hi-Quad PDIP PDIP Power Plastic Power PowerSO Plastic PowerSO PowerSSO PowerSSO QFN PowerSO PowerSSO QFNQFP 4, QFPSIL Power PDIP Plastic 2,000 SILSMD Flat Diodes & 0 SO SMD SO Watts Flat Diodes End 0 SOTSSOP Year May TSSOP Watts Year Watts BGA QFP QFN TSSOP By Package:

38 Billions of parts produced in Cu Wire Wide variety of Front End technologies 38 12,000 Cumulated M Units Cumulated M units produced produced in Cu in wire Cu wire 10,000 8,000 6,000 4,000 2,000 By Wafer Tech: BCD BIP CMOS Misc P.MOSFET VIPOWER Year

39 Thousands of Kms of Cu Wire Wide variety of Wire types 39 Earth's Circumference : Earth-Moon: km ~ km 800, , , , mils < 1mil 0.6mil By Dia (mil) Cumulated km of purchased Cu wires Cumulated km of purchased Cu wires 400, , , , Year

40 40 Wireless interconnection trend is one of the more demanding business segment in term of miniaturization, integration, electrical performances & cost 5% 15% 25% 80% 45% 30% More change in 2 years than during last 20 years

41 Ultra Low K Silicon Characterization : White Bumps WB = White Bump = Ultra Low K Delamination (too high stress below bump) Jerome Lopez- STM - Semi Europe

42 FINE PITCH / BUMPS LARGE PITCH / BUMPS Flip Chip Process: Solder Bumps Large Pitch Stress Reduction MR Mass Reflow (Capillary UnderFill) vs TC-NCP (Thermo-Compression) Mass Reflow Solder, Pitch 140µm PROS Mature (process,materials) Lower stress (soft bump, larger UBM) Sourcing flexibility CONS Substrate Cost (more layers, SOP) & Layout Large bump pitch Low stress due to large UBM & soft solder bump material 42 Cu pillars Large Pitch MR Cu pillars Fine Pitch TC Mass Reflow Cu Pillar, Pitch 125µm Thermo Compression Cu Pillar, Pitch 50µm (40um for 3D) Mature (process,materials) Limited stress (larger UBM) Reduce O/S risk vs Solder Current density per bump Sourcing flexibility Miniaturization Reliability & Yield Higher bump density & finer bump pitch <80um Substrate Cost (same as Solder Bump one) Large bump pitch & UBM size Stress induced by Cu Pillar is reduced thanks to usage of very large UBM size Substrate Cost & Layout Assy Cost & UPH Lower Sourcing flexibility No reflow, vertical stress with Thermo-Compression bond force NCPaste applied before die attach, absorbing part of stress. Cu pillars Fine Pitch Mass Reflow Cu Pillar, Pitch 80µm Mature (process,materials) Substrate & Assy Cost Sourcing flexibility Higher stress at bump area Sensitive to unsolder MR Reflow generates stress for bumps during cooling : Si & Substrate have CTE, stress on bumps without protection The larger the die, the more CTE stress mismatch (die to substrate) The more space available for pad pitch solder bumps rather than Pillars Die area (mm2)

43 Current status Target Q Stress Reduction Solder Bumps Large Pitch MR Flip Chip process vs Die Size Road Map Recommended Under analysis To be avoided Current Full confidence border Q4 13 Target confidence border 43 Cu pillars Large Pitch MR Cu pillars Fine Pitch TC Cu pillars Fine Pitch MR The larger the die, the more CTE stress mismatch (die to substrate) The more space available for pad pitch solder bumps rather than Pillars Die area (mm2)

44 Towards Cu Pillar Bumps for Flip Chip 44 Solder bumps Cu Pillar Bumps 130 µm < 80 µm Si Al SiN

45 Towards Cu Pillar Bumps for Flip Chip 45 Cu Pillar Bumps Higher density of interconnections allowed with finer pitch Good electrical properties Package performance increase < 80 µm High electro-migration performance Higher standoff for underfill process Higher thermal fatigue Lower substrate cost / solder mask

46 100µm Pitch Min. 230µm Pitch Towards Cu Pillar Bumps for Flip Chip 46 Solder bumps Cu Pillar Bumps 130 µm < 80 µm 230µm Pitch Solder Bump SMD (SOP) 140µm Pitch Pillar Bump NSMD (OSP)

47 100µm Pitch Min. 230µm Pitch Towards Cu Pillar Bumps for Flip Chip 47 Solder bumps Cu Pillar Bumps Substrate: 50% of package cost 130 µm Allows peripheral bump pitch routing relaxed Line / Space + less layers Cheap finishing for CUF/MUF (OSP) 230µm Pitch Solder Bump SMD (SOP) 140µm Pitch Pillar Bump NSMD (OSP)

48 Cu Pillars packaging 48 Cu Pillar interconnections on BGA substrates FC CuP Cu Pillar interconnections on 3D / Die to Die

49 ST s competitiveness moving to 3D Jean Michailos - STM - European 3D TSV Summit 2013

50 3D integration environment = ST strength Jean Michailos - STM - European 3D TSV Summit 2013

51 ST first step in 2.5D TSV WL camera Jean Michailos - STM - European 3D TSV Summit 2013

52 3D main technical challenges Front side processes TSV etching (depth & uniformity) TSV Cu filling Portable to advanced technology nodes (FDSOI) Back side processes Carrier temporary bonding & thin wafer de-bonding Jean Michailos - STM - European 3D TSV Summit 2013

53 3D main technical challenges 3D Package assembly Thin die sawing, pick & place, warpage, non solder Jean Michailos - STM - European 3D TSV Summit 2013

54 Analog/digital partitioning Jean Michailos - STM - European 3D TSV Summit 2013

55 Memory on Application Processor Jean Michailos - STM - European 3D TSV Summit 2013

56 Further development axes Jean Michailos - STM - European 3D TSV Summit 2013

57 ST status & perpectives Jean Michailos - STM - European 3D TSV Summit 2013

58 58 Wafer Level Packaging Fan In-WLP Fan Out-WLP (ewlb) Solder ball UBM (Under Bump Metallurgy) RDL (Al,Cu) Si Chip Solder ball Cu-RDL Si Chip EMC Courtesy of Infineon/ Stats-Chippac/ ST 2010

59 59 Fan-out WLP / 2-side Pre-formed PCB Bar 8x8 Fan-out 12x12 Fan-out Laser drill and pasted filling epop Package epop X-section 180um 450um

60 3D-eWLB / 3D-IC Package Roadmap Single Sided, Single Chip Double Sided, Single or Multi-Chip F2F or Multichip SoW PoP F2F + SoW SiP on Wafer (SoW) F2F + FO-WLP Single Chip Multichip Multichip + SoW Courtesy of Infineon/ Stats-Chippac/ ST

61 Interconnections The Interconnections trends for new Packaging 61 Sense & Power Digital Sensors Power Adv. QFNs WLPs WB BGAs FC BGAs 3D IC Cu wires Cu Pillars Cu RDL

62 Content 62 STMicroelectronics presentation General presentation R&D STM Packaging Platforms covered at ST Packaging development for Advanced Cmos technologies Business segments Main requests Cu pillar for FC packages Cu RDL for WLPs Conclusions

63 Conclusions 63 An overview of packaging trends was presented Packaging is a differentiation factor for new products Interconnection is evolving fast WB no more considered for advanced Cmos technologies Copper metal is predominant Main dev/ activities: FC Cu pillar 3D 3D & WL combination Team work & anticipation are fondamendal for success Co-design FEBEcomp activities Electrical, thermal & thermo-mechanical modelling

64 64 Packaging by ST Thank You

65 65