High-Performance Technologies for an Analog-Centric World

Transcription

1 High-Performance Technologies for an Analog-Centric World Oct 13, 2011 Lou N. Hutter, SVP GM, Analog Foundry Business Unit Dongbu HiTek

2 Agenda Analog in Our World Today Diverse Technology Needs of the Analog Market High-Performance Analog Technologies Major Challenges in the Analog Roadmap Conclusions

3 2 Big Questions 1) The World is Going Digital, Right? 2) So Why am I Talking About Analog?

4 Fancy Smart Phones Apple iphone4 Samsung Galaxy

5 Apple iphone4 - A Closer Look Analog Power Audio Video Display Touch Transmitters Compass Logic/Memory Apps Processor + DRAM NAND Flash NOR Flash Quad Baseband Gyroscopes Accelerometer 9 Chips 4 Chips

6 Notebook A Closer Look Without Analog.. It won t TURN ON! The screen won t DISPLAY! Many other functions won t WORK (In case the 1st 2 problems weren t bad enough) Analog Inside

7 Analog is Everywhere Analog Semiconductor ICs

8 Answers to the 2 Big Questions 1) The World is Going Digital, Right? Yes 2) So Why am I Talking About Analog? Because the World s Going Digital But it needs Analog to get there!

9 What Did He Say???...A Closer Look Real World Signal Conditioning (Analog) The High Buzz Stuff Small Feature Sizes Temperature Pressure Position Motion Sound Video Light How to Electronically Interact With, and Control, This Real World? Signal Conditioning (Analog) Processor (Digital) The Low Buzz Stuff That Makes it Work

10 A Golf Analogy 1) You Drive for Show Logic/Memory and 2) You Putt for Dough Analog

11 Agenda Analog in Our World Today Diverse Technology Needs of the Analog Market High-Performance Analog Technologies Major Challenges in the Analog Roadmap Conclusions

12 Application Space Analog CMOS Automotive (Sensors) Baseband PMICs Audio Amplifiers (GP & HP) Data Converters (GP & HP) Power Automotive (Engine, ABS) LED Drivers & Lighting Class-D Audio Solar Micro-Inverters Motor Drivers Telecom, PoE

13 Digital vs. Analog Voltage Levels 1000V Electric Vehicles, Trains, Power Distribution LED Lighting, Industrial 100V 10V 1V Telecom, PoE Automotive, LED Drivers, Solar Hard Disk Drives, Industrial, Power Management Cell Phones, Power Management, Precision Analog Digital Logic 100mV Audio Signals 10mV Energy Harvesting Signals

14 Building an Analog Portfolio Analog IP & ESD Memory Functions High-Performance (Noise, TFR, PIP Caps) High-Voltage/Power (DECMOS, LDMOS, Power Metal) Analog CMOS Baseline (Logic CMOS, Analog CMOS, Passives, B/Gap Bipolar)

15 Agenda Analog in Our World Today Diverse Technology Needs of the Analog Market High-Performance Analog Technologies Major Challenges in the Analog Roadmap Conclusions

16 Technology Care-Abouts Analog CMOS Automotive (Sensors) Logic CMOS Baseband Analog CMOS PMICs Poly or Thin-Film Resistor Audio PIP or MIM Cap Amplifiers (GP & HP) DECMOS (7V-30V) Data Converters (GP & HP) Bipolar (NPN & PNP) JFETs Low CMOS 1/f Noise Low Resistor TCR Low Capacitor VCC & DA Component Matching Low Package Shifts Focus on Performance & Density Power BCD Automotive (Engine, ABS) Logic CMOS LED Drivers & Lighting Analog CMOS Class-D Audio LDMOS (N & P) Solar Micro-Inverters DECMOS Motor Drivers Poly Resistor Telecom, PoE MIM Cap Bipolar (NPN & PNP) Low CMOS 1/f Noise Component Matching 30V, 60V, 85V, 150V, & 700V Thick Cu Metallization ESD Capability Focus on Power & Voltage

17 Analog Requires Diversity DBH s 0.35um Nodes DBH s 0.18um Nodes AN350 3V Analog CMOS AN V / 5V Analog CMOS AN350 5V Analog CMOS HP V / 5V HP Analog CMOS BD350 BD350 BD350HV BD350HV BD350LV 3V / 60V BCD 5V / 60V BCD 3V / 85V BCD 5V / 85V BCD 5V / 24V BCD BD V / 5V / 60V (Gen1) BD180X 1.8V / 5V / 60V (Gen2) BD180XHV 1.8V / 5V / 85V BD180LV 1.8V / 5V / 30V (NBL) BD180LV 1.8V / 5V / 20V (No NBL) UHV700 UHV700 5V / 20V / 700V (Epi) 5V / 20V / 700V (No NBL)

18 DBH s 0.18um Modular Platform IP Portability & More BD180X* 60V Power Process (Extension to 85V) BD180LV 30V Power Process (Epi) HP180 Precision Analog 1.8V/5V Mixed Signal + High Voltage BD180LV 20V Power Process (Non-Epi) * BD180X is a Gen-2 Process. Gen-1 (BD180) is Fully Qualified (4Q08) and in Production.

19 AN um Analog CMOS Svg (V 2 /Hz) Svg (V 2 /Hz) Technology Features Baseline: 1P3M (up to 6M) M1 Pitch: 0.46 µm Top Metal: 3 μm Al (Option) CMOS: CMOS: CMOS: CMOS: Density: 1.8V & 5V Isolated Low-V T Low 1/f Noise 115K Gt/mm 2 (1.8V) DECMOS: 7V 30V NPN: 10V RES: Poly 215, 2K Ω/sq CAP: MIM 2.0 ff/µm 2 NVM: Fuse, Anti-Fuse, MTP PDK: Cadence, Others Available: Now 5V PMOS Noise Data T-25C 5V NMOS Noise Data T=25C HVPMOS (Svg) Vg=Vth-1.0, Vds=-2.5V 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 1E-10 1E-11 1E-12 1E-13 1E Frequency (Hz) 10/0.5 10/10 HVNMOS (Svg) Vg=Vth+1.0, Vds=2.5V Frequency (Hz) 10/0.5 10/10

20 AN180 24V DECMOS Capability 24V DENMOS 24V DEPMOS Enables HV Capability in a LV CMOS Process Extends Application Space for Technology No Mask Adder

21 BD180LV 0.18um, 30V Power Process Technology Features Platform: AN V Power Flows: 1P3M, Epi & Non-Epi Top Metal: 3 μm Al (Option) CMOS: 1.8V & 5V CMOS: Isolated CMOS: Low-V T Density: 115K Gt/mm 2 (1.8V) NLDMOS Rsp Data T=25C (Epi Flow) STM BCD8 TI LBC7 Toshiba BiCD-0.13 DBH BD180LV DECMOS: 7V 30V NLDMOS: 7V 30V, SOA-Optimized PLDMOS: 7V 30V, SOA-Optimized NPN: 10V RES: Poly 215, 2K Ω/sq CAP: MIM 2.0 ff/µm 2 NVM: Fuse, Anti-Fuse, MTP PDK: Cadence, Others Available: Now (NBL), Now (Non-NBL) 24V NLDMOS SOA Data T=25C (Epi Flow) Note: Barth TLP data on 24V nldmos with W=42um. VT=1V (100ns pulse width, 10ns rise time)

22 BD180LV IDM-Like Rsp Performance STM BCD8 NLDMOS TI LBC7 Toshiba BiCD-0.13 DBH BD180LV DBH BD180LV (no epi)

23 [mw mm2] BD180X 0.18um, 60V Power Process Specific On-resistance (Rsp) [mw mm2] Technology Features Platform: AN V Power Rsp vs BVdss ; nldmos Flow: 1P3M, Epi Top Metal: 3 μm Al (Option) BD180_60V - nldmos LS CMOS: CMOS: CMOS: Density: BD180LV - nldmos LS BD180X - nldmos LS target BD180X_60V 1st Si 1.8V & 5V Isolated Low-V T 115K Gt/mm 2 (1.8V) Conv. DNWELL structure Rsp vs Rated Voltage ; nldmos BD180_60V - nldmos LS 80 BD180LV - nldmos LS BD180X - nldmos LS target 60 BD180X_60V 1st Si DECMOS: 12V 60V NLDMOS: 12V 60V, SOA-Optimized PLDMOS: 12V 60V, SOA-Optimized NPN: 10V NDT structure RES: Poly 215, 2K Ω/sq CAP: MIM 2.0 ff/µm 2 NVM: Fuse, Anti-Fuse, MTP PDK: Breakdown Voltage [V] Cadence, Others Available: Now Rated Voltage [V]

24 BD180XHV * 85V Preliminary Data Ids [ua/um] V LS NLDMOS 85V nldmos Ldr=6.0um (X=0.7um) BV-on W=21x2um Vgs=0V Vgs=2V Vgs=3V Vgs=5V Vds [V] * In Development

25 HP180 Precision Analog Process Technology Features Platform: AN180 + Precision Flow: 1P3M, Non-Epi Top Metal: 3 μm Al (Option) 10/0.6 Noise NMOS Noise Comparison Vds=-2.5V, Vg=Vth+1.0 CMOS: 1.8V & 5V CMOS: Isolated CMOS: Focus on Low Noise TFR: SiCr 1K Ω/sq, TCR < 25 ppm/c JFET: 5V N- and P-JFET, Low Noise DECMOS: 7V 24V NPN: 10V, Isolated HSR: 2K Ω/sq CAP: PIP 1.0 ff/µm 2, Low DA & VCC 10/0.6 PMOS Noise Comparison Noise Comparison Vds=-2.5V, Vg=Vth+1.0 NVM: Fuse, Anti-Fuse, MTP PDK: Cadence, Others Available: Now

26 HP180 High-Performance Passives Thin-Film Resistor Poly-Poly Capacitor TCR ~ 5 ppm/c VCC L ~ 2.0 ppm/v VCC Q ~ 2.8 ppm/v 2

27 UHV um, 700V Capability Idsat [A] Id [A] 0.35 µm 1P4M Epi & Non-Epi Flows M1 Pitch: 1.0 µm M4 Thick: 3 µm (Al) CMOS: 5V CMOS: Isolated CMOS: Low-VT Technology Features MIM CAP: 5V 1.0 ff/µm 2 PIP CAP: 8V~20V 1.0 ff/µm 2 NLDMOS: 450V, 700V PLDMOS: 450V, 700V DECMOS: 12V 30V NPN: 5V, 20V PNP: 5V, 20V RES: Poly 320 ~ 10K Ω/sq NVM: Fuse, OTP, MTP Gate Density: 13K Gt/mm 2 200mm Wafers SOA Characterized PDK: Cadence, Others Status: 4Q11 Qual (Non-NBL) 1Q12 Qual (NBL) 9.E-03 8.E-03 7.E V SF nldmos Vgs=2.4V 1.E-06 1.E V SF nldmos 6.E-03 5.E-03 Vgs=2.2V 1.E-08 4.E-03 3.E-03 Vgs=2.0V 1.E-09 2.E-03 1.E-03 0.E+00 Vgs=1.8V Vgs=1.6V Vds [V] 1.E-10 1.E Vds [V]

28 Agenda Analog in Our World Today Diverse Technology Needs of the Analog Market High-Performance Analog Technologies Major Challenges in the Analog Roadmap Conclusions

29 Moore s Law Impact on Digital 10 um 1 um Modern CMOS Beginning of Submicron CMOS Deep UV Litho 65 nm in nm 10 nm Every Generation Feature size shrinks to ~70% Transistor density doubles 90 nm in nm in 2009 Presumed Limit to Scaling 32 nm in 2011 EUV Litho ? 1 nm Courtesy Peter Rickert, TI

30 Moore s Law How Digital Scaling Works 100% x70% x70% Generation Area/Die 100% 50% 25% 12.5% 6.25% Die/Wafer Cost/Wafer Cost/Die Note: Assumes Constant Wafer Size, Constant Capacity Cheaper

31 Analog Scaling Issue: Not Much to Scale Transistor Size Analog & Power Scale Slower Not Much Digital on a Typical Analog ICs Power/ HV Analog Analog HV/Power Digital Digital Analog Technology Feature Size

32 Simple Scaling Doesn t Work Well for Analog Digital 20% Analog 30% x70% x85% x85% HV/Power 50% x90% x90% Generation Area/Die 100% 73% 53% Die/Wafer Cost/Wafer Cost/Die Note: Assumes Constant Wafer Size, Constant Capacity More Expensive

33 Analog Scaling Need the Z-Dimension nalog HV/Power Digital Analog Factors STI CMP Well Dopings Cu BEOL Device Issue Resolution LDMOS Isolation Capacitor Resistor HV Means Large Physics- Dictated Drift Region. HV Means Large Spacing Between Nearby Devices. Planar Area Set by Voltage Capability of Dielectric. Poly Resistors Consume Space in FEOL. Impact Dishing Forces Density Rules, Which Impact Resistors & Caps. Higher Doping Reduces HV Device BVs. CMP Dishing Forces Metal Density Rules, Not Good for Power Devices. Trench LDMOS. Trench Isolation. MIM Caps over Active Circuitry. TFR in BEOL.

34 Widening Technology Gap 10 um 5um 1um 1 um Analog 130nm 100 nm 10 nm Logic Litho-Based Analog Scaling Will Slow Targeted Component Scaling Will Allow Die Shrinks to Occur 1 nm

35 Conclusions The Real World is Analog Analog is What Gives Products Their Character Analog Means Diversity Analog Scaling More Difficult than Digital Dongbu HiTek Understands Analog and Has Leadership Technologies and a Roadmap to the Future We Are Working to Reach Our Vision: Most Respected Analog Foundry

36 Thank You