DOUBLE PATTERNING CHALLENGES FOR 20nm TECHNOLOGY

Transcription

1 DOUBLE PATTERNING CHALLENGES FOR 20nm TECHNOLOGY SEMICON DRESDEN TechARENA OCTOBER 12 th 2011 Vincent Farys, Bertrand Le-Gratiet, Pierre-Jérôme Goirand STMicroelectronics Crolles

2 2 OUTLINE Lithography Roadmap Double Patterning introduction in 45 and 28nm Technologies Double Patterning for 20nm Presentation of Double Patterning for Metal1X Interconnection for 20nm Design Challenges Process Challenges Double Patterning Costs comparison Conclusions

3 3 OUTLINE Lithography Roadmap Double Patterning introduction in 45 and 28nm Technologies Double Patterning for 20nm Presentation of Double Patterning for Metal1X Interconnection for 20nm Design Challenges Process Challenges Double Patterning Costs comparison Conclusions

4 4 LITHOGRAPHY ROADMAP FOR LOGIC CMOS 150 METAL Pitch roadmap for Logic CMOS nm 193nm Immersion Pitch nm nm 193nm Immersion double patterning by frequency doubling double patterning used for: 1- active/gate end cut 2- salicide area definition 3- contact (pitch splitting) 4- metal1x (splitting vs doubling) double patterning used for cutting gate end on dense memory cell 28nm 193nm Immersion 64 14nm EUV or SIT 193nm Immersion Years Pitch limit for 1D single expo 193nm Immersion 45 10nm EUV or ML2 32

5 5 OUTLINE Lithography Roadmap Double Patterning introduction in 45 and 28nm Technologies Double Patterning for 20nm Presentation of Double Patterning for Metal1X Interconnection for 20nm Design Challenges Process Challenges Double Patterning Costs comparison Conclusions

6 DOUBLE PATTERNING INTRODUCTION IN 40 AND 28nm TECHNOLOGIES Critical gaps between gate are more easily patterned using a cut mask. No design split, neither constrained design rules, but pitch is not enhanced.

7 7 OUTLINE Lithography Roadmap Double Patterning introduction in 45 and 28nm Technologies Double Patterning for 20nm Presentation of Double Patterning for Metal1X Interconnection for 20nm Design Challenges Process Challenges Double Patterning Costs comparison Conclusions

8 8 DOUBLE PATTERNING FOR 20nm For 20nm technology, what are the options? 1D critical levels where pitch is 80nm, can be patterned with cut mask strategy active area and gate definition 2D critical levels at pitch 80nm have to be patterned with pitch splitting, and litho-etch-litho-etch (LELE) strategy: Contacts definition. 1D critical levels where pitch is 80nm, can be patterned with pitch splitting (LELE) or frequency doubling patterning (Spacer Image Transfer): Metal 1X where pitch is 64nm Will be discussed later on

9 9 OUTLINE Lithography Roadmap Double Patterning introduction in 45 and 28nm Technologies Double Patterning for 20nm Presentation of Double Patterning for Metal1X Interconnection for 20nm Design Challenges Process Challenges Double Patterning Costs comparison Conclusions

10 Target mask1 mask2 Target mask1 mask2 Target mask1 mask2 10 DOUBLE PATTERNING FOR METAL1X 20nm Target 2 viable solutions exist: Target Target Target Direct decomposition i.e. LELE Indirect decomposition i.e. SIT (Sidewall Image Transfer) Target Litho 1 Litho 2 Litho 2 Mask 1 Mask Mask 1 2 Litho 1 Mask 2 Mask 1 Mask 21 mask1 Target Target Target mask1 mask1 mask1 mask1 mask2 mask2 mask1 mask2 mask1 mask2 mask1 mask1 mask2 mask2 mask2 Mentor DDL Brion DDL Mentor DDL Brion DDL Mentor DDL In both cases, small trenches (35 nm) have to be printed Brion DDL Mentor DDL as Positive Tone Development is limited to 45nm dimension, introduction of Negative Tone is mandatory Brion DDL Double patterning and Negative Tone development represent real process breakthroughs regarding previous node

11 LELE SIT 11 DETAILS OF DOUBLE PATTERNING FOR METAL1X 20nm SOC opened TEOS hardmask TiN hardmask SOC opened TiN hardmask Litho1 + trilayer etch Litho1 + trilayer etch SiO2 spacer on SOC Etch TEOS hardmask Spacer Dep + Etch+ SOC strip Litho2 + trilayer etch Litho2 + trilayer etch Etch2 TEOS hardmask + TiN + resist strip Etch TiN hardmask + SOC strip Similar flow complexity, but different patterning accuracy

12 12 DOUBLE PATTERNING FOR METAL1X 20nm: SIT process scheme clips 3. 2 nd Block litho 4. Etch TiN HM 1. Core-mandrel 2. Spacer etch

13 13 DOUBLE PATTERNING FOR METAL1X 20nm: LELE process scheme clips M1 M1+I1 I1 TEOS Hard Mask opened TEOS Hard Mask M1 TiN Hard Mask opened I1 M1 M1 TEOS Hard Mask opened TiN Hard Mask Bottom CD1(M1) = 25.7nm Bottom CD2(I1) = 27.2nm

14 14 OUTLINE Lithography Roadmap Double Patterning introduction in 45 and 28nm Technologies Double Patterning for 20nm Presentation of Double Patterning for Metal1X Interconnection for 20nm Design Challenges Process Challenges Double Patterning Costs comparison Conclusions

15 15 DESIGN CHALLENGES Main Challenges Need design process co-optimisation to define the rules Design rules needs to be DP-aware to avoid coloring conflict (Not able to correct these conflicts at process level). RX PC CTC > crit pitch < crit pitch < crit pitch Decomposition capability has to move from process level () to design level (P&R) P&R tools need to be abble to automaticaly correct colouring conflict

16 16 DESIGN CHALLENGES Example of DPT Routing issue SIT LELE Coloring conflict Color conflict at stitching area

17 17 DESIGN CHALLENGES After re-routing SIT LELE

18 18 OUTLINE Lithography Roadmap Double Patterning introduction in 45 and 28nm Technologies Double Patterning for 20nm Presentation of Double Patterning for Metal1X Interconnection for 20nm Design Challenges Process Challenges Double Patterning Costs comparison Conclusions

19 LELE Litho1 Litho2 PROCESS CHALLENGES LELE Overlay Litho2-litho1 CD1 CD2 Dimensional control: 2 independent distributions High dimentional control required Yield/Reliability: space between metal lines should not be too small and directly depends on overlay of litho2 to litho1 Overlay: control to previous and following double patterning levels. Gaps between lines end, have limited resolution High overlay constraint around 3 nm between litho 1 and 2 Complexe and tighter overlay to previous and following double patterning levels. Additional cut mask can be added at the expense of high costs 19

20 SIT PROCESS CHALLENGES SIT CD1 CD2 Dimensional control: CD2 depends on CD1 and uniformity of spacer process Gaps between lines end, and line to line end, is controled by the second litho High uniformity of spacer process (spacer deposition and etch) is required CD compensation from non uniformity can be optimized in litho High resolution of second litho is required for gap, through lithography and optimization 20

21 21 OUTLINE Lithography Roadmap Double Patterning introduction in 45 and 28nm Technologies Double Patterning for 20nm Presentation of Double Patterning for Metal1X Interconnection for 20nm Design Challenges Process Challenges Double Patterning Costs comparison Conclusions

22 DOUBLE PATTERNING COSTS COMPARISON 22 Back end choosen here is an 11 metal levels, using trench first hard mask for all levels but the last 2 metals, with: 2 or 3 Metal1X pitch 64: LELE or SIT using trilayer 4 or 5 Metal1X pitch 80: Single patterning using Barc 2 Metals2X 193nm lithography 2 Metals 8X 248nm lithography Pads 248nm lithography

23 23 DOUBLE PATTERNING COSTS COMPARISON 1 Metal1X brick Double Cu damascene, trench first hard mask process # Steps for Critical Met1X patterning Ref 28nm LELE SIT ULK stack deposition Hard masks dep Critical diel deposition Litho (metal+via) Etch/cleans (metal+via) Metal barrier+fill CMP # of steps Number of steps increased equally by 40%, for LELE and SIT 1

24 24 DOUBLE PATTERNING COSTS COMPARISON Cost increase for 1 Metal1X brick Cost increase for the whole Back End As a conclusion, LELE has a slight cost advantage vs SIT. It is simpler to introduce, using more conventional design rules and routers, deposition and patterning techniques, whereas it has strong overlay constraints.

25 25 OUTLINE Lithography Roadmap Double Patterning introduction in 45 and 28nm Technologies Double Patterning for 20nm Presentation of Double Patterning for Metal1X Interconnection for 20nm Design Challenges Process Challenges Double Patterning Costs comparison Conclusions

26 26 CONCLUSIONS 20nm LITHOGRAPHY LEVEL DOUBLE PATTERNING CUT MASK DOUBLE PATTERNING PITCH SPLIT - LELE DOUBLE PATTERNING PITCH DOUBLING - SIT ACTIVE - GATE -Possible strategy because of 80nm -Process: overlay not over constrained -Cost: low added cost -Possible strategy -Process: high overlay constraint -Cost: moderate added cost -Possible strategy -Process: constraint on CD control -Cost: moderate added cost CONTACT VIA1X -Not suitable! Possible strategy Process: overlay not overconstrained if contact is the only LELE level -Possible, with very restrictive design rules LINE1X -Impossible due to pitch < 80nm -Possible strategy -Design: easy for traditional routing tools -Process: high overlay constraint -Cost: moderate added cost -Possible strategy -Design: need new routing tools -Process: need new critical deposition process. Constraint on CD control. Scalable down to 14nm. -Cost: moderate added cost

27 27 Acknowledgements This presentation has been made possible thanks To Lens Project Organisation and Partners To ST R&D teams

28 Thank You 28