Selective isotropic etching of Group IV semiconductors to enable gate all around device architectures

Transcription

1 TEL Technology Center, America, LLC - imec Selective isotropic etching of Group IV semiconductors to enable gate all around device architectures SPCC, April 10, 2018 S. Kal 1, C. Pereira 1, Y. Oniki 2, F. Holsteyns 2, J. Smith 1, A. Mosden 1, K. Kumar 1, P. Biolsi 1, T Hurd 1. 1 TEL Technology Center, America, LLC, USA 2 Imec, Belgium Subhadeep.Kal@us.tel.com

2 Chemical Oxide Removal (COR) Reaction Mechanism: Case for O 2 etch HF and NH 3 adsorb on the O 2 surface, reacting to form (NH 4 ) 2 F 6 Fluorosilicate - AFS) (Ammonium HF NH 3 HF (NH 4 ) 2 F 6 NH 3 O 2 NH 3 catalyzes a desired reaction pathway Slide courtesy: Tokyo Technology Solutions 2

3 A typical oxide etch process with Certas AFS Thickness=50.02 nm AFS O2 Post COR etch O2 Post PHT treatment (COR PHT) process can be repeated in cyclic fashion to meet process requirements ~4X Volume Expansion Pristine oxide surface regenerated 12nm Oxide Removal Recipe post PHT Ability to: Process with PR Additional knob to control: Pattern wiggling Pattern damage Slide courtesy: Tokyo Technology Solutions 3

4 Spacer Nanosheet Selective Etches INNER SPACER MODULE HM: N (or CN, OC) Spacer: OxCyNz Inner spacer: OxCyNz (would be different from spacer material) HM/dummy poly Spacer / fin P N Dmy poly Dmy OX Inner spacer Spacer formation Fin recess Cavity etch Inner spacer formation 4

5 Spacer Nanosheet Selective Etches SD/ILD0/RMG MODULES N-EPI: :B, P-EPI: :P CESL: N ILD0: O2 Dummy poly (dummy gate): a- EPI Inner spacer Dmy poly Dmy OX SD EPI ILD0 CESL CESL/ILD0 Dummy poly/ox removal Channel release HK MG HKMG 5

6 EA[nm] Selective etch for Nanowire N N N Step 1 Substrate Substrate Substrate Certas : selectivity Poly Partial release : etch =5-6 nm (each side, total = 10-12nm) loss <1nm Etch target and uniformity >5 A Square etch front Full release: etch ~25 nm (each side, total ~25nm) loss <1nm Etch gas[sccm] The above data is on blanket films 6

7 COR : etch: etch time optimization Incoming POST gas phase etch (recipe A; aggressive etch) No process T1 T2 T3 (T1<<T3) Summary for / stack: Selective : etch on imec wafer looks good (: >50:1) etch front looks VERY flat/square EA proportional etch time, without additional loss Partial etch uniformity ~3nm for Left /right side & top/bottom layers (incoming tapper may contribute) 7

8 COR : etch: pressure optimization Incoming POST TEL gas phase etch (Recipe B; medium etch) No process P1 P2 P3 P4 (P1<<P4) Summary for / stack: Selective : etch on imec wafer looks good (: >50:1) etch front looks VERY flat/square EA proportional etch time, without additional loss Pressure (i.e etch gas partial pressure) is contributing to slower etch rate due to byproduct formation depending on CD causing left-right and top-bottom non uniformity 8

9 Overlay comparison with incoming COR : etch: cavity and channel release Incoming POST Etch ET/ cyc No process Cavity etch Channel release Tilted Non-Tilted Ge%for = 20% Summary: : etch selectivity > 50:1 No N HM loss ER = 70nm/min etch front is square Data based on alternate test structures 9

10 Non-Tilted COR : etch: annealing effect Incoming POST etch No process Without anneal WITH anneal Summary : Ge%for = 20% 1 Steam anneal 500C 2hrs 2 RTP 850C 1min 3 RTP 850C 5s Anneal affects the ER significantly Anneal also reduces the : selectivity at the - interface o resulting in loss o meniscus etch front Data based on alternate test structures 10

11 EA[nm] Selective etch for Nanowire application N N N Step 1 Substrate Substrate Substrate Certas : selectivity Poly Partial release : etch =5-6 nm (each side, total = 10-12nm) loss <1nm Etch target and uniformity >5 A Square etch front Full release: etch ~25 nm (each side, total ~25nm) loss <1nm Etch gas[sccm] The above data is on blanket films 11

12 Tilted Non-Tilted COR : etch: etch time optimization Incoming POST Etch ET/ cyc No process 90S 120S Ge%for = 20% Summary: : etch selectivity > 10:1 No N HM loss ER = 7nm/min etch front is requires further improvement Post etch surface is smooth 12

13 COR N spacer etch N liner N Substrate N liner/spr dep N liner N Substrate N liner/spr etch Selective N spacer etch: Required N: etch selectivity > 25:1 (no loss) Required N: etch selectivity > 25:1 (no loss) Summary: N: / etch selectivity > 50:1 No loss N still preserved on layers 13

14 COR Selective dummy poly (a-) pull N/O a- N/O ILD0 CESL Isotropic gas etch CESL/ILD0 Dummy poly/ox removal Dummy poly removal : Extremely selective etch ~ nm No N loss or O2 loss Device structure Test structure 14

15 Nanosheet Selective Etches: Updated Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Step 9 Fin recess Cavity etch Inner spacer formation Dummy poly removal Channel release Test structure 15

16 Conclusion Dry plasma free etches are advantageous & crucial for Nanowire/CFET integrations applications, due to: High etch selectivity, inherent from the etch mechanism No plasma damage Aspect ratio dependency Cyclic process (potential self limiting capability) 16

17