Patterning Challenges for N7 and Beyond At a Crossroads. Steven Scheer. Director, Corporate Development Division TOKYO ELECTRON LIMITED

Transcription

1 Patterning Challenges for N7 and Beyond At a Crossroads Steven Scheer Director, Corporate Development Division TOKYO ELECTRON LIMITED Advanced Technologies in Accelerating Digital Era and IoT Forum Friday, September 4, 2015 Room 401, TWTC Nangang Exhibition Hall, Taipei 1

2 Different Drivers Continuous Growth B USD Mobile Computing Analytics Sensing Enhancement ipad iphone Cellphones w/ camera G Cellphones , IBM PC MS-DOS Source: IHS Q

3 Technology Roadmap: Continuous Innovation Functional Diversification More than Moore CMOS Scaling KrF ArF ArF-Immersion DRAM Cu/ULK Wire-Bonding Strained Si High-k Metal Gate FinFET Flip-Chip NAND Homogeneous 2.5D 3D NAND STT-MRAM 3DI ReRAM Heterogeneous Si Photonics Advanced Packaging (3DI / WLP) Now DP/MP Cu/ELK Nanowire FET Emerging Memory 2017~ More Moore EUV DSA NIL, EBDW Patterning New Material New Structure Source: Tokyo Electron Limited (based on ITRS) 3

4 Patterning Destination Set by Device Technology DRAM 3D NAND Logic Planar STI PMOS T. Ghani, et al., IEDM Dry Exposure FinFET STI 22nm (FinFET RMG) C. Auth, et al., VLSI tech SADP + Cut (x1 2) Nanowire STI SEM Image : TEL AR > 50 Jae-woo Im et al., ISSCC, 201 R. Coquand et al., VLSI tech SAQP + Cut (x2 3) 4

5 Patterning Paths Which to Choose? EUV Multiple Patterning DSA Source: IMEC 2015 Process Simplicity Design Flexibility Pitch Scalability Production Ready Low CapEx Materials Enabled Shrink High CapEx Tool Productivity Edge Placement Error (EPE) Process Complexity Self Alignment Defect Design Flexibility 5

6 Patterning at a Crossroads 6

7 Immersion Multiple Patterning Patterning Superhighway Gate Fin Metal 7

8 Immersion Multiple Patterning Process Pre Pattern Grid Formation Cut Pattern Pattern Memorization Critical Process Step 193i Single Patterning Litho Material Process SAMP (DP, QP, OP) Deposition Etch LE x Multiple Patterning Litho (193i, EUV) Planarization Etch Line Cut Etch Deposition Key Patterning Technology LER Reduction CDU Control LER Reduction CDU Control Spacer Selectivity Hole Shrink Pattern Healing Variation Control Self Alignment Pattern Reversal HM Selectivity 8

9 Grid Pattern Formation DCS & Metal Oxide Spacer SiO 2 SADP Performance Enhancements Direct Current Superposition (DCS) Technology Photo Resist TiO SiARC Ar + EB H* DCS cured (Enhanced Smoothing) PR Curing Si Si Si TiO Spacer (Improved Selectivity) Si Coating 9

10 Grid Pattern Formation DCS & Metal Oxide Spacer 44nm hp Photo Resist 22nm hp Spacer Depo Spacer RIE Middle Layer RIE Bottom Layer RIE Ox spacer DCS applied TiO spacer Improved LER & Resist Profile No recess on Middle Layer Higher RIE Selectivity Improved Image Transfer Low temperature TiO and DCS process enable improved SADP process 10

11 Cut Pattern Formation Healing & Shrinking For Fin, Gate 193i 41.9nm 17.5nm 18.7nm Trench shrink for cutmask 20.0LS 66.1nm 19.9nm 19.8nm Hole shrink Hole multiplication 11.8LS For Via, Contact 63nm 63nm 63nm 14nmΦ 63nm 11

12 Cut Pattern Formation Healing & Shrinking Min 63nm pitch in immersion PR SiARC SOC TEOS In-situ polymer deposition thru-etching SiARC etch SOC etch Oxide etch Ashing 63nm 63nm 63nm 14nmΦ 63nm 12

13 Cut Pattern Formation Healing & Shrinking EL (%) Nominal dose best focus Under dose defocus Process Window ADI (49.3nm±10%) AEI (31.2m±10%) DOF (nm) CER (nm) Hole CD Healing CDU 15.5nm (3sig) CER 3.6nm hole CD(nm) nm nm Placement error Y (nm) Placement Error ADI Placement error X (nm) 8 Placement error Y (nm) 6 Design based AEI Placement error X (nm) EL: 60% enlarged DOF: 34% enlarged CDU: 80% improved CER: 70% improved *CER: Circle Edge Roughness Keep Placement Error TEL healing & shrinking improves overall process variability 13

14 \ EUV Patterning Waiting for the Light 14

15 Pattern Collapse Mitigation at 22nm HP Process Condition Exposure tool: NXE3100 Resist: ESR1 Process: 2.38% TMAH DIW rinse Surfactant rinse DIW (ref.) FIRM Extreme TM FIRM Extreme TM A Process Window Count Resolution Limit (nm) Sensitivity at 22nm (mj/cm2) LWR at 22nm (nm) Pattern Size 22nm Half pitch (Top-Down SEM Image) Resolution and LER improvement achieved using surfactant rinse FIRM Extreme A FIRM Extreme is a trademark of Merck Performance Materials 15

16 CLEAN TRACK LWR & CER Improvement 70nm pitch/ line and space 64nm pitch/ line and space 56nm pitch/ line and space 44nm pitch/ line and space 64nm pitch/ contact hole Presmoothing LWR 5.20nm LWR 4.42nm LWR 5.48nm LWR 7.03nm CER 1.84nm Postsmoothing LWR 4.66nm LWR 3.90nm LWR 4.74nm LWR 6.23nm CER 1.59nm 10.3% Improved 11.8% Improved 13.5% Improved 11.3% Improved 13.8% Improved TEL Jun Sung Chun / SEMATECH et. al, SPIE2014 TEL vapor phase smoothing process can improve LWR and CER 16

17 Etch Hardening & LER Improvement Post Litho CD 29nm No Cure CD 38nm Post Etch w/cure CD 37nm 13.5nm EUV Resist Base FTIR Data for cured & un-cured resist LER 2.9nm LER 2.2nm LER 1.8nm CD 63nm CD 52nm CD 53nm LER 3.5nm LER 2.9nm LER 2.5nm VUV cure can modify chemical structure of EUV resist leading to smoothing ~ 20-30% improvement in roughness for optimized cure process as compared to non-cure 17

18 DSA Patterning Order From Chaos Self-Aligned L/S Pitch Multiplication Self-Aligned Hole Pitch Multiplication Simple Pitch Multiplication with CDU/LWR Self-Healing 18

19 DSA Hole Shrink Process Flow Hole Guide Affinity Control BCP Coat & Bake PMMA Wet Dev. Negative tone resist pattern Affinity control processes to change template surface properties Wet development removes PMMA core 19

20 Champion Hole Defectivity 2015 CLEAN TRACK LITHIUS Pro Z DSA Normalized Defect Density Others 39% DSA Failure 9% On Material 25% Missing Hole 27% Q1/13 Q2/13 Q4/13 Q1/14 Q3/14 Missing Hole Large Material Small Material Embedded DSA Failure Line Signature Others 20

21 DSA Etch Overall Process Optimization Position Center Right Middle Right Edge Effect of HF RF Power LER LWR Selectivity CD-SEM Square scan 300K CD: 21.5nm LWR: 1.84nm LER: 1.79nm CD: 21.9nm LWR: 1.94nm LER: 2.07nm CD: 21.6nm LWR: 2.11nm LER: 1.98nm LER, LWR [nm] Selectivity X-SEM SiARC remain: 15.5nm Btm CD: 23.5nm SiARC remain: 20.9nm Btm CD: 25.1nm SiARC remain: 13.7nm Btm CD: 24.3nm HF Source Power [W] Effect of Ion Energy LER LWR Selectivity 6.0 Simultaneous optimization of CDU, LER, and selectivity achieved LER, LWR [nm] Selectivity Vpp [V] 21

22 Crossroads or Converging Paths? 22

23 Summary New drivers for increased computing power and storage continue to demand new semiconductor technologies Traditional scaling is at an inflection point, requiring new innovation to enable cost effective patterning solutions Developing these innovations requires partnership between customers, consortia, and suppliers TEL is ready to support all patterning technologies 23

24 What path do you want to follow? TEL Patterning Solutions 謝謝 TM 24

25 Acknowledgements Semiconductor companies collaborations Consortia (EIDEC, IMEC, SEMATECH) Material suppliers (Merck, TOK) Equipment suppliers (ASML, HHT, KLA-Tencor) TEL global technology teams (PSP, TDC, ATG, TTCA) Co-authors Hidetami Yaegashi Kenichi Oyama Takashi Hayakawa Takahiro Kitano Makoto Muramatsu Kousuke Yoshihara Satoru Shimura Shinichiro Kawakami Toshikatsu Tobana Mark Somervell Carlos Fonseca Ben Rathsack Anton devilliers Serge Biesmans Omar Madrigal Samuel House Rob Crowell Nagisa Sato Ken Nawa Koichi Yatsuda Seiji Fujimoto Noritaka Yokomori Hideo Nakashima Seiji Nagahara Hiroyuki Iwaki Akihiro Sonoda TEL is a trademark of Tokyo Electron Limited. steven1.scheer@tel.com 25